index
:
test/novena_base
coretest_hashes
master
sha256_core
trng
Cryptech Novena FPGA baseline
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
2015-02-01
Added header with license and info to the constraint file.
Joachim Strömbergson
2015-02-01
Updated README with more info about the base.
Joachim Strömbergson
2015-02-01
Changed file type.
Joachim Strömbergson
2015-02-01
Added proper file headers to all verilog source files.
Joachim Strömbergson
2015-02-01
Removed trailing whitespace and ^M.
Joachim Strömbergson
2015-02-01
Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.
Joachim Strömbergson
2015-02-01
Removed trailing whitespace and DOS ^M.
Joachim Strömbergson
2015-01-31
Adding license for the project.
Joachim Strömbergson
2015-01-31
Adding all main hw source files and constraints.
Joachim Strömbergson
2015-01-31
Removed exe bit on source files.
Joachim Strömbergson
2015-01-31
Adding initial version of the sw parts of the baseline.
Joachim Strömbergson
2015-01-31
Adding documentation.
Joachim Strömbergson
2015-01-31
Adding readme to explain the contents of the new repo.
Joachim Strömbergson