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-rw-r--r--rtl/src/verilog/cipher_selector.v19
-rw-r--r--rtl/src/verilog/eim_memory.v2
-rw-r--r--rtl/src/verilog/hash_selector.v (renamed from rtl/src/verilog/core_selector.v)59
3 files changed, 37 insertions, 43 deletions
diff --git a/rtl/src/verilog/cipher_selector.v b/rtl/src/verilog/cipher_selector.v
index ea18e14..8eead4b 100644
--- a/rtl/src/verilog/cipher_selector.v
+++ b/rtl/src/verilog/cipher_selector.v
@@ -2,15 +2,12 @@
//
// cipher_selector.v
// -----------------
-// Top level wrapper that creates the Cryptech coretest system.
-// The wrapper contains instances of external interface, coretest
-// and the core to be tested. And if more than one core is
-// present the wrapper also includes address and data muxes.
+// Selector for cipher cores.
//
//
// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
-//
+//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
@@ -58,16 +55,16 @@ module cipher_selector
//
reg [31: 0] tmp_read_data;
assign sys_read_data = tmp_read_data;
-
+
/* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
* to prevent ISE from complaining that we don't use input ports.
*/
-
+
reg [31: 0] reg_dummy_first;
reg [31: 0] reg_dummy_second;
reg [31: 0] reg_dummy_third;
-
+
always @(posedge sys_clk)
//
if (sys_rst)
@@ -108,10 +105,10 @@ module cipher_selector
end
//
end
-
-endmodule
+
+endmodule // cipher_selector
//======================================================================
-// EOF core_selector.v
+// EOF cipher_selector.v
//======================================================================
diff --git a/rtl/src/verilog/eim_memory.v b/rtl/src/verilog/eim_memory.v
index 953cff3..60ca57f 100644
--- a/rtl/src/verilog/eim_memory.v
+++ b/rtl/src/verilog/eim_memory.v
@@ -109,7 +109,7 @@ module eim_memory
// EIM address space and select which core to send EIM read and
// write operations to.
//----------------------------------------------------------------
- core_selector segment_cores
+ hash_selector segment_hashes
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/hash_selector.v
index 093830a..3d7e05f 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/hash_selector.v
@@ -1,16 +1,13 @@
//======================================================================
//
-// core_selector.v
+// hash_selector.v
// ---------------
-// Top level wrapper that creates the Cryptech coretest system.
-// The wrapper contains instances of external interface, coretest
-// and the core to be tested. And if more than one core is
-// present the wrapper also includes address and data muxes.
+// Core selector for hash cores.
//
//
// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
-//
+//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
@@ -39,7 +36,7 @@
//
//======================================================================
-module core_selector
+module hash_selector
(
input wire sys_clk,
input wire sys_rst,
@@ -52,7 +49,7 @@ module core_selector
input wire [31 : 0] sys_write_data
);
-
+
/* In this memory segment (HASHES) we have 14 address bits. Every core has
* 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here.
*
@@ -62,7 +59,7 @@ module core_selector
*
* So far we have three cores: SHA-1, SHA-256 and SHA-512.
*/
-
+
/*********************************************************
* To add new HASH core named XXX follow the steps below *
*********************************************************
@@ -125,15 +122,15 @@ module core_selector
/* We can comment following lines to exclude cores from implementation
* in case we run out of slices.
*/
-
- //----------------------------------------------------------------
- // List of Available Cores
- //----------------------------------------------------------------
- `define USE_CORE_SHA1
- `define USE_CORE_SHA256
- `define USE_CORE_SHA512
-
-
+
+ //----------------------------------------------------------------
+ // List of Available Cores
+ //----------------------------------------------------------------
+ // `define USE_CORE_SHA1
+ // `define USE_CORE_SHA256
+ // `define USE_CORE_SHA512
+
+
//----------------------------------------------------------------
// Core Address Table
//----------------------------------------------------------------
@@ -141,8 +138,8 @@ module core_selector
localparam CORE_ADDR_SHA1 = 6'd1;
localparam CORE_ADDR_SHA256 = 6'd2;
localparam CORE_ADDR_SHA512 = 6'd3;
-
-
+
+
//----------------------------------------------------------------
// Global Registers
//----------------------------------------------------------------
@@ -160,8 +157,8 @@ module core_selector
.write_data(sys_write_data),
.read_data(read_data_global)
);
-
-
+
+
//----------------------------------------------------------------
// SHA-1
//----------------------------------------------------------------
@@ -181,8 +178,8 @@ module core_selector
.read_data(read_data_sha1)
);
`endif
-
-
+
+
//----------------------------------------------------------------
// SHA-256
//----------------------------------------------------------------
@@ -202,8 +199,8 @@ module core_selector
.read_data(read_data_sha256)
);
`endif
-
-
+
+
//----------------------------------------------------------------
// SHA-512
//----------------------------------------------------------------
@@ -223,14 +220,14 @@ module core_selector
.read_data(read_data_sha512)
);
`endif
-
-
+
+
//----------------------------------------------------------------
// Output (Read Data) Multiplexor
//----------------------------------------------------------------
reg [31: 0] sys_read_data_mux;
assign sys_read_data = sys_read_data_mux;
-
+
always @*
//
case (addr_core_num)
@@ -256,8 +253,8 @@ module core_selector
endcase
-endmodule
+endmodule // hash_selector
//======================================================================
-// EOF core_selector.v
+// EOF hash_selector.v
//======================================================================