diff options
Diffstat (limited to 'rtl/src/verilog/novena_baseline_top.v')
| -rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 3499fa3..4bf1fdb 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -56,12 +56,12 @@ module novena_baseline_top input wire eim_bclk, // EIM burst clock. Started by the CPU. input wire eim_cs0_n, // Chip select (active low). inout wire [15 : 0] eim_da, // Bidirectional address and data port. - input wire [18: 16] eim_a, // MSB part of address port. + input wire [18: 16] eim_a, // MSB part of address port. input wire eim_lba_n, // Latch address signal (active low). input wire eim_wr_n, // write enable signal (active low). input wire eim_oe_n, // output enable signal (active low). output wire eim_wait_n, // Data wait signal (active low). - + // Novena utility ports apoptosis_pin, // Hold low to not restart after config. led_pin // LED on edge close to the FPGA. @@ -137,13 +137,16 @@ module novena_baseline_top .sys_clk(sys_clk), .sys_rst(sys_rst), + .noise(ct_noise), + .noise_led(ct_led), + .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_eim_dout), .sys_read_data(sys_eim_din) - ); + ); //---------------------------------------------------------------- @@ -160,16 +163,6 @@ module novena_baseline_top .led_out(led_pin) ); - - //---------------------------------------------------------------- - // Cryptech Logic - // - // Logic specific to the Cryptech use of the Novena. - // Currently we just hard wire the LED outputs. - //---------------------------------------------------------------- - assign ct_led = {8{ct_noise}}; - - //---------------------------------------------------------------- // Novena Patch // |