diff options
| -rw-r--r-- | rtl/src/verilog/cdc_bus_pulse.v | 216 | ||||
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 220 | ||||
| -rw-r--r-- | rtl/src/verilog/eim_arbiter.v | 486 | ||||
| -rw-r--r-- | rtl/src/verilog/eim_da_phy.v | 72 | ||||
| -rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 208 | ||||
| -rw-r--r-- | rtl/src/verilog/novena_clkmgr.v | 162 |
6 files changed, 682 insertions, 682 deletions
diff --git a/rtl/src/verilog/cdc_bus_pulse.v b/rtl/src/verilog/cdc_bus_pulse.v index 104bfa5..631506c 100644 --- a/rtl/src/verilog/cdc_bus_pulse.v +++ b/rtl/src/verilog/cdc_bus_pulse.v @@ -1,114 +1,114 @@ -`timescale 1ns / 1ps
-
-module cdc_bus_pulse
- (
- src_clk, src_din, src_req,
- dst_clk, dst_dout, dst_pulse
- );
-
- /* This module is based on design suggested on page 27 of an article titled
- "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog"
- by Clifford E. Cummings (Sunburst Design, Inc.)
- */
-
- //
- // Parameters
- //
- parameter DATA_WIDTH = 32; // width of data bus
-
-
- //
- // Ports
- //
- input wire src_clk; // source domain clock
- input wire [DATA_WIDTH-1:0] src_din; // data from source clock domain
- input wire src_req; // start transfer pulse from source clock domain
-
- input wire dst_clk; // destination domain clock
- output wire [DATA_WIDTH-1:0] dst_dout; // data to destination clock domain
- output wire dst_pulse; // transfer done pulse to destination clock domain
-
-
- //
- // Source Side Registers
- //
- reg src_ff = 1'b0; // transfer request flag
- reg [DATA_WIDTH-1:0] src_latch = {DATA_WIDTH{1'bX}}; // source data buffer
-
-
- //
- // Source Request Handler
- //
- always @(posedge src_clk)
- //
- if (src_req) begin // transfer request pulse?
- src_ff <= ~src_ff; // toggle transfer request flag...
- src_latch <= src_din; // ... and capture data in source buffer
- end
-
-
- //
- // Source -> Destination Flag Sync Logic
- //
-
- /* ISE may decide to infer SRL here, so we explicitly instantiate slice registers. */
-
- wire flag_sync_first; // first FF output
- wire flag_sync_second; // second FF output
- wire flag_sync_third; // third FF output
- wire flag_sync_pulse; // flag toggle detector output
-
- FDCE ff_sync_first
- (
- .C (dst_clk),
+`timescale 1ns / 1ps + +module cdc_bus_pulse + ( + src_clk, src_din, src_req, + dst_clk, dst_dout, dst_pulse + ); + + /* This module is based on design suggested on page 27 of an article titled + "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog" + by Clifford E. Cummings (Sunburst Design, Inc.) + */ + + // + // Parameters + // + parameter DATA_WIDTH = 32; // width of data bus + + + // + // Ports + // + input wire src_clk; // source domain clock + input wire [DATA_WIDTH-1:0] src_din; // data from source clock domain + input wire src_req; // start transfer pulse from source clock domain + + input wire dst_clk; // destination domain clock + output wire [DATA_WIDTH-1:0] dst_dout; // data to destination clock domain + output wire dst_pulse; // transfer done pulse to destination clock domain + + + // + // Source Side Registers + // + reg src_ff = 1'b0; // transfer request flag + reg [DATA_WIDTH-1:0] src_latch = {DATA_WIDTH{1'bX}}; // source data buffer + + + // + // Source Request Handler + // + always @(posedge src_clk) + // + if (src_req) begin // transfer request pulse? + src_ff <= ~src_ff; // toggle transfer request flag... + src_latch <= src_din; // ... and capture data in source buffer + end + + + // + // Source -> Destination Flag Sync Logic + // + + /* ISE may decide to infer SRL here, so we explicitly instantiate slice registers. */ + + wire flag_sync_first; // first FF output + wire flag_sync_second; // second FF output + wire flag_sync_third; // third FF output + wire flag_sync_pulse; // flag toggle detector output + + FDCE ff_sync_first + ( + .C (dst_clk), .D (src_ff), // capture flag from another clock domain - .Q (flag_sync_first), // metastability can occur here
- .CLR (1'b0),
+ .Q (flag_sync_first), // metastability can occur here + .CLR (1'b0), .CE (1'b1) - );
- FDCE ff_sync_second
- (
- .C (dst_clk),
+ ); + FDCE ff_sync_second + ( + .C (dst_clk), .D (flag_sync_first), // synchronize captured flag to remove metastability - .Q (flag_sync_second), // and pass it to another flip-flop
- .CLR (1'b0),
+ .Q (flag_sync_second), // and pass it to another flip-flop + .CLR (1'b0), .CE (1'b1) - );
- FDCE ff_sync_third
- (
- .C (dst_clk),
+ ); + FDCE ff_sync_third + ( + .C (dst_clk), .D (flag_sync_second), // delay synchronized flag in another flip-flip, because we need - .Q (flag_sync_third), // two synchronized flag values (current and delayed) to detect its change
- .CLR (1'b0),
+ .Q (flag_sync_third), // two synchronized flag values (current and delayed) to detect its change + .CLR (1'b0), .CE (1'b1) - );
-
- // when delayed flag value differs from its current value, it was changed
- // by the source side, so there must have been a transfer request
- assign flag_sync_pulse = flag_sync_second ^ flag_sync_third;
-
-
- //
- // Destination Side Registers
- //
- reg dst_pulse_reg = 1'b0; // transfer done flag
- reg [DATA_WIDTH-1:0] dst_latch = {DATA_WIDTH{1'bX}}; // destination data buffer
-
- assign dst_pulse = dst_pulse_reg;
- assign dst_dout = dst_latch;
-
- //
- // Destination Request Handler
- //
- always @(posedge dst_clk) begin
- //
- dst_pulse_reg <= flag_sync_pulse; // generate pulse if flag change was detected
- //
- if (flag_sync_pulse) dst_latch <= src_latch; // by the time destination side receives synchronized
- // // flag value, data should be stable, we can safely
- // // capture and store it in the destination buffer
- //
- end
-
-
-endmodule
+ ); + + // when delayed flag value differs from its current value, it was changed + // by the source side, so there must have been a transfer request + assign flag_sync_pulse = flag_sync_second ^ flag_sync_third; + + + // + // Destination Side Registers + // + reg dst_pulse_reg = 1'b0; // transfer done flag + reg [DATA_WIDTH-1:0] dst_latch = {DATA_WIDTH{1'bX}}; // destination data buffer + + assign dst_pulse = dst_pulse_reg; + assign dst_dout = dst_latch; + + // + // Destination Request Handler + // + always @(posedge dst_clk) begin + // + dst_pulse_reg <= flag_sync_pulse; // generate pulse if flag change was detected + // + if (flag_sync_pulse) dst_latch <= src_latch; // by the time destination side receives synchronized + // // flag value, data should be stable, we can safely + // // capture and store it in the destination buffer + // + end + + +endmodule diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 2db2a05..eb6551a 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,112 +1,112 @@ -`timescale 1ns / 1ps
-
-module core_selector
- (
- sys_clk, sys_rst,
+`timescale 1ns / 1ps + +module core_selector + ( + sys_clk, sys_rst, sys_eim_addr, sys_eim_wr, sys_eim_rd, - sys_eim_dout, sys_eim_din
- );
-
- //
- // Ports
- //
- input wire sys_clk;
- input wire sys_rst;
-
- input wire [13: 0] sys_eim_addr;
- input wire sys_eim_wr;
+ sys_eim_dout, sys_eim_din + ); + + // + // Ports + // + input wire sys_clk; + input wire sys_rst; + + input wire [13: 0] sys_eim_addr; + input wire sys_eim_wr; input wire sys_eim_rd; - input wire [31: 0] sys_eim_dout;
- output wire [31: 0] sys_eim_din;
-
-
- //
- // Internal Registers
- //
- reg [31: 0] reg_x = {32{1'b0}};
- reg [31: 0] reg_y = {32{1'b0}};
- reg [15: 0] reg_ctl = {16{1'b0}};
- reg [31: 0] sys_eim_din_reg = {32{1'b0}};
-
-
- //
- // Parameters
- //
- localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address
- localparam ADDER_OFFSET_REG_X = 2'd0; // X
- localparam ADDER_OFFSET_REG_Y = 2'd1; // Y
- localparam ADDER_OFFSET_REG_Z = 2'd2; // Z
- localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL}
-
-
- /* This flag detects whether adder core is being addressed. */
- wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
-
- /* These flags detect whether write or read access is requested. */
- wire eim_access_write = sys_eim_wr & eim_access_adder;
- wire eim_access_read = sys_eim_rd & eim_access_adder;
-
-
- //
- // Write Request Handler
- //
- always @(posedge sys_clk)
- //
- if (sys_rst) begin
- reg_x <= {32{1'b0}};
- reg_y <= {32{1'b0}};
- reg_ctl <= {16{1'b0}};
- end else if (eim_access_write) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout;
- ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout;
- ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0];
- endcase
- //
- end
-
-
- //
- // Read Request Handler
- //
- wire [31: 0] reg_z;
- wire [15: 0] reg_sts;
-
- always @(posedge sys_clk)
- //
- if (sys_rst) sys_eim_din_reg <= {32{1'b0}};
- //
- else if (eim_access_read) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x;
- ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y;
- ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z;
- ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl};
- endcase
- //
- end
-
- assign sys_eim_din = sys_eim_din_reg;
-
-
- //
- // Demo Adder Core
- //
- demo_adder adder_core
- (
- .clk (sys_clk),
- .rst (sys_rst),
-
- .x (reg_x),
- .y (reg_y),
- .z (reg_z),
-
- .ctl (reg_ctl),
- .sts (reg_sts)
- );
-
-
-
-endmodule
+ input wire [31: 0] sys_eim_dout; + output wire [31: 0] sys_eim_din; + + + // + // Internal Registers + // + reg [31: 0] reg_x = {32{1'b0}}; + reg [31: 0] reg_y = {32{1'b0}}; + reg [15: 0] reg_ctl = {16{1'b0}}; + reg [31: 0] sys_eim_din_reg = {32{1'b0}}; + + + // + // Parameters + // + localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address + localparam ADDER_OFFSET_REG_X = 2'd0; // X + localparam ADDER_OFFSET_REG_Y = 2'd1; // Y + localparam ADDER_OFFSET_REG_Z = 2'd2; // Z + localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL} + + + /* This flag detects whether adder core is being addressed. */ + wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; + + /* These flags detect whether write or read access is requested. */ + wire eim_access_write = sys_eim_wr & eim_access_adder; + wire eim_access_read = sys_eim_rd & eim_access_adder; + + + // + // Write Request Handler + // + always @(posedge sys_clk) + // + if (sys_rst) begin + reg_x <= {32{1'b0}}; + reg_y <= {32{1'b0}}; + reg_ctl <= {16{1'b0}}; + end else if (eim_access_write) begin + // + case (sys_eim_addr[1:0]) + ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout; + ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout; + ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0]; + endcase + // + end + + + // + // Read Request Handler + // + wire [31: 0] reg_z; + wire [15: 0] reg_sts; + + always @(posedge sys_clk) + // + if (sys_rst) sys_eim_din_reg <= {32{1'b0}}; + // + else if (eim_access_read) begin + // + case (sys_eim_addr[1:0]) + ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x; + ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y; + ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z; + ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl}; + endcase + // + end + + assign sys_eim_din = sys_eim_din_reg; + + + // + // Demo Adder Core + // + demo_adder adder_core + ( + .clk (sys_clk), + .rst (sys_rst), + + .x (reg_x), + .y (reg_y), + .z (reg_z), + + .ctl (reg_ctl), + .sts (reg_sts) + ); + + + +endmodule diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v index 247ff69..1e39629 100644 --- a/rtl/src/verilog/eim_arbiter.v +++ b/rtl/src/verilog/eim_arbiter.v @@ -1,247 +1,247 @@ -`timescale 1ns / 1ps
-
-module eim_arbiter
- (
+`timescale 1ns / 1ps + +module eim_arbiter + ( eim_bclk, eim_cs0_n, eim_da, eim_lba_n, eim_wr_n, - eim_oe_n, eim_wait_n,
-
- sys_clk,
- sys_addr,
- sys_wren, sys_data_out,
- sys_rden, sys_data_in
- );
-
-
- //
- // Ports
- //
- input wire eim_bclk; // | eim bus
- input wire eim_cs0_n; // |
+ eim_oe_n, eim_wait_n, + + sys_clk, + sys_addr, + sys_wren, sys_data_out, + sys_rden, sys_data_in + ); + + + // + // Ports + // + input wire eim_bclk; // | eim bus + input wire eim_cs0_n; // | inout wire [15: 0] eim_da; // | - input wire eim_lba_n; // |
+ input wire eim_lba_n; // | input wire eim_wr_n; // | - input wire eim_oe_n; // |
- output wire eim_wait_n; // |
-
- input wire sys_clk; // system clock
-
- output wire [13: 0] sys_addr; // | user bus
- output wire sys_wren; // |
- output wire [31: 0] sys_data_out; // |
- output wire sys_rden; // |
- input wire [31: 0] sys_data_in; // |
-
-
- //
- // Data/Address PHY
- //
-
- /* PHY is needed to control bi-directional address/data bus. */
-
- wire [15: 0] da_ro; // value read from pins
- reg [15: 0] da_di; // value drives onto pins
-
- eim_da_phy da_phy
- (
- .buf_io (eim_da), // <-- connect directly top-level port
- .buf_di (da_di),
- .buf_ro (da_ro),
- .buf_t (eim_oe_n) // <-- driven by EIM directly
- );
-
-
- //
- // FSM
- //
- localparam EIM_FSM_STATE_INIT = 5'b0_0_000; // arbiter is idle
-
- localparam EIM_FSM_STATE_WRITE_START = 5'b1_1_000; // got address to write at
- localparam EIM_FSM_STATE_WRITE_LSB = 5'b1_1_001; // got lower 16 bits of data to write
- localparam EIM_FSM_STATE_WRITE_MSB = 5'b1_1_010; // got upper 16 bits of data to write
- localparam EIM_FSM_STATE_WRITE_WAIT = 5'b1_1_100; // request to user-side logic sent
- localparam EIM_FSM_STATE_WRITE_DONE = 5'b1_1_111; // user-side logic acknowledged transaction
-
- localparam EIM_FSM_STATE_READ_START = 5'b1_0_000; // got address to read from
- localparam EIM_FSM_STATE_READ_WAIT = 5'b1_0_100; // request to user-side logic sent
- localparam EIM_FSM_STATE_READ_READY = 5'b1_0_011; // got acknowledge from user logic
- localparam EIM_FSM_STATE_READ_LSB = 5'b1_0_001; // returned lower 16 bits to master
- localparam EIM_FSM_STATE_READ_MSB = 5'b1_0_010; // returned upper 16 bits to master
- localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete
-
- reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state
- reg [13: 0] eim_addr_latch = {14{1'bX}}; // transaction address
- reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write
-
- /* These flags are used to wake up from INIT state. */
- wire eim_write_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b0) && (da_ro[1:0] == 2'b00);
- wire eim_read_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b1) && (da_ro[1:0] == 2'b00);
-
- /* These are transaction response flag and data from user-side logic. */
- wire eim_user_ack;
- wire [31: 0] eim_user_data;
-
- /* FSM is reset whenever Chip Select is de-asserted. */
-
- //
- // FSM Transition Logic
- //
- always @(posedge eim_bclk or posedge eim_cs0_n) begin
- //
- if (eim_cs0_n == 1'b1) eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- else begin
- //
- case (eim_fsm_state)
- //
- // INIT -> WRITE, INIT -> READ
- //
- EIM_FSM_STATE_INIT: begin
- if (eim_write_start_flag) eim_fsm_state <= EIM_FSM_STATE_WRITE_START;
- if (eim_read_start_flag) eim_fsm_state <= EIM_FSM_STATE_READ_START;
- end
- //
- // WRITE
- //
- EIM_FSM_STATE_WRITE_START: eim_fsm_state <= EIM_FSM_STATE_WRITE_LSB;
- //
- EIM_FSM_STATE_WRITE_LSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_MSB;
- //
- EIM_FSM_STATE_WRITE_MSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_WAIT;
- //
- EIM_FSM_STATE_WRITE_WAIT:
- if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_WRITE_DONE;
- //
- EIM_FSM_STATE_WRITE_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- // READ
- //
- EIM_FSM_STATE_READ_START: eim_fsm_state <= EIM_FSM_STATE_READ_WAIT;
- //
- EIM_FSM_STATE_READ_WAIT:
- if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_READ_READY;
- //
- EIM_FSM_STATE_READ_READY: eim_fsm_state <= EIM_FSM_STATE_READ_LSB;
- //
- EIM_FSM_STATE_READ_LSB: eim_fsm_state <= EIM_FSM_STATE_READ_MSB;
- //
- EIM_FSM_STATE_READ_MSB: eim_fsm_state <= EIM_FSM_STATE_READ_DONE;
- //
- EIM_FSM_STATE_READ_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- //
- //
- default: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- endcase
- //
- end
- //
- end
-
-
- //
- // Address Latch
- //
- always @(posedge eim_bclk)
- //
- if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag))
- eim_addr_latch <= da_ro[15:2];
-
-
- //
- // Additional Write Logic
- //
- always @(posedge eim_bclk)
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_START)
- eim_write_lsb_latch <= da_ro;
-
-
- //
- // Additional Read Logic
- //
-
- /* Note that this stuff operates on falling clock edge, because the cpu
- * samples our bi-directional data bus on rising clock edge.
- */
-
- always @(negedge eim_bclk or posedge eim_cs0_n)
- //
- if (eim_cs0_n == 1'b1) da_di <= {16{1'bX}}; // don't care what to drive
- else begin
- //
- if (eim_fsm_state == EIM_FSM_STATE_READ_LSB) da_di <= eim_user_data[15: 0]; // drive lower 16 bits at first...
- if (eim_fsm_state == EIM_FSM_STATE_READ_MSB) da_di <= eim_user_data[31:16]; // ...then drive upper 16 bits
- //
- end
-
-
- //
- // Wait Logic
- //
-
- /* Note that this stuff operates on falling clock edge, because the cpu
- * samples our WAIT_N flag on rising clock edge.
- */
-
- reg eim_wait_reg = 1'b0;
-
- always @(negedge eim_bclk or posedge eim_cs0_n)
- //
- if (eim_cs0_n == 1'b1) eim_wait_reg <= 1'b0; // clear wait
- else begin
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_START) eim_wait_reg <= 1'b1; // start waiting for write to complete
- if (eim_fsm_state == EIM_FSM_STATE_READ_START) eim_wait_reg <= 1'b1; // start waiting for read to complete
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_DONE) eim_wait_reg <= 1'b0; // write transaction done
- if (eim_fsm_state == EIM_FSM_STATE_READ_READY) eim_wait_reg <= 1'b0; // read transaction done
- //
- if (eim_fsm_state == EIM_FSM_STATE_INIT) eim_wait_reg <= 1'b0; // fsm is idle, no need to wait any more
- //
- end
-
- assign eim_wait_n = ~eim_wait_reg;
-
-
- /* These flags are used to generate 1-cycle pulses to trigger CDC transaction.
- * Note that FSM goes from WRITE_LSB to WRITE_MSB and from READ_START to READ_WAIT
- * unconditionally, so these flags will always be active for 1 cycle only, which
- * is exactly what we need.
- */
-
- wire arbiter_write_req_pulse = (eim_fsm_state == EIM_FSM_STATE_WRITE_LSB) ? 1'b1 : 1'b0;
- wire arbiter_read_req_pulse = (eim_fsm_state == EIM_FSM_STATE_READ_START) ? 1'b1 : 1'b0;
-
- //
- // CDC Block
- //
-
- /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and
- * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+14+32 = 48 bits
- * are transfered, these are: write flag, read flag, address, write data. During read transaction
- * some bogus write data is passed, which is not used later anyway. During read requests 32 bits of data
- * are returned, during write requests 32 bits of bogus data are returned, that are never used later.
- */
-
- eim_arbiter_cdc eim_cdc
- (
- .eim_clk (eim_bclk),
-
- .eim_req (arbiter_write_req_pulse | arbiter_read_req_pulse),
- .eim_ack (eim_user_ack),
-
- .eim_din ({arbiter_write_req_pulse, arbiter_read_req_pulse, eim_addr_latch, da_ro, eim_write_lsb_latch}),
- .eim_dout (eim_user_data),
-
- .sys_clk (sys_clk),
- .sys_addr (sys_addr),
- .sys_wren (sys_wren),
- .sys_data_out (sys_data_out),
- .sys_rden (sys_rden),
- .sys_data_in (sys_data_in)
- );
-
-
-endmodule
+ input wire eim_oe_n; // | + output wire eim_wait_n; // | + + input wire sys_clk; // system clock + + output wire [13: 0] sys_addr; // | user bus + output wire sys_wren; // | + output wire [31: 0] sys_data_out; // | + output wire sys_rden; // | + input wire [31: 0] sys_data_in; // | + + + // + // Data/Address PHY + // + + /* PHY is needed to control bi-directional address/data bus. */ + + wire [15: 0] da_ro; // value read from pins + reg [15: 0] da_di; // value drives onto pins + + eim_da_phy da_phy + ( + .buf_io (eim_da), // <-- connect directly top-level port + .buf_di (da_di), + .buf_ro (da_ro), + .buf_t (eim_oe_n) // <-- driven by EIM directly + ); + + + // + // FSM + // + localparam EIM_FSM_STATE_INIT = 5'b0_0_000; // arbiter is idle + + localparam EIM_FSM_STATE_WRITE_START = 5'b1_1_000; // got address to write at + localparam EIM_FSM_STATE_WRITE_LSB = 5'b1_1_001; // got lower 16 bits of data to write + localparam EIM_FSM_STATE_WRITE_MSB = 5'b1_1_010; // got upper 16 bits of data to write + localparam EIM_FSM_STATE_WRITE_WAIT = 5'b1_1_100; // request to user-side logic sent + localparam EIM_FSM_STATE_WRITE_DONE = 5'b1_1_111; // user-side logic acknowledged transaction + + localparam EIM_FSM_STATE_READ_START = 5'b1_0_000; // got address to read from + localparam EIM_FSM_STATE_READ_WAIT = 5'b1_0_100; // request to user-side logic sent + localparam EIM_FSM_STATE_READ_READY = 5'b1_0_011; // got acknowledge from user logic + localparam EIM_FSM_STATE_READ_LSB = 5'b1_0_001; // returned lower 16 bits to master + localparam EIM_FSM_STATE_READ_MSB = 5'b1_0_010; // returned upper 16 bits to master + localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete + + reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state + reg [13: 0] eim_addr_latch = {14{1'bX}}; // transaction address + reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write + + /* These flags are used to wake up from INIT state. */ + wire eim_write_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b0) && (da_ro[1:0] == 2'b00); + wire eim_read_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b1) && (da_ro[1:0] == 2'b00); + + /* These are transaction response flag and data from user-side logic. */ + wire eim_user_ack; + wire [31: 0] eim_user_data; + + /* FSM is reset whenever Chip Select is de-asserted. */ + + // + // FSM Transition Logic + // + always @(posedge eim_bclk or posedge eim_cs0_n) begin + // + if (eim_cs0_n == 1'b1) eim_fsm_state <= EIM_FSM_STATE_INIT; + // + else begin + // + case (eim_fsm_state) + // + // INIT -> WRITE, INIT -> READ + // + EIM_FSM_STATE_INIT: begin + if (eim_write_start_flag) eim_fsm_state <= EIM_FSM_STATE_WRITE_START; + if (eim_read_start_flag) eim_fsm_state <= EIM_FSM_STATE_READ_START; + end + // + // WRITE + // + EIM_FSM_STATE_WRITE_START: eim_fsm_state <= EIM_FSM_STATE_WRITE_LSB; + // + EIM_FSM_STATE_WRITE_LSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_MSB; + // + EIM_FSM_STATE_WRITE_MSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_WAIT; + // + EIM_FSM_STATE_WRITE_WAIT: + if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_WRITE_DONE; + // + EIM_FSM_STATE_WRITE_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT; + // + // READ + // + EIM_FSM_STATE_READ_START: eim_fsm_state <= EIM_FSM_STATE_READ_WAIT; + // + EIM_FSM_STATE_READ_WAIT: + if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_READ_READY; + // + EIM_FSM_STATE_READ_READY: eim_fsm_state <= EIM_FSM_STATE_READ_LSB; + // + EIM_FSM_STATE_READ_LSB: eim_fsm_state <= EIM_FSM_STATE_READ_MSB; + // + EIM_FSM_STATE_READ_MSB: eim_fsm_state <= EIM_FSM_STATE_READ_DONE; + // + EIM_FSM_STATE_READ_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT; + // + // + // + default: eim_fsm_state <= EIM_FSM_STATE_INIT; + // + endcase + // + end + // + end + + + // + // Address Latch + // + always @(posedge eim_bclk) + // + if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag)) + eim_addr_latch <= da_ro[15:2]; + + + // + // Additional Write Logic + // + always @(posedge eim_bclk) + // + if (eim_fsm_state == EIM_FSM_STATE_WRITE_START) + eim_write_lsb_latch <= da_ro; + + + // + // Additional Read Logic + // + + /* Note that this stuff operates on falling clock edge, because the cpu + * samples our bi-directional data bus on rising clock edge. + */ + + always @(negedge eim_bclk or posedge eim_cs0_n) + // + if (eim_cs0_n == 1'b1) da_di <= {16{1'bX}}; // don't care what to drive + else begin + // + if (eim_fsm_state == EIM_FSM_STATE_READ_LSB) da_di <= eim_user_data[15: 0]; // drive lower 16 bits at first... + if (eim_fsm_state == EIM_FSM_STATE_READ_MSB) da_di <= eim_user_data[31:16]; // ...then drive upper 16 bits + // + end + + + // + // Wait Logic + // + + /* Note that this stuff operates on falling clock edge, because the cpu + * samples our WAIT_N flag on rising clock edge. + */ + + reg eim_wait_reg = 1'b0; + + always @(negedge eim_bclk or posedge eim_cs0_n) + // + if (eim_cs0_n == 1'b1) eim_wait_reg <= 1'b0; // clear wait + else begin + // + if (eim_fsm_state == EIM_FSM_STATE_WRITE_START) eim_wait_reg <= 1'b1; // start waiting for write to complete + if (eim_fsm_state == EIM_FSM_STATE_READ_START) eim_wait_reg <= 1'b1; // start waiting for read to complete + // + if (eim_fsm_state == EIM_FSM_STATE_WRITE_DONE) eim_wait_reg <= 1'b0; // write transaction done + if (eim_fsm_state == EIM_FSM_STATE_READ_READY) eim_wait_reg <= 1'b0; // read transaction done + // + if (eim_fsm_state == EIM_FSM_STATE_INIT) eim_wait_reg <= 1'b0; // fsm is idle, no need to wait any more + // + end + + assign eim_wait_n = ~eim_wait_reg; + + + /* These flags are used to generate 1-cycle pulses to trigger CDC transaction. + * Note that FSM goes from WRITE_LSB to WRITE_MSB and from READ_START to READ_WAIT + * unconditionally, so these flags will always be active for 1 cycle only, which + * is exactly what we need. + */ + + wire arbiter_write_req_pulse = (eim_fsm_state == EIM_FSM_STATE_WRITE_LSB) ? 1'b1 : 1'b0; + wire arbiter_read_req_pulse = (eim_fsm_state == EIM_FSM_STATE_READ_START) ? 1'b1 : 1'b0; + + // + // CDC Block + // + + /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and + * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+14+32 = 48 bits + * are transfered, these are: write flag, read flag, address, write data. During read transaction + * some bogus write data is passed, which is not used later anyway. During read requests 32 bits of data + * are returned, during write requests 32 bits of bogus data are returned, that are never used later. + */ + + eim_arbiter_cdc eim_cdc + ( + .eim_clk (eim_bclk), + + .eim_req (arbiter_write_req_pulse | arbiter_read_req_pulse), + .eim_ack (eim_user_ack), + + .eim_din ({arbiter_write_req_pulse, arbiter_read_req_pulse, eim_addr_latch, da_ro, eim_write_lsb_latch}), + .eim_dout (eim_user_data), + + .sys_clk (sys_clk), + .sys_addr (sys_addr), + .sys_wren (sys_wren), + .sys_data_out (sys_data_out), + .sys_rden (sys_rden), + .sys_data_in (sys_data_in) + ); + + +endmodule diff --git a/rtl/src/verilog/eim_da_phy.v b/rtl/src/verilog/eim_da_phy.v index 9fe0c3b..9b76d3b 100644 --- a/rtl/src/verilog/eim_da_phy.v +++ b/rtl/src/verilog/eim_da_phy.v @@ -1,47 +1,47 @@ -`timescale 1ns / 1ps
-
-module eim_da_phy
- (
- buf_io,
- buf_di, buf_ro,
- buf_t
- );
-
- //
- // Parameters
- //
- parameter BUS_WIDTH = 16;
-
- //
- // Ports
- //
- inout wire [BUS_WIDTH-1:0] buf_io; // connect directly to top-level pins
- input wire [BUS_WIDTH-1:0] buf_di; // drive input (value driven onto pins)
- output wire [BUS_WIDTH-1:0] buf_ro; // receiver output (value read from pins)
- input wire buf_t; // tristate control (driver is disabled during tristate)
-
- //
- // IOBUFs
- //
+`timescale 1ns / 1ps + +module eim_da_phy + ( + buf_io, + buf_di, buf_ro, + buf_t + ); + + // + // Parameters + // + parameter BUS_WIDTH = 16; + + // + // Ports + // + inout wire [BUS_WIDTH-1:0] buf_io; // connect directly to top-level pins + input wire [BUS_WIDTH-1:0] buf_di; // drive input (value driven onto pins) + output wire [BUS_WIDTH-1:0] buf_ro; // receiver output (value read from pins) + input wire buf_t; // tristate control (driver is disabled during tristate) + + // + // IOBUFs + // genvar i; - generate for (i=0; i<BUS_WIDTH; i=i+1)
+ generate for (i=0; i<BUS_WIDTH; i=i+1) begin: eim_da - //
- IOBUF #
- (
+ // + IOBUF # + ( .IOSTANDARD ("LVCMOS33"), .DRIVE (12), .SLEW ("FAST") - )
- IOBUF_inst
- (
+ ) + IOBUF_inst + ( .IO (buf_io[i]), .O (buf_ro[i]), .I (buf_di[i]), .T (buf_t) - );
+ ); // end - endgenerate
-
-endmodule
+ endgenerate + +endmodule diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index a62f311..57ef434 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -1,7 +1,7 @@ -`timescale 1ns / 1ps
-
-module novena_baseline_top
- (
+`timescale 1ns / 1ps + +module novena_baseline_top + ( gclk_p_pin, gclk_n_pin, eim_bclk, eim_cs0_n, eim_da, @@ -10,13 +10,13 @@ module novena_baseline_top reset_mcu_b_pin, apoptosis_pin, - led_pin
- );
-
+ led_pin + ); + // // Top-Levl Ports // - input wire gclk_p_pin; // general-purpose 50 MHz LVDS clock + input wire gclk_p_pin; // general-purpose 50 MHz LVDS clock input wire gclk_n_pin; // input wire eim_bclk; // burst clock from cpu @@ -27,106 +27,106 @@ module novena_baseline_top input wire eim_oe_n; // output enable signal (active low) output wire eim_wait_n; // wait signal (active low) - input wire reset_mcu_b_pin; // this must be configured as input w/pullup
+ input wire reset_mcu_b_pin; // this must be configured as input w/pullup // not to kill the cpu after configuration output wire apoptosis_pin; // not used, tied to 0 - output wire led_pin; // visual activity indicator
-
-
- //
- // Clock Manager
- //
-
- /* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */
-
- wire sys_clk;
- wire sys_rst;
-
- wire eim_bclk_buf;
-
- novena_clkmgr clkmgr
- (
- .gclk_p (gclk_p_pin),
- .gclk_n (gclk_n_pin),
- - .reset_mcu_b (reset_mcu_b_pin),
- - .sys_clk (sys_clk),
- .sys_rst (sys_rst),
-
- .bclk_in (eim_bclk),
- .bclk_out (eim_bclk_buf)
- );
-
-
- //
- // EIM Arbiter
- //
-
- /* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */
-
+ output wire led_pin; // visual activity indicator + + + // + // Clock Manager + // + + /* Clock manager is used to buffer BCLK and also generate SYS_CLK from GCLK. */ + + wire sys_clk; + wire sys_rst; + + wire eim_bclk_buf; + + novena_clkmgr clkmgr + ( + .gclk_p (gclk_p_pin), + .gclk_n (gclk_n_pin), + + .reset_mcu_b (reset_mcu_b_pin), + + .sys_clk (sys_clk), + .sys_rst (sys_rst), + + .bclk_in (eim_bclk), + .bclk_out (eim_bclk_buf) + ); + + + // + // EIM Arbiter + // + + /* EIM arbiter handles EIM access and transfers it into `sys_clk' clock domain. */ + wire [13: 0] sys_eim_addr; - wire sys_eim_wr;
+ wire sys_eim_wr; wire sys_eim_rd; wire [31: 0] sys_eim_dout; - wire [31: 0] sys_eim_din;
-
- eim_arbiter eim
- (
- .eim_bclk (eim_bclk_buf),
- .eim_cs0_n (eim_cs0_n),
+ wire [31: 0] sys_eim_din; + + eim_arbiter eim + ( + .eim_bclk (eim_bclk_buf), + .eim_cs0_n (eim_cs0_n), .eim_da (eim_da), - .eim_lba_n (eim_lba_n),
+ .eim_lba_n (eim_lba_n), .eim_wr_n (eim_wr_n), - .eim_oe_n (eim_oe_n),
- .eim_wait_n (eim_wait_n),
-
- .sys_clk (sys_clk),
-
- .sys_addr (sys_eim_addr),
- .sys_wren (sys_eim_wr),
- .sys_data_out (sys_eim_dout),
- .sys_rden (sys_eim_rd),
- .sys_data_in (sys_eim_din)
- );
-
-
- //
- // Core Selector (MUX)
- //
-
- /* This multiplexor is used to map demo adder registers somewhere into EIM address space. */
-
- core_selector mux
- (
- .sys_clk (sys_clk),
- .sys_rst (sys_rst),
-
- .sys_eim_addr (sys_eim_addr),
- .sys_eim_wr (sys_eim_wr),
- .sys_eim_rd (sys_eim_rd),
- - .sys_eim_dout (sys_eim_dout),
- .sys_eim_din (sys_eim_din)
- );
-
-
- //
- // LED Driver
- //
- eim_indicator led
- (
- .sys_clk (sys_clk),
- .sys_rst (sys_rst),
- .eim_active (sys_eim_wr | sys_eim_rd),
- .led_out (led_pin)
- );
-
-
- //
- // Unused
- //
- assign apoptosis_pin = 1'b0;
-
-
-endmodule
+ .eim_oe_n (eim_oe_n), + .eim_wait_n (eim_wait_n), + + .sys_clk (sys_clk), + + .sys_addr (sys_eim_addr), + .sys_wren (sys_eim_wr), + .sys_data_out (sys_eim_dout), + .sys_rden (sys_eim_rd), + .sys_data_in (sys_eim_din) + ); + + + // + // Core Selector (MUX) + // + + /* This multiplexor is used to map demo adder registers somewhere into EIM address space. */ + + core_selector mux + ( + .sys_clk (sys_clk), + .sys_rst (sys_rst), + + .sys_eim_addr (sys_eim_addr), + .sys_eim_wr (sys_eim_wr), + .sys_eim_rd (sys_eim_rd), + + .sys_eim_dout (sys_eim_dout), + .sys_eim_din (sys_eim_din) + ); + + + // + // LED Driver + // + eim_indicator led + ( + .sys_clk (sys_clk), + .sys_rst (sys_rst), + .eim_active (sys_eim_wr | sys_eim_rd), + .led_out (led_pin) + ); + + + // + // Unused + // + assign apoptosis_pin = 1'b0; + + +endmodule diff --git a/rtl/src/verilog/novena_clkmgr.v b/rtl/src/verilog/novena_clkmgr.v index 2f8c02f..5713383 100644 --- a/rtl/src/verilog/novena_clkmgr.v +++ b/rtl/src/verilog/novena_clkmgr.v @@ -1,100 +1,100 @@ -`timescale 1ns / 1ps
-
-module novena_clkmgr
- (
+`timescale 1ns / 1ps + +module novena_clkmgr + ( gclk_p, gclk_n, reset_mcu_b, - sys_clk, sys_rst,
- bclk_in, bclk_out
- );
-
- //
- // Ports
- //
- input wire gclk_p; // signal from clock pins
- input wire gclk_n; //
- - input wire reset_mcu_b; // cpu reset (async)
- - output wire sys_clk; // buffered system clock output
- output wire sys_rst; // system reset output (sync)
-
- input wire bclk_in; // signal from clock pin
- output wire bclk_out; // buffered clock output
-
-
- //
- // IBUFGDS
- //
- (* BUFFER_TYPE="NONE" *)
- wire gclk;
- + sys_clk, sys_rst, + bclk_in, bclk_out + ); + + // + // Ports + // + input wire gclk_p; // signal from clock pins + input wire gclk_n; // + + input wire reset_mcu_b; // cpu reset (async) + + output wire sys_clk; // buffered system clock output + output wire sys_rst; // system reset output (sync) + + input wire bclk_in; // signal from clock pin + output wire bclk_out; // buffered clock output + + + // + // IBUFGDS + // + (* BUFFER_TYPE="NONE" *) + wire gclk; + IBUFGDS IBUFGDS_gclk ( .I (gclk_p), .IB (gclk_n), .O (gclk) - );
-
-
- //
- // DCM
- //
- wire dcm_reset; // dcm reset
- wire dcm_locked; // output clock valid
- wire gclk_missing; // no input clock
-
- clkmgr_dcm dcm
- (
- .CLK_IN1 (gclk),
- .RESET (dcm_reset),
- .INPUT_CLK_STOPPED (gclk_missing),
-
- .CLK_OUT1 (sys_clk),
- .CLK_VALID (dcm_locked)
- );
-
-
+ ); + + + // + // DCM + // + wire dcm_reset; // dcm reset + wire dcm_locked; // output clock valid + wire gclk_missing; // no input clock + + clkmgr_dcm dcm + ( + .CLK_IN1 (gclk), + .RESET (dcm_reset), + .INPUT_CLK_STOPPED (gclk_missing), + + .CLK_OUT1 (sys_clk), + .CLK_VALID (dcm_locked) + ); + + // // DCM Reset Logic - //
-
- /* DCM should be reset on power-up, when input clock is stopped or when the CPU gets reset. */
- - reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
- + // + + /* DCM should be reset on power-up, when input clock is stopped or when the CPU gets reset. */ + + reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register + always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing) // if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) dcm_rst_shreg <= {16{1'b1}}; else dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0}; - - assign dcm_reset = dcm_rst_shreg[15];
-
-
+ + assign dcm_reset = dcm_rst_shreg[15]; + + // // System Reset Logic - //
-
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
- + // + + /* System reset is asserted for 16 cycles whenever DCM aquires lock. */ + reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register - + always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) // if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) sys_rst_shreg <= {16{1'b1}}; - else if (dcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; - - assign sys_rst = sys_rst_shreg[15];
-
-
- //
- // BCLK BUFG
- //
- BUFG BUFG_BCLK
- (
- .I (bclk_in),
- .O (bclk_out)
- );
-
-
-endmodule
+ else if (dcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0}; + + assign sys_rst = sys_rst_shreg[15]; + + + // + // BCLK BUFG + // + BUFG BUFG_BCLK + ( + .I (bclk_in), + .O (bclk_out) + ); + + +endmodule |