aboutsummaryrefslogtreecommitdiff
path: root/rtl/src/verilog/novena_baseline_top.v
diff options
context:
space:
mode:
authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 09:03:37 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 09:03:37 +0100
commit5150947e0bfc393b03e49bcb37e1168eb02f5b67 (patch)
treee800d87f2142c31fece7c15b1e26b368b670c624 /rtl/src/verilog/novena_baseline_top.v
parent0d258b832847ca29bcf47f1904b7cc4a76e2a191 (diff)
Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.
Diffstat (limited to 'rtl/src/verilog/novena_baseline_top.v')
0 files changed, 0 insertions, 0 deletions