diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-01 09:36:44 +0100 |
---|---|---|
committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-01 09:36:44 +0100 |
commit | d88592bf59eeb7263507f4d13a69aa841840bda7 (patch) | |
tree | 093f7de6ef866faa98f513836648ec1690de05b1 /rtl/src/verilog/demo_adder.v | |
parent | a67abc2f80d5181d607abb8663d13f6dd8ec1b0b (diff) |
Added proper file headers to all verilog source files.
Diffstat (limited to 'rtl/src/verilog/demo_adder.v')
-rw-r--r-- | rtl/src/verilog/demo_adder.v | 174 |
1 files changed, 108 insertions, 66 deletions
diff --git a/rtl/src/verilog/demo_adder.v b/rtl/src/verilog/demo_adder.v index a86f114..54e7f72 100644 --- a/rtl/src/verilog/demo_adder.v +++ b/rtl/src/verilog/demo_adder.v @@ -1,66 +1,108 @@ -`timescale 1ns / 1ps
-
-module demo_adder
- (
- clk, rst,
- x, y, z,
- ctl, sts
- );
-
- //
- // Ports
- //
- input wire clk; // clock
- input wire rst; // reset
-
- input wire [31: 0] x; // x
- input wire [31: 0] y; // y
- output wire [31: 0] z; // z = x + y
-
- input wire [15: 0] ctl; // control
- output wire [15: 0] sts; // status
-
-
- //
- // Internal Registers
- //
- reg [31: 0] z_reg = {32{1'b0}};
- reg [15: 0] sts_reg = {16{1'b0}};
- reg [15: 0] ctl_dly = {16{1'b0}};
-
- assign z = z_reg;
- assign sts = sts_reg;
-
-
- //
- // Control Logic
- //
- always @(posedge clk)
- //
- if (rst) ctl_dly <= {16{1'b0}};
- else ctl_dly <= ctl;
-
- /* This flag is set whenever different value is written to control register. */
-
- wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0;
-
-
- //
- // Adder Logic
- //
- always @(posedge clk)
- //
- if (rst) z_reg <= {32{1'b0}};
- else if (adder_go) z_reg <= x + y;
-
-
- //
- // Status Logic
- //
- always @(posedge clk)
- //
- if (rst) sts_reg <= {16{1'b0}};
- else if (adder_go) sts_reg <= ctl;
-
-
-endmodule
+//====================================================================== +// +// demo_adder.v +// ------------ +// Simple test core for the Cryptech Novena FPGA framework. The core +// s a 32-bit adder that allows us to verfy that we can write registers +// get a computation done and read out the registers via the EIM. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module demo_adder + ( + clk, rst, + x, y, z, + ctl, sts + ); + + // + // Ports + // + input wire clk; // clock + input wire rst; // reset + + input wire [31: 0] x; // x + input wire [31: 0] y; // y + output wire [31: 0] z; // z = x + y + + input wire [15: 0] ctl; // control + output wire [15: 0] sts; // status + + + // + // Internal Registers + // + reg [31: 0] z_reg = {32{1'b0}}; + reg [15: 0] sts_reg = {16{1'b0}}; + reg [15: 0] ctl_dly = {16{1'b0}}; + + assign z = z_reg; + assign sts = sts_reg; + + + // + // Control Logic + // + always @(posedge clk) + // + if (rst) ctl_dly <= {16{1'b0}}; + else ctl_dly <= ctl; + + /* This flag is set whenever different value is written to control register. */ + + wire adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0; + + + // + // Adder Logic + // + always @(posedge clk) + // + if (rst) z_reg <= {32{1'b0}}; + else if (adder_go) z_reg <= x + y; + + + // + // Status Logic + // + always @(posedge clk) + // + if (rst) sts_reg <= {16{1'b0}}; + else if (adder_go) sts_reg <= ctl; + + +endmodule + +//====================================================================== +// EOF demo_adder.v +//====================================================================== |