Fixed names for core selector to follow the form of the selectors for rng and ciphers. Fixed copy crimes. Disabled hash cores for the time being since we want to debug the rng.trng

1 files changed, 8 insertions, 11 deletions

diff --git a/rtl/src/verilog/cipher_selector.v b/rtl/src/verilog/cipher_selector.v
index ea18e14..8eead4b 100644
--- a/rtl/src/verilog/cipher_selector.v
+++ b/rtl/src/verilog/cipher_selector.v
@@ -2,15 +2,12 @@
 //
 // cipher_selector.v
 // -----------------
-// Top level wrapper that creates the Cryptech coretest system.
-// The wrapper contains instances of external interface, coretest
-// and the core to be tested. And if more than one core is
-// present the wrapper also includes address and data muxes.
+// Selector for cipher cores.
 //
 //
 // Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
 // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
@@ -58,16 +55,16 @@ module cipher_selector
    //
    reg [31: 0]          tmp_read_data;
    assign sys_read_data = tmp_read_data;
-   
+
 
    /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
     * to prevent ISE from complaining that we don't use input ports.
     */
-   
+
    reg [31: 0]          reg_dummy_first;
    reg [31: 0]          reg_dummy_second;
    reg [31: 0]          reg_dummy_third;
-   
+
    always @(posedge sys_clk)
      //
      if (sys_rst)
@@ -108,10 +105,10 @@ module cipher_selector
             end
           //
        end
-   
 
-endmodule
+
+endmodule // cipher_selector
 
 //======================================================================
-// EOF core_selector.v
+// EOF cipher_selector.v
 //======================================================================