diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
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committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
commit | a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 (patch) | |
tree | 2fc4876ab32718ce45943e960fbd1f8be16eb1d5 /rtl/src/ipcore/coregen.cgp | |
parent | 785767f35cdee9aca04969b97734e05351bb084d (diff) |
Adding all main hw source files and constraints.
Diffstat (limited to 'rtl/src/ipcore/coregen.cgp')
-rw-r--r-- | rtl/src/ipcore/coregen.cgp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/rtl/src/ipcore/coregen.cgp b/rtl/src/ipcore/coregen.cgp new file mode 100644 index 0000000..929723b --- /dev/null +++ b/rtl/src/ipcore/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
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