From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Sat, 31 Jan 2015 09:03:06 +0100
Subject: Adding all main hw source files and constraints.

---
 rtl/src/ipcore/coregen.cgp | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 rtl/src/ipcore/coregen.cgp

(limited to 'rtl/src/ipcore/coregen.cgp')

diff --git a/rtl/src/ipcore/coregen.cgp b/rtl/src/ipcore/coregen.cgp
new file mode 100644
index 0000000..929723b
--- /dev/null
+++ b/rtl/src/ipcore/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
-- 
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