Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master

1 files changed, 21 insertions, 7 deletions

diff --git a/rtl/build/Makefile b/rtl/build/Makefile
index aa5aeb4..cfac6ae 100644
--- a/rtl/build/Makefile
+++ b/rtl/build/Makefile
@@ -7,16 +7,30 @@ isedir = /opt/Xilinx/14.7/ISE_DS
 xil_env = . $(isedir)/settings64.sh
 
 vfiles = \
-	../src/verilog/novena_baseline_top.v \
-	../src/verilog/novena_clkmgr.v \
 	../src/verilog/cdc_bus_pulse.v \
+	../src/verilog/cipher_selector.v \
+	../src/verilog/core_selector.v \
+	../src/verilog/eim_arbiter_cdc.v \
 	../src/verilog/eim_arbiter.v \
-	../src/verilog/demo_adder.v \
 	../src/verilog/eim_da_phy.v \
-	../src/verilog/eim_arbiter_cdc.v \
-	../src/verilog/core_selector.v \
-	../src/testbench/tb_demo_adder.v \
 	../src/verilog/eim_indicator.v \
-	../src/ipcore/clkmgr_dcm.v
+	../src/verilog/eim_memory.v \
+	../src/verilog/novena_baseline_top.v \
+	../src/verilog/novena_clkmgr.v \
+	../src/verilog/novena_regs.v \
+	../src/verilog/rng_selector.v \
+	../src/verilog/sha1.v \
+	../src/verilog/sha256.v \
+	../src/verilog/sha512.v \
+	../src/ipcore/clkmgr_dcm.v \
+	../../../../core/sha1/src/rtl/sha1_core.v \
+	../../../../core/sha1/src/rtl/sha1_w_mem.v \
+	../../../../core/sha256/src/rtl/sha256_core.v \
+	../../../../core/sha256/src/rtl/sha256_k_constants.v \
+	../../../../core/sha256/src/rtl/sha256_w_mem.v \
+	../../../../core/sha512/src/rtl/sha512_core.v \
+	../../../../core/sha512/src/rtl/sha512_h_constants.v \
+	../../../../core/sha512/src/rtl/sha512_k_constants.v \
+	../../../../core/sha512/src/rtl/sha512_w_mem.v
 
 include xilinx.mk