From 13b8166c8989b5e83b0c998279c60c17bf46e890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 5 Feb 2015 15:31:33 -0500 Subject: add all SHA cores (hello coretest_hashes) --- rtl/build/.gitignore | 52 +++++++++++ rtl/build/Makefile | 32 +++++++ rtl/build/novena_baseline_top.bmm | 0 rtl/build/novena_baseline_top.ucf | 1 + rtl/build/xilinx.mk | 176 ++++++++++++++++++++++++++++++++++++++ rtl/build/xilinx.opt | 42 +++++++++ 6 files changed, 303 insertions(+) create mode 100644 rtl/build/.gitignore create mode 100644 rtl/build/Makefile create mode 100644 rtl/build/novena_baseline_top.bmm create mode 120000 rtl/build/novena_baseline_top.ucf create mode 100644 rtl/build/xilinx.mk create mode 100644 rtl/build/xilinx.opt (limited to 'rtl/build') diff --git a/rtl/build/.gitignore b/rtl/build/.gitignore new file mode 100644 index 0000000..e60e316 --- /dev/null +++ b/rtl/build/.gitignore @@ -0,0 +1,52 @@ +*.xrpt +_xmsgs +default.xreport +netlist.lst +novena_baseline_top.bgn +novena_baseline_top.bit +novena_baseline_top.bld +novena_baseline_top.cfi +novena_baseline_top.drc +novena_baseline_top.lso +novena_baseline_top.lso +novena_baseline_top.map +novena_baseline_top.mcs +novena_baseline_top.mrp +novena_baseline_top.ncd +novena_baseline_top.ngc +novena_baseline_top.ngd +novena_baseline_top.ngm +novena_baseline_top.pcf +novena_baseline_top.post_map.twr +novena_baseline_top.post_map.twx +novena_baseline_top.prj +novena_baseline_top.prm +novena_baseline_top.psr +novena_baseline_top.scr +novena_baseline_top.srp +novena_baseline_top.twr +novena_baseline_top.twx +novena_baseline_top_bd.bmm +novena_baseline_top_bitgen.xwb +novena_baseline_top_bitgen.xwbt +novena_baseline_top_err.twr +novena_baseline_top_err.twx +novena_baseline_top_par.grf +novena_baseline_top_par.ncd +novena_baseline_top_par.pad +novena_baseline_top_par.par +novena_baseline_top_par.ptwx +novena_baseline_top_par.unroutes +novena_baseline_top_par.xpi +novena_baseline_top_par_pad.csv +novena_baseline_top_par_pad.txt +novena_baseline_top_summary.xml +novena_baseline_top_usage.xml +par_usage_statistics.html +smartguide.ncd +smartpreview.twr +smartpreview.twr +usage_statistics_webtalk.html +webtalk.log +xlnx_auto* +xst diff --git a/rtl/build/Makefile b/rtl/build/Makefile new file mode 100644 index 0000000..ec03197 --- /dev/null +++ b/rtl/build/Makefile @@ -0,0 +1,32 @@ +project = novena_baseline_top +vendor = xilinx +family = spartan6 +part = xc6slx45csg324-3 +top_module = novena_baseline_top +isedir = /opt/Xilinx/14.7/ISE_DS +xil_env = . $(isedir)/settings64.sh + +vfiles = \ + ../src/verilog/novena_baseline_top.v \ + ../src/verilog/novena_clkmgr.v \ + ../src/verilog/cdc_bus_pulse.v \ + ../src/verilog/eim_arbiter.v \ + ../src/verilog/eim_da_phy.v \ + ../src/verilog/eim_arbiter_cdc.v \ + ../src/verilog/core_selector.v \ + ../src/verilog/eim_indicator.v \ + ../src/ipcore/clkmgr_dcm.v \ + ../../../../core/sha256/src/rtl/sha256_core.v \ + ../../../../core/sha256/src/rtl/sha256_k_constants.v \ + ../../../../core/sha256/src/rtl/sha256.v \ + ../../../../core/sha256/src/rtl/sha256_w_mem.v \ + ../../../../core/sha1/src/rtl/sha1_core.v \ + ../../../../core/sha1/src/rtl/sha1.v \ + ../../../../core/sha1/src/rtl/sha1_w_mem.v \ + ../../../../core/sha512/src/rtl/sha512_core.v \ + ../../../../core/sha512/src/rtl/sha512_h_constants.v \ + ../../../../core/sha512/src/rtl/sha512_k_constants.v \ + ../../../../core/sha512/src/rtl/sha512.v \ + ../../../../core/sha512/src/rtl/sha512_w_mem.v + +include xilinx.mk diff --git a/rtl/build/novena_baseline_top.bmm b/rtl/build/novena_baseline_top.bmm new file mode 100644 index 0000000..e69de29 diff --git a/rtl/build/novena_baseline_top.ucf b/rtl/build/novena_baseline_top.ucf new file mode 120000 index 0000000..fddd839 --- /dev/null +++ b/rtl/build/novena_baseline_top.ucf @@ -0,0 +1 @@ +../src/ucf/novena_baseline.ucf \ No newline at end of file diff --git a/rtl/build/xilinx.mk b/rtl/build/xilinx.mk new file mode 100644 index 0000000..a3a0216 --- /dev/null +++ b/rtl/build/xilinx.mk @@ -0,0 +1,176 @@ +# The top level module should define the variables below then include +# this file. The files listed should be in the same directory as the +# Makefile. +# +# variable description +# ---------- ------------- +# project project name (top level module should match this name) +# top_module top level module of the project +# libdir path to library directory +# libs library modules used +# vfiles all local .v files +# xilinx_cores all local .xco files +# vendor vendor of FPGA (xilinx, altera, etc.) +# family FPGA device family (spartan3e) +# part FPGA part name (xc4vfx12-10-sf363) +# flashsize size of flash for mcs file (16384) +# optfile (optional) xst extra opttions file to put in .scr +# map_opts (optional) options to give to map +# par_opts (optional) options to give to par +# intstyle (optional) intstyle option to all tools +# +# files description +# ---------- ------------ +# $(project).ucf ucf file +# +# Library modules should have a modules.mk in their root directory, +# namely $(libdir)//module.mk, that simply adds to the vfiles +# and xilinx_cores variable. +# +# all the .xco files listed in xilinx_cores will be generated with core, with +# the resulting .v and .ngc files placed back in the same directory as +# the .xco file. +# +# TODO: .xco files are device dependant, should use a template based system + +coregen_work_dir ?= ./coregen-tmp +map_opts ?= -timing -ol high -detail -pr b -register_duplication -w +par_opts ?= -ol high +isedir ?= /opt/Xilinx/13.3/ISE_DS +xil_env ?= . $(isedir)/settings32.sh +flashsize ?= 8192 + +libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) +mkfiles = Makefile $(libmks) xilinx.mk +include $(libmks) + +corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) +local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) +vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) +junk += $(local_corengcs) + +.PHONY: default xilinx_cores clean twr etwr +default: $(project).bit $(project).mcs +xilinx_cores: $(corengcs) +twr: $(project).twr +etwr: $(project)_err.twr + +define cp_template +$(2): $(1) + cp $(1) $(2) +endef +$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) + +%.ngc %.v: %.xco + @echo "=== rebuilding $@" + if [ -d $(coregen_work_dir) ]; then \ + rm -rf $(coregen_work_dir)/*; \ + else \ + mkdir -p $(coregen_work_dir); \ + fi + cd $(coregen_work_dir); \ + $(xil_env); \ + coregen -b $$OLDPWD/$<; \ + cd - + xcodir=`dirname $<`; \ + basename=`basename $< .xco`; \ + if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \ + echo "'$@' wasn't created."; \ + exit 1; \ + else \ + cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \ + fi +junk += $(coregen_work_dir) + +date = $(shell date +%F-%H-%M) + +# some common junk +junk += *.xrpt + +programming_files: $(project).bit $(project).mcs + mkdir -p $@/$(date) + mkdir -p $@/latest + for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done + $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr + +$(project).mcs: $(project).bit + $(xil_env); \ + promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^ +junk += $(project).mcs $(project).cfi $(project).prm + +$(project).bit: $(project)_par.ncd + $(xil_env); \ + bitgen $(intstyle) -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit +junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm + + +$(project)_par.ncd: $(project).ncd + $(xil_env); \ + if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \ + :; \ + else \ + $(MAKE) etwr; \ + fi +junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad +junk += $(project)_par_pad.csv $(project)_par_pad.txt +junk += $(project)_par.grf $(project)_par.ptwx +junk += $(project)_par.unroutes $(project)_par.xpi + +$(project).ncd: $(project).ngd + if [ -r $(project)_par.ncd ]; then \ + cp $(project)_par.ncd smartguide.ncd; \ + smartguide="-smartguide smartguide.ncd"; \ + else \ + smartguide=""; \ + fi; \ + $(xil_env); \ + map $(intstyle) $(map_opts) $$smartguide $< +junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map +junk += smartguide.ncd $(project).psr +junk += $(project)_summary.xml $(project)_usage.xml + +$(project).ngd: $(project).ngc $(project).ucf $(project).bmm + $(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm +junk += $(project).ngd $(project).bld + +$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj + $(xil_env); xst $(intstyle) -ifn $(project).scr +junk += xlnx_auto* $(top_module).lso $(project).srp +junk += netlist.lst xst $(project).ngc + +$(project).prj: $(vfiles) $(mkfiles) + for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done + sort -u $(project).tmpprj > $(project).prj + rm -f $(project).tmpprj +junk += $(project).prj + +optfile += $(wildcard $(project).opt) +top_module ?= $(project) +$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt + echo "run" > $@ + echo "-p $(part)" >> $@ + echo "-top $(top_module)" >> $@ + echo "-ifn $(project).prj" >> $@ + echo "-ofn $(project).ngc" >> $@ + cat ./xilinx.opt $(optfile) >> $@ +junk += $(project).scr + +$(project).post_map.twr: $(project).ncd + $(xil_env); trce -e 10 $< $(project).pcf -o $@ +junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr + +$(project).twr: $(project)_par.ncd + $(xil_env); trce $< $(project).pcf -o $(project).twr +junk += $(project).twr $(project).twx smartpreview.twr + +$(project)_err.twr: $(project)_par.ncd + $(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr +junk += $(project)_err.twr $(project)_err.twx +junk += $(project).lso $(project)_bitgen.xwb $(project)_bitgen.xwbt +junk += usage_statistics_webtalk.html par_usage_statistics.html webtalk.log _xmsgs default.xreport + +.gitignore: $(mkfiles) + echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore + +clean:: + rm -rf $(junk) diff --git a/rtl/build/xilinx.opt b/rtl/build/xilinx.opt new file mode 100644 index 0000000..7fe9d8b --- /dev/null +++ b/rtl/build/xilinx.opt @@ -0,0 +1,42 @@ +-ifmt mixed +-ofmt NGC +-opt_mode speed +-opt_level 1 +-iuc NO +-keep_hierarchy no +-netlist_hierarchy as_optimized +-rtlview no +-glob_opt AllClockNets +-read_cores yes +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +#-dsp_utilization_ratio 100 +-safe_implementation No +-fsm_extract YES +-fsm_encoding Auto +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-shreg_extract YES +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +#-use_dsp48 auto +-iobuf YES +-max_fanout 500 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 -- cgit v1.2.3 From 0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 13:51:40 -0500 Subject: First stage of integration cleanup. Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory. --- rtl/build/Makefile | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'rtl/build') diff --git a/rtl/build/Makefile b/rtl/build/Makefile index ec03197..cfac6ae 100644 --- a/rtl/build/Makefile +++ b/rtl/build/Makefile @@ -7,26 +7,30 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings64.sh vfiles = \ - ../src/verilog/novena_baseline_top.v \ - ../src/verilog/novena_clkmgr.v \ ../src/verilog/cdc_bus_pulse.v \ + ../src/verilog/cipher_selector.v \ + ../src/verilog/core_selector.v \ + ../src/verilog/eim_arbiter_cdc.v \ ../src/verilog/eim_arbiter.v \ ../src/verilog/eim_da_phy.v \ - ../src/verilog/eim_arbiter_cdc.v \ - ../src/verilog/core_selector.v \ ../src/verilog/eim_indicator.v \ + ../src/verilog/eim_memory.v \ + ../src/verilog/novena_baseline_top.v \ + ../src/verilog/novena_clkmgr.v \ + ../src/verilog/novena_regs.v \ + ../src/verilog/rng_selector.v \ + ../src/verilog/sha1.v \ + ../src/verilog/sha256.v \ + ../src/verilog/sha512.v \ ../src/ipcore/clkmgr_dcm.v \ + ../../../../core/sha1/src/rtl/sha1_core.v \ + ../../../../core/sha1/src/rtl/sha1_w_mem.v \ ../../../../core/sha256/src/rtl/sha256_core.v \ ../../../../core/sha256/src/rtl/sha256_k_constants.v \ - ../../../../core/sha256/src/rtl/sha256.v \ ../../../../core/sha256/src/rtl/sha256_w_mem.v \ - ../../../../core/sha1/src/rtl/sha1_core.v \ - ../../../../core/sha1/src/rtl/sha1.v \ - ../../../../core/sha1/src/rtl/sha1_w_mem.v \ ../../../../core/sha512/src/rtl/sha512_core.v \ ../../../../core/sha512/src/rtl/sha512_h_constants.v \ ../../../../core/sha512/src/rtl/sha512_k_constants.v \ - ../../../../core/sha512/src/rtl/sha512.v \ ../../../../core/sha512/src/rtl/sha512_w_mem.v include xilinx.mk -- cgit v1.2.3