diff options
Diffstat (limited to 'toolruns/quartus/terasic_de0')
3 files changed, 154 insertions, 0 deletions
diff --git a/toolruns/quartus/terasic_de0/external_avalanche_entropy.qpf b/toolruns/quartus/terasic_de0/external_avalanche_entropy.qpf new file mode 100644 index 0000000..d21d0f9 --- /dev/null +++ b/toolruns/quartus/terasic_de0/external_avalanche_entropy.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+# Date created = 16:17:23 August 14, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:17:23 August 14, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "external_avalanche_entropy"
diff --git a/toolruns/quartus/terasic_de0/external_avalanche_entropy.qsf b/toolruns/quartus/terasic_de0/external_avalanche_entropy.qsf new file mode 100644 index 0000000..5295cd8 --- /dev/null +++ b/toolruns/quartus/terasic_de0/external_avalanche_entropy.qsf @@ -0,0 +1,84 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+# Date created = 16:17:23 August 14, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# external_avalanche_entropy_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY external_avalanche_entropy
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:17:23 AUGUST 14, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/external_avalanche_entropy/src/rtl/external_avalanche_entropy.v
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_location_assignment PIN_R8 -to clk
+set_location_assignment PIN_J15 -to reset_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk -entity external_avalanche_entropy
+set_location_assignment PIN_A15 -to debug[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[0]
+set_location_assignment PIN_A13 -to debug[1]
+set_location_assignment PIN_B13 -to debug[2]
+set_location_assignment PIN_A11 -to debug[3]
+set_location_assignment PIN_D1 -to debug[4]
+set_location_assignment PIN_F3 -to debug[5]
+set_location_assignment PIN_B1 -to debug[6]
+set_location_assignment PIN_L3 -to debug[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[7]
+set_location_assignment PIN_D3 -to noise
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to noise
+set_global_assignment -name SDC_FILE //psf/Home/Sandbox/proj/cores/external_avalanche_entropy/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc b/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc new file mode 100644 index 0000000..ed97c9c --- /dev/null +++ b/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc @@ -0,0 +1,40 @@ +#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.
+#
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "clk" -period 20.000ns [get_ports {clk}] -waveform {0 10.000}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
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