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-rw-r--r--src/rtl/entropy.v41
1 files changed, 26 insertions, 15 deletions
diff --git a/src/rtl/entropy.v b/src/rtl/entropy.v
index 6295ef9..fed4697 100644
--- a/src/rtl/entropy.v
+++ b/src/rtl/entropy.v
@@ -43,7 +43,7 @@ module entropy(input wire clk,
input wire we,
input wire [7:0] addr,
input wire [15:0] dwrite,
- output wire [15:0] dread,
+ output wire [31:0] dread,
output wire [7 : 0] debug
);
@@ -61,6 +61,8 @@ module entropy(input wire clk,
parameter ADDR_ENT_RD_RNG1_RNG2 = 8'h10;
parameter ADDR_ENT_RD_P = 8'h11;
parameter ADDR_ENT_RD_N = 8'h12;
+ parameter ADDR_ENT_MIX = 8'h20;
+ parameter ADDR_ENT_CONCAT = 8'h21;
//----------------------------------------------------------------
@@ -70,13 +72,15 @@ module entropy(input wire clk,
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] debug_reg;
-
+ reg [31 : 0] mix_reg;
+ reg [31 : 0] concat_reg;
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- wire [15:0] p, n;
- reg [15 : 0] tmp_dread;
+ wire [31 : 0] p, n;
+ reg [31 : 0] tmp_dread;
//----------------------------------------------------------------
@@ -84,7 +88,7 @@ module entropy(input wire clk,
//----------------------------------------------------------------
genvar i;
generate
- for(i=0; i<16; i=i+1) begin: tworoscs
+ for(i=0; i<32; i=i+1) begin: tworoscs
rosc px(clk, nreset, rng1, rng2, p[i]);
rosc nx(clk, nreset, rng1, rng2, n[i]);
end
@@ -108,25 +112,30 @@ module entropy(input wire clk,
rng1 <= 8'h55;
rng2 <= 8'haa;
delay_ctr_reg <= 32'h00000000;
+ mix_reg <= 32'h00000000;
+ concat_reg <= 32'h00000000;
debug_reg <= 8'h00;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
-
+ mix_reg <= n ^ p;
+ concat_reg <= {n[31 : 16] ^ n[15 : 0], p[31 : 16] ^ p[15 : 0]};
+
if (delay_ctr_reg == 32'h00000000)
begin
debug_reg <= n[7 : 0];
end
- if(cs & we) begin
- case(addr)
- ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
- ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
- default:;
- endcase
- end
- end // else: !if(!nreset)
+ if(cs & we)
+ begin
+ case(addr)
+ ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
+ ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
+ default:;
+ endcase
+ end
+ end
end
@@ -139,9 +148,11 @@ module entropy(input wire clk,
if(cs & ~we)
case(addr)
- ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {rng1, rng2};
+ ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {16'h0000, rng1, rng2};
ADDR_ENT_RD_P: tmp_dread = p;
ADDR_ENT_RD_N: tmp_dread = n;
+ ADDR_ENT_MIX: tmp_dread = mix_reg;
+ ADDR_ENT_CONCAT: tmp_dread = concat_reg;
default:;
endcase
end