1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48#include "cmsis_os.h"
#include "stm-init.h"
#include "stm-uart.h"
osMutexId stdio_mutex;
osMutexDef(stdio_mutex);
void notify(const char* name, int state) {
osMutexWait(stdio_mutex, osWaitForever);
//printf("%s: %d\n\r", name, state);
uart_send_string(name);
uart_send_string(": ");
uart_send_integer(state, 1);
uart_send_string("\r\n");
osMutexRelease(stdio_mutex);
}
void test_thread(void const *args) {
whilepre { line-height: 125%; }
td.linenos .normal { color: inherit; background-color: transparent; padding-left: 5px; padding-right: 5px; }
span.linenos { color: inherit; background-color: transparent; padding-left: 5px; padding-right: 5px; }
td.linenos .special { color: #000000; background-color: #ffffc0; padding-left: 5px; padding-right: 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding-left: 5px; padding-right: 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .ges { font-weight: bold; font-style: italic } /* Generic.EmphStrong */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long *//*
* stm-sdram.c
* -----------
* Functions concerning the 2x512 Mbit SDRAM working memory.
*
* Copyright (c) 2016, NORDUnet A/S All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of the NORDUnet nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stm32f4xx_hal.h"
#include "stm-init.h"
#include "stm-sdram.h"
#include "stm-fmc.h"
#include "stm-led.h"
/* Mode Register Bits */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
SDRAM_HandleTypeDef hsdram1;
SDRAM_HandleTypeDef hsdram2;
static void _sdram_init_gpio(void);
static HAL_StatusTypeDef _sdram_init_fmc(void);
static HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2);
HAL_StatusTypeDef sdram_init(void)
{
HAL_StatusTypeDef status;
static int initialized = 0;
if (initialized) {
return HAL_OK;
}
initialized = 1;
/* We rely on several things being set up by fmc_init() instead of duplicating all
* that code here for independent FPGA/SDRAM FMC setup. This means the FPGA<->STM32
* FMC bus can be used without the SDRAMs initialized, but the SDRAMs can't be
* initialized withouth the FPGA<->STM32 FMC bus being set up too.
*/
fmc_init();
// configure FMC
_sdram_init_gpio();
status = _sdram_init_fmc();
if (status != HAL_OK) return status;
// configure SDRAM registers
status = _sdram_init_params(&hsdram1, &hsdram2);
if (status != HAL_OK) return status;
return HAL_OK;
}
static void _sdram_init_gpio(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* The bulk of the FMC GPIO pins are set up in fmc_init_gpio().
* This function just needs to enable the additional ones used
* with the SDRAMs.
*/
fmc_af_gpio(GPIOB, GPIO_PIN_5 | GPIO_PIN_6);
fmc_af_gpio(GPIOC, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
fmc_af_gpio(GPIOE, GPIO_PIN_0 | GPIO_PIN_1);
fmc_af_gpio(GPIOF, GPIO_PIN_11);
fmc_af_gpio(GPIOG, GPIO_PIN_8 | GPIO_PIN_15);
fmc_af_gpio(GPIOI, GPIO_PIN_4 | GPIO_PIN_5);
}
static HAL_StatusTypeDef _sdram_init_fmc()
{
HAL_StatusTypeDef status;
FMC_SDRAM_TimingTypeDef SdramTiming;
/*
* following settings are for -75E speed grade memory chip
* clocked at only 90 MHz instead of the rated 133 MHz
*
* ExitSelfRefreshDelay: 67 ns @ 90 MHz is 6.03 cycles, so in theory
* 6 can be used here, but let's be on the safe side
*
* WriteRecoveryTime: must be >= tRAS - tRCD (5 - 2 = 3 cycles),
* and >= tRC - tRCD - tRP (8 - 2 - 2 = 4 cycles)
*/
SdramTiming.LoadToActiveDelay = 2; // tMRD
SdramTiming.ExitSelfRefreshDelay = 7; // (see above)
SdramTiming.SelfRefreshTime = 5; // should be >= tRAS (5 cycles)
SdramTiming.RowCycleDelay = 8; // tRC
SdramTiming.WriteRecoveryTime = 4; // (see above)
SdramTiming.RPDelay = 2; // tRP
SdramTiming.RCDDelay = 2; // tRCD
/*
* configure the first bank
*/
// memory type
hsdram1.Instance = FMC_SDRAM_DEVICE;
// bank
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
// settings for IS42S32160F
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
// write protection not needed
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
// memory clock is 90 MHz (HCLK / 2)
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
// read burst not needed
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
// additional pipeline stages not neeed
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
// call HAL layer
status = HAL_SDRAM_Init(&hsdram1, &SdramTiming);
if (status != HAL_OK) return status;
/*
* configure the second bank
*/
// memory type
hsdram2.Instance = FMC_SDRAM_DEVICE;
// bank number
hsdram2.Init.SDBank = FMC_SDRAM_BANK2;
// settings for IS42S32160F
hsdram2.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
hsdram2.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
hsdram2.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
hsdram2.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram2.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
// write protection not needed
hsdram2.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
// memory clock is 90 MHz (HCLK / 2)
hsdram2.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
// read burst not needed
hsdram2.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
// additional pipeline stages not neeed
hsdram2.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
// call HAL layer
return HAL_SDRAM_Init(&hsdram2, &SdramTiming);
}
static HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2)
{
HAL_StatusTypeDef ok; // status
FMC_SDRAM_CommandTypeDef cmd; // command
#define HAL_Delay(n) for (int i = 0; i < 1000 * n; ++i)
/*
* enable clocking
*/
cmd.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
cmd.AutoRefreshNumber = 1;
cmd.ModeRegisterDefinition = 0;
HAL_Delay(1);
ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1);
if (ok != HAL_OK) return ok;
/*
* precharge all banks
*/
cmd.CommandMode = FMC_SDRAM_CMD_PALL;
cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
cmd.AutoRefreshNumber = 1;
cmd.ModeRegisterDefinition = 0;
HAL_Delay(1);
ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1);
if (ok != HAL_OK) return ok;
/*
* send two auto-refresh commands in a row
*/
cmd.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
cmd.AutoRefreshNumber = 1;
cmd.ModeRegisterDefinition = 0;
ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1);
if (ok != HAL_OK) return ok;
ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1);
if (ok != HAL_OK) return ok;
/*
* load mode register
*/
cmd.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
cmd.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1_2;
cmd.AutoRefreshNumber = 1;
cmd.ModeRegisterDefinition =
SDRAM_MODEREG_BURST_LENGTH_1 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_2 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ;
ok = HAL_SDRAM_SendCommand(sdram1, &cmd, 1);
if (ok != HAL_OK) return ok;
/*
* set number of consequtive auto-refresh commands
* and program refresh rate
*
* RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
*
* RefreshCycles = 7.8125 us * 90 MHz = 703
*
* According to the formula on p.1665 of the reference manual,
* we also need to subtract 20 from the value, so the target
* refresh rate is 703 - 20 = 683.
*/
ok = HAL_SDRAM_SetAutoRefreshNumber(sdram1, 8);
if (ok != HAL_OK) return ok;
HAL_SDRAM_ProgramRefreshRate(sdram1, 683);
if (ok != HAL_OK) return ok;
/*
* done
*/
return HAL_OK;
}
|