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path: root/projects/libhal-test/Makefile
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TEST = cores test-bus test-trng test-hash test-aes-key-wrap test-pbkdf2 test-ecdsa test-rsa test-mkmif

CFLAGS += -I $(LIBHAL_SRC)
LIBC_OBJS = printf.o gettimeofday.o
LIBS += $(LIBHAL_BLD)/libhal.a $(LIBTFM_BLD)/libtfm.a

all: $(TEST:=.elf)

vpath %.c $(LIBHAL_SRC)/tests $(LIBHAL_SRC)/utils

# .mo extension for files with main() that need to be wrapped as __main()
%.mo: %.c
	$(CC) -c $(CFLAGS) -Dmain=__main -o $@ $<

%.elf: %.mo main.o $(BOARD_OBJS) $(LIBC_OBJS) $(LIBS)
	$(CC) $(CFLAGS) $^ -o $*.elf -T$(LDSCRIPT) -g -Wl,-Map=$*.map
	$(OBJCOPY) -O binary $*.elf $*.bin
	$(SIZE) $*.elf

# don't automatically delete objects, to avoid a lot of unnecessary rebuilding
.SECONDARY: $(BOARD_OBJS) $(LIBC_OBJS)

clean:
	rm -f *.o *.mo
	rm -f *.elf
	rm -f *.bin
	rm -f *.map
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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr B 17000 11000
encoding utf-8
Sheet 23 27
Title "rev04_21"
Date "15 10 2016"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 9200 3350 0    60   ~ 12
*) Power - AUX
Text Notes 6100 3350 0    60   ~ 12
*) Power - CORE & BRAM
Text Notes 3100 3250 0    60   ~ 12
*) Ground Pins
Text Notes 7010 1060 0    66   ~ 13
FPGA power and ground
$Comp
L power:GND #GND_0132
U 1 1 58023EE6
P 3100 8450
F 0 "#GND_0132" H 3100 8450 20  0000 C CNN
F 1 "+GND" H 3100 8380 30  0000 C CNN
F 2 "" H 3100 8450 70  0000 C CNN
F 3 "" H 3100 8450 70  0000 C CNN
	1    3100 8450
	1    0    0    -1  
$EndComp
$Comp
L power:GND #GND_0133
U 1 1 58023EE5
P 4900 8350
F 0 "#GND_0133" H 4900 8350 20  0000 C CNN
F 1 "+GND" H 4900 8280 30  0000 C CNN
F 2 "" H 4900 8350 70  0000 C CNN
F 3 "" H 4900 8350 70  0000 C CNN
	1    4900 8350
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:FPGA_VCCINT_1V0 #FPGA_VCCINT_1V00
U 1 1 58023EE4
P 7100 3650
F 0 "#FPGA_VCCINT_1V00" H 7100 3650 20  0000 C CNN
F 1 "+FPGA_VCCINT_1V0" H 7100 3580 30  0000 C CNN
F 2 "" H 7100 3650 70  0000 C CNN
F 3 "" H 7100 3650 70  0000 C CNN
	1    7100 3650
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:FPGA_VCCAUX_1V8 #FPGA_VCCAUX_1V8_02
U 1 1 58023EE3
P 10100 3650
F 0 "#FPGA_VCCAUX_1V8_02" H 10100 3650 20  0000 C CNN
F 1 "+FPGA_VCCAUX_1V8" H 10100 3580 30  0000 C CNN
F 2 "" H 10100 3650 70  0000 C CNN
F 3 "" H 10100 3650 70  0000 C CNN
	1    10100 3650
	1    0    0    -1  
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
	10100 3650 10100 3850
$Comp
L Cryptech_Alpha:XC7A200TFBG484_NEW U13
U 9 1 58023EE2
P 2700 6050
F 0 "U13" H 2290 3640 60  0000 L BNN
F 1 "XC7A200T-1FBG484C" H 2700 6050 50  0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 2290 3640 60  0001 C CNN
F 3 "" H 2700 6050 50  0001 C CNN
	9    2700 6050
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:XC7A200TFBG484_NEW U13
U 10 1 58023EE1
P 4500 6050
F 0 "U13" H 4090 3740 60  0000 L BNN
F 1 "XC7A200T-1FBG484C" H 4500 6050 50  0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 4090 3740 60  0001 C CNN
F 3 "" H 4500 6050 50  0001 C CNN
	10   4500 6050
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:XC7A200TFBG484_NEW U13
U 14 1 58023EE0
P 9700 4050
F 0 "U13" H 9290 3640 60  0000 L BNN
F 1 "XC7A200T-1FBG484C" H 9700 4050 50  0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 9290 3640 60  0001 C CNN
F 3 "" H 9700 4050 50  0001 C CNN
	14   9700 4050
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:XC7A200TFBG484_NEW U13
U 15 1 58023EDF
P 6700 3950
F 0 "U13" H 6290 3640 60  0000 L BNN
F 1 "XC7A200T-1FBG484C" H 6700 3950 50  0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 6290 3640 60  0001 C CNN
F 3 "" H 6700 3950 50  0001 C CNN
	15   6700 3950
	1    0    0    -1  
$EndComp
$Comp
L Cryptech_Alpha:XC7A200TFBG484_NEW U13
U 16 1 58023EDE
P 6700 5350
F 0 "U13" H 6290 6160 60  0000 L TNN
F 1 "XC7A200T-1FBG484C" H 6700 5350 50  0001 C CNN
F 2 "Cryptech_Alpha_Footprints:BGA484C100P22X22_2300X2300X254" H 6290 6160 60  0001 C CNN
F 3 "" H 6700 5350 50  0001 C CNN
	16   6700 5350
	1    0    0    1   
$EndComp
Connection ~ 3100 4050
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Connection ~ 3100 6450
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Connection ~ 3100 6950
Connection ~ 3100 7050
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Connection ~ 4900 4050
Connection ~ 4900 4150
Connection ~ 4900 4250
Connection ~ 4900 4350
Connection ~ 4900 4450
Connection ~ 4900 4550
Connection ~ 4900 4650
Connection ~ 4900 4750
Connection ~ 4900 4850
Connection ~ 4900 4950
Connection ~ 4900 5050
Connection ~ 4900 5150
Connection ~ 4900 5250
Connection ~ 4900 5350
Connection ~ 4900 5450
Connection ~ 4900 5550
Connection ~ 4900 5650
Connection ~ 4900 5750
Connection ~ 4900 5850
Connection ~ 4900 5950
Connection ~ 4900 6050
Connection ~ 4900 6150
Connection ~ 4900 6250
Connection ~ 4900 6350
Connection ~ 4900 6450
Connection ~ 4900 6550
Connection ~ 4900 6650
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Connection ~ 4900 6850
Connection ~ 4900 6950
Connection ~ 4900 7050
Connection ~ 4900 7150
Connection ~ 4900 7250
Connection ~ 4900 7350
Connection ~ 4900 7450
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Connection ~ 4900 7950
Connection ~ 4900 8050
Connection ~ 4900 8150
Connection ~ 7100 3850
Connection ~ 7100 3950
Connection ~ 7100 4050
Connection ~ 7100 4650
Connection ~ 7100 4750
Connection ~ 7100 4850
Connection ~ 7100 4950
Connection ~ 7100 5050
Connection ~ 7100 5150
Connection ~ 7100 5250
Connection ~ 7100 5350
Connection ~ 7100 5450
Connection ~ 7100 5550
Connection ~ 7100 5650
Connection ~ 7100 5750
Connection ~ 7100 5850
Connection ~ 10100 3850
Connection ~ 10100 3950
Connection ~ 10100 4050
Connection ~ 10100 4150
$Comp
L Mechanical:Heatsink HS1
U 1 1 5F6D16C5
P 12100 3750
F 0 "HS1" H 12242 3871 50  0000 L CNN
F 1 "BGA-STD-025" H 12242 3780 50  0000 L CNN
F 2 "Symbol:KiCad-Logo2_8mm_SilkScreen" H 12112 3750 50  0001 C CNN
F 3 "" H 12112 3750 50  0001 C CNN
F 4 "ABL Heatsinks" H 12100 3750 50  0001 C CNN "Manufacturer"
	1    12100 3750
	1    0    0    -1  
$EndComp
$EndSCHEMATC