aboutsummaryrefslogtreecommitdiff
path: root/stm-init.c
AgeCommit message (Collapse)Author
2021-09-13Added call to ice40mkm_init() during initialization.Pavel V. Shatov (Meister)
2017-08-31CleanupPaul Selkirk
2017-05-02Merge branch 'init_cleanup' into no-rtosPaul Selkirk
Clean up Makefiles and initialization code.
2017-04-17Use default SysTick interrupt priority.Paul Selkirk
We really don't want SysTick_Handler, which runs the task scheduler, to run at a higher priority than SVC_Handler, which runs supposedly-atomic operations like mutex locking and unlocking. I've seen a mutex lock/unlock mismatch which I think is due to interrupting rt_mut_release at a particularly inopportune moment.
2016-06-13Change gpio setups from macros to inline functions.Paul Selkirk
2016-06-06Refactor HAL_UART_MspInit, link DMA in MX_USART*_UART_Init so ↵Paul Selkirk
HAL_UART_MspInit doesn't have to.
2016-06-02Use DMA for UART RX instead of interrupts.Fredrik Thulin
DMA is more efficient and less prone to miss characters than interrupts. An open question is if circular mode is really the best. If someone copy-pastes more than the RX buffer size of configuration into the CLI, we risk the DMA controller catching up with the reader and overwriting data not yet read. Since we don't have flow control back to the users terminal, we will always fail if too much data is entered before we can process it. The question is if failing to stuff new data at the end of a buffer might be better than data being overwritten - thus messing up the commands in unpredictable ways.
2016-05-23SDRAM initialization and test code from Pavel.Fredrik Thulin
Integrated into the cli-test program as such: cryptech> test sdram Initializing SDRAM Starting SDRAM test (n = 0) Run sequential write-then-read test for the first chip Run random write-then-read test for the first chip Run sequential write-then-read test for the second chip Run random write-then-read test for the second chip Run interleaved write-then-read test for both chips at once SDRAM test (n = 0) completed SDRAM test completed successfully cryptech>
2016-05-21Add code to access the keystore memory (SPI flash).Fredrik Thulin
2016-05-20Add code to reset FPGA using FPGA_PROGRAM_B and FPGA_INIT_B.Fredrik Thulin
Also add code to erase FPGA config memory and check status of FPGA_DONE.
2016-05-19Refactor FPGA bitstream upload code.Fredrik Thulin
Move the N25Q128 code to it's own file in order to be able to reuse it for the keystore memory code.
2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18A little more robust file transferFredrik Thulin
2016-05-18FPGA config memory access code from Pavel.Fredrik Thulin
2016-05-16Add code to talk with the external RTC chip.Fredrik Thulin
2016-05-15add simple filetransfer pocFredrik Thulin
2016-05-14rename some definesFredrik Thulin
2016-05-14found paul is setting up HSE in TARGET_CRYPTECH_ALPHAFredrik Thulin
2016-05-13rename huart1 and huart2 to huart_mgmt and huart_userFredrik Thulin
reduces risk of using the wrong one
2016-05-12Update LED pinouts, don't think the colors are right yet though.Fredrik Thulin
2016-05-12Enable HSE (external clock oscillator).Fredrik Thulin
2016-05-12Test both UARTs, and also test receiving data.Fredrik Thulin
2016-04-24This time for sure - async receive, and everything that flows from that.Paul Selkirk
2016-04-14import mbed rtos libraryPaul Selkirk
2015-11-11Lots of cleanup.Paul Selkirk
Clean up and simplify(?) Makefile. Add copyrights as needed. Add include guard to stm-fmc.h. Move MX_USART2_UART_Init back to stm-init.c for possible copyright reasons. Move libc, src, and include files to top level.