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2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18A little more robust file transferFredrik Thulin
2016-05-18FPGA config memory access code from Pavel.Fredrik Thulin
2016-05-16Add code to talk with the external RTC chip.Fredrik Thulin
2016-05-15add simple filetransfer pocFredrik Thulin
2016-05-14rename some definesFredrik Thulin
2016-05-14found paul is setting up HSE in TARGET_CRYPTECH_ALPHAFredrik Thulin
2016-05-13rename huart1 and huart2 to huart_mgmt and huart_userFredrik Thulin
reduces risk of using the wrong one
2016-05-12Update LED pinouts, don't think the colors are right yet though.Fredrik Thulin
2016-05-12Enable HSE (external clock oscillator).Fredrik Thulin
2016-05-12Test both UARTs, and also test receiving data.Fredrik Thulin
2016-04-24This time for sure - async receive, and everything that flows from that.Paul Selkirk
2016-04-14import mbed rtos libraryPaul Selkirk
2015-11-11Lots of cleanup.Paul Selkirk
Clean up and simplify(?) Makefile. Add copyrights as needed. Add include guard to stm-fmc.h. Move MX_USART2_UART_Init back to stm-init.c for possible copyright reasons. Move libc, src, and include files to top level.