aboutsummaryrefslogtreecommitdiff
path: root/projects
AgeCommit message (Collapse)Author
2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18A little more robust file transferFredrik Thulin
2016-05-18put some generic CLI code in mgmt-cli.cFredrik Thulin
2016-05-18Add reboot command.Fredrik Thulin
2016-05-18Write in 4k-chunks, with acks for flow control.Fredrik Thulin
2016-05-18build libcliPaul Selkirk
2016-05-16Use baud rate 921600 instead of 115200.Fredrik Thulin
Don't want to wait longer than necessary for firmware file transfers.
2016-05-16Add code to talk with the external RTC chip.Fredrik Thulin
2016-05-15add simple filetransfer pocFredrik Thulin
2016-05-14update FMC test for alphaFredrik Thulin
2016-05-13Add test program for libcli based CLI.Fredrik Thulin
2016-05-13Implement support for the two UARTs on the alpha board.Fredrik Thulin
2016-05-12Update LED pinouts, don't think the colors are right yet though.Fredrik Thulin
2016-05-12Test both UARTs, and also test receiving data.Fredrik Thulin
2016-04-24This time for sure - async receive, and everything that flows from that.Paul Selkirk
2016-04-21threaded rpc serverPaul Selkirk
2016-04-14import mbed rtos libraryPaul Selkirk
2016-04-11Reorganize Makefile and directory structure, because it's messy, and it's ↵Paul Selkirk
about to get messier.