| Age | Commit message (Collapse) | Author |
|---|
|
Integrated into the cli-test program as such:
cryptech> test sdram
Initializing SDRAM
Starting SDRAM test (n = 0)
Run sequential write-then-read test for the first chip
Run random write-then-read test for the first chip
Run sequential write-then-read test for the second chip
Run random write-then-read test for the second chip
Run interleaved write-then-read test for both chips at once
SDRAM test (n = 0) completed
SDRAM test completed successfully
cryptech>
|
|
|
|
|
|
Hopefully, having this excitement now makes adding commands a little bit
less exciting from here on.
|
|
Also add code to erase FPGA config memory and check status of FPGA_DONE.
|
|
Move the N25Q128 code to it's own file in order to be able to reuse it
for the keystore memory code.
|
|
This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:
filetransfer --fpga /path/to/bitstream
The bitstream is identified by 'file' e.g. like this:
alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164
|
|
|
|
|
|
|
|
|
|
|
|
Don't want to wait longer than necessary for firmware file transfers.
|
|
|
|
|
