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path: root/projects/cli-test/filetransfer
AgeCommit message (Collapse)Author
2020-07-13Whack all Python shebangs to Python 3Rob Austein
2020-05-26Wow, python-version-independent hexadecimal is painfulRob Austein
2020-05-25Untested conversion to support Python 3Rob Austein
2016-06-02Use DMA for UART RX instead of interrupts.Fredrik Thulin
DMA is more efficient and less prone to miss characters than interrupts. An open question is if circular mode is really the best. If someone copy-pastes more than the RX buffer size of configuration into the CLI, we risk the DMA controller catching up with the reader and overwriting data not yet read. Since we don't have flow control back to the users terminal, we will always fail if too much data is entered before we can process it. The question is if failing to stuff new data at the end of a buffer might be better than data being overwritten - thus messing up the commands in unpredictable ways.
2016-05-24non-working code to upload an application and jump to itFredrik Thulin
Committing my work in progress in case someone else wants to help.
2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18A little more robust file transferFredrik Thulin
2016-05-18Write in 4k-chunks, with acks for flow control.Fredrik Thulin
2016-05-16Use baud rate 921600 instead of 115200.Fredrik Thulin
Don't want to wait longer than necessary for firmware file transfers.
2016-05-15add simple filetransfer pocFredrik Thulin