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2016-05-23commit bugfix from Pavel fixing initialization of the second SDRAM chipFredrik Thulin
2016-05-21Add code to access the keystore memory (SPI flash).Fredrik Thulin
2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18FPGA config memory access code from Pavel.Fredrik Thulin
2016-05-18build libcliPaul Selkirk
2016-05-16Add code to talk with the external RTC chip.Fredrik Thulin
2016-05-12Add build target for the alphaFredrik Thulin
2016-04-24This time for sure - async receive, and everything that flows from that.Paul Selkirk
2016-04-14import mbed rtos libraryPaul Selkirk
2016-04-11Reorganize Makefile and directory structure, because it's messy, and it's ↵Paul Selkirk
about to get messier.