Age | Commit message (Collapse) | Author | |
---|---|---|---|
2016-05-24 | Merge branch 'master' of git.cryptech.is:sw/stm32 | Paul Selkirk | |
2016-05-24 | Remove unused linker scripts | Paul Selkirk | |
2016-05-23 | SDRAM initialization and test code from Pavel. | Fredrik Thulin | |
Integrated into the cli-test program as such: cryptech> test sdram Initializing SDRAM Starting SDRAM test (n = 0) Run sequential write-then-read test for the first chip Run random write-then-read test for the first chip Run sequential write-then-read test for the second chip Run random write-then-read test for the second chip Run interleaved write-then-read test for both chips at once SDRAM test (n = 0) completed SDRAM test completed successfully cryptech> | |||
2016-05-23 | commit bugfix from Pavel fixing initialization of the second SDRAM chip | Fredrik Thulin | |
2016-05-21 | Add code to access the keystore memory (SPI flash). | Fredrik Thulin | |
2016-05-18 | Add FPGA bitstream upload command to cli-test. | Fredrik Thulin | |
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164 | |||
2016-05-18 | FPGA config memory access code from Pavel. | Fredrik Thulin | |
2016-05-16 | Add code to talk with the external RTC chip. | Fredrik Thulin | |
2016-05-12 | Add build target for the alpha | Fredrik Thulin | |
2016-04-24 | This time for sure - async receive, and everything that flows from that. | Paul Selkirk | |
2016-04-14 | import mbed rtos library | Paul Selkirk | |