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it's easier than setting up a dedicated timer.
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first place.
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We really don't want SysTick_Handler, which runs the task scheduler, to
run at a higher priority than SVC_Handler, which runs supposedly-atomic
operations like mutex locking and unlocking. I've seen a mutex lock/unlock
mismatch which I think is due to interrupting rt_mut_release at a
particularly inopportune moment.
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buffer, because we've observed out-of-order receives under load.
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receive buffer with half-complete callbacks, and raise the dma priority.
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STM32 HAL code directly.
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This lets us, say, use these sections for stack or heap.
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We don't plan to put initialized data in SDRAM, and we don't have startup
code to copy initialized data, so don't even bother. Further, the linker
will reserve space in FLASH, even for uninitialized data, so just don't.
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Also rearchitect the way we handle RPC requests - have a bunch of waiting
dispatch threads rather than continually creating and deleting threads.
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HAL_UART_MspInit doesn't have to.
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DMA is more efficient and less prone to miss characters than interrupts.
An open question is if circular mode is really the best. If someone
copy-pastes more than the RX buffer size of configuration into the CLI,
we risk the DMA controller catching up with the reader and overwriting
data not yet read.
Since we don't have flow control back to the users terminal, we will
always fail if too much data is entered before we can process it. The
question is if failing to stuff new data at the end of a buffer might be
better than data being overwritten - thus messing up the commands in
unpredictable ways.
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This bootloader is now the application at 0x08000000 (FLASH start),
which the STM32 will execute upon reset.
The other applications are now loaded at 0x08030000 (128 KB into the
flash) and will never get started unless the bootloader has been
programmed into flash too.
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The applications to be uploaded using 'dfu upload' have to have another
FLASH defined in their linker script.
Have to recompile some firmware tomorrow and test if this actually
works.
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Committing my work in progress in case someone else wants to help.
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Integrated into the cli-test program as such:
cryptech> test sdram
Initializing SDRAM
Starting SDRAM test (n = 0)
Run sequential write-then-read test for the first chip
Run random write-then-read test for the first chip
Run sequential write-then-read test for the second chip
Run random write-then-read test for the second chip
Run interleaved write-then-read test for both chips at once
SDRAM test (n = 0) completed
SDRAM test completed successfully
cryptech>
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This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:
filetransfer --fpga /path/to/bitstream
The bitstream is identified by 'file' e.g. like this:
alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164
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