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AgeCommit message (Collapse)Author
2016-06-01Implement circular buffer UART RX using interrupts.Fredrik Thulin
2016-05-26Implement a bootloader.Fredrik Thulin
This bootloader is now the application at 0x08000000 (FLASH start), which the STM32 will execute upon reset. The other applications are now loaded at 0x08030000 (128 KB into the flash) and will never get started unless the bootloader has been programmed into flash too.
2016-05-25More DFU code. This might actually work.Fredrik Thulin
The applications to be uploaded using 'dfu upload' have to have another FLASH defined in their linker script. Have to recompile some firmware tomorrow and test if this actually works.
2016-05-25remove non-free files we're not using anywaysFredrik Thulin
2016-05-24non-working code to upload an application and jump to itFredrik Thulin
Committing my work in progress in case someone else wants to help.
2016-05-23SDRAM initialization and test code from Pavel.Fredrik Thulin
Integrated into the cli-test program as such: cryptech> test sdram Initializing SDRAM Starting SDRAM test (n = 0) Run sequential write-then-read test for the first chip Run random write-then-read test for the first chip Run sequential write-then-read test for the second chip Run random write-then-read test for the second chip Run interleaved write-then-read test for both chips at once SDRAM test (n = 0) completed SDRAM test completed successfully cryptech>
2016-05-23commit bugfix from Pavel fixing initialization of the second SDRAM chipFredrik Thulin
2016-05-21Add code to access the keystore memory (SPI flash).Fredrik Thulin
2016-05-18Add FPGA bitstream upload command to cli-test.Fredrik Thulin
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
2016-05-18FPGA config memory access code from Pavel.Fredrik Thulin
2016-05-16Add code to talk with the external RTC chip.Fredrik Thulin
2016-05-12Add build target for the alphaFredrik Thulin
2016-04-24This time for sure - async receive, and everything that flows from that.Paul Selkirk
2016-04-14import mbed rtos libraryPaul Selkirk