diff options
Diffstat (limited to 'stm-fpgacfg.c')
| -rw-r--r-- | stm-fpgacfg.c | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/stm-fpgacfg.c b/stm-fpgacfg.c index f8ff6fa..9e2a307 100644 --- a/stm-fpgacfg.c +++ b/stm-fpgacfg.c @@ -1,7 +1,8 @@ /* * stm-fpgacfg.c * ---------- - * Functions for accessing the FPGA config memory. + * Functions for accessing the FPGA config memory and controlling + * the low-level status of the FPGA (reset registers/reboot etc.). * * Copyright (c) 2016, NORDUnet A/S All rights reserved. * @@ -69,3 +70,43 @@ void fpgacfg_access_control(enum fpgacfg_access_ctrl access) HAL_GPIO_WritePin(GPIOF, PROM_ARM_ENA_Pin, GPIO_PIN_SET); } } + +void fpgacfg_reset_fpga(enum fpgacfg_reset reset) +{ + if (reset == RESET_FULL) { + /* The delay should be at least 250 uS. With HAL_Delay(1) the pulse is very close + * to that, and With HAL_Delay(3) the pulse is close to 2 ms. */ + HAL_GPIO_WritePin(FPGA_PROGRAM_Port, FPGA_PROGRAM_Pin, GPIO_PIN_RESET); + HAL_Delay(3); + HAL_GPIO_WritePin(FPGA_PROGRAM_Port, FPGA_PROGRAM_Pin, GPIO_PIN_SET); + } else if (reset == RESET_REGISTERS) { + HAL_GPIO_WritePin(FPGA_INIT_Port, FPGA_INIT_Pin, GPIO_PIN_SET); + HAL_Delay(3); + HAL_GPIO_WritePin(FPGA_INIT_Port, FPGA_INIT_Pin, GPIO_PIN_RESET); + } +} + +int fpgacfg_check_done(void) +{ + GPIO_PinState status = HAL_GPIO_ReadPin(FPGA_DONE_Port, FPGA_DONE_Pin); + return (status == GPIO_PIN_SET); +} + +int fpgacfg_erase_sectors(int num) +{ + if (num > N25Q128_NUM_SECTORS - 1 || num < 0) num = N25Q128_NUM_SECTORS - 1; + while (num) { + int timeout = 1000; + while (timeout--) { + int i = n25q128_get_wip_flag(&fpgacfg_ctx); + if (i < 0) return 0; + if (! i) break; + HAL_Delay(10); + } + + if (! n25q128_erase_sector(&fpgacfg_ctx, num--)) { + return 0; + } + } + return 1; +} |