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-rw-r--r--projects/cli-test/Makefile3
-rw-r--r--projects/cli-test/mgmt-misc.c10
-rw-r--r--projects/cli-test/mgmt-show.c22
-rw-r--r--projects/cli-test/mgmt-test.c75
-rw-r--r--projects/cli-test/test-fmc.c197
-rw-r--r--projects/cli-test/test-fmc.h43
6 files changed, 345 insertions, 5 deletions
diff --git a/projects/cli-test/Makefile b/projects/cli-test/Makefile
index 5a6cea8..11c1737 100644
--- a/projects/cli-test/Makefile
+++ b/projects/cli-test/Makefile
@@ -8,9 +8,10 @@ OBJS = \
mgmt-keystore.o \
mgmt-masterkey.o \
mgmt-misc.o \
- test-mkmif.o \
mgmt-show.o \
mgmt-test.o \
+ test-fmc.o \
+ test-mkmif.o \
test_sdram.o
BOARD_OBJS = \
diff --git a/projects/cli-test/mgmt-misc.c b/projects/cli-test/mgmt-misc.c
index 535f0af..b7b4fcc 100644
--- a/projects/cli-test/mgmt-misc.c
+++ b/projects/cli-test/mgmt-misc.c
@@ -58,14 +58,14 @@ int cli_receive_data(struct cli_def *cli, uint8_t *buf, size_t len, cli_data_cal
if (! control_mgmt_uart_dma_rx(DMA_RX_STOP)) {
cli_print(cli, "Failed stopping DMA");
- return CLI_OK;
+ goto fail;
}
cli_print(cli, "OK, write size (4 bytes), data in %li byte chunks, CRC-32 (4 bytes)", (uint32_t) n);
if (uart_receive_bytes(STM_UART_MGMT, (void *) &filesize, 4, 1000) != HAL_OK) {
cli_print(cli, "Receive timed out");
- return CLI_ERROR;
+ goto fail;
}
cli_print(cli, "Send %li bytes of data", filesize);
@@ -80,7 +80,7 @@ int cli_receive_data(struct cli_def *cli, uint8_t *buf, size_t len, cli_data_cal
if (uart_receive_bytes(STM_UART_MGMT, (void *) buf, n, 1000) != HAL_OK) {
cli_print(cli, "Receive timed out");
- return CLI_ERROR;
+ goto fail;
}
filesize -= n;
my_crc = update_crc(my_crc, buf, n);
@@ -90,7 +90,7 @@ int cli_receive_data(struct cli_def *cli, uint8_t *buf, size_t len, cli_data_cal
*/
if (data_callback != NULL && ! data_callback(buf, (size_t) n)) {
cli_print(cli, "Data processing failed");
- return CLI_OK;
+ goto fail;
}
counter++;
@@ -106,6 +106,8 @@ int cli_receive_data(struct cli_def *cli, uint8_t *buf, size_t len, cli_data_cal
cli_print(cli, "CRC checksum did NOT match");
}
+ fail:
+ control_mgmt_uart_dma_rx(DMA_RX_START);
return CLI_OK;
}
diff --git a/projects/cli-test/mgmt-show.c b/projects/cli-test/mgmt-show.c
index e88b784..7d6b509 100644
--- a/projects/cli-test/mgmt-show.c
+++ b/projects/cli-test/mgmt-show.c
@@ -69,6 +69,25 @@ static int cmd_show_fpga_status(struct cli_def *cli, const char *command, char *
return CLI_OK;
}
+static int cmd_show_fpga_cores(struct cli_def *cli, const char *command, char *argv[], int argc)
+{
+ const hal_core_t *core;
+ const hal_core_info_t *info;
+
+ if (! fpgacfg_check_done()) {
+ cli_print(cli, "FPGA has not loaded a bitstream");
+ return CLI_OK;
+ }
+
+ for (core = hal_core_iterate(NULL); core != NULL; core = hal_core_iterate(core)) {
+ info = hal_core_info(core);
+ cli_print(cli, "%04x: %8.8s %4.4s",
+ (unsigned int)info->base, info->name, info->version);
+ }
+
+ return CLI_OK;
+}
+
static int cmd_show_keystore_status(struct cli_def *cli, const char *command, char *argv[], int argc)
{
cli_print(cli, "Keystore memory is %sonline", (keystore_check_id() != 1) ? "NOT ":"");
@@ -135,6 +154,9 @@ void configure_cli_show(struct cli_def *cli)
/* show fpga status*/
cli_register_command(cli, c_fpga, "status", cmd_show_fpga_status, 0, 0, "Show status about the FPGA");
+ /* show fpga cores*/
+ cli_register_command(cli, c_fpga, "cores", cmd_show_fpga_cores, 0, 0, "Show the currently available FPGA cores");
+
struct cli_command *c_keystore = cli_register_command(cli, c, "keystore", NULL, 0, 0, NULL);
/* show keystore status*/
diff --git a/projects/cli-test/mgmt-test.c b/projects/cli-test/mgmt-test.c
index 138982f..59f0b6e 100644
--- a/projects/cli-test/mgmt-test.c
+++ b/projects/cli-test/mgmt-test.c
@@ -35,12 +35,15 @@
#include "stm-init.h"
#include "stm-led.h"
#include "stm-sdram.h"
+#include "stm-fmc.h"
+#include "stm-fpgacfg.h"
#include "mgmt-cli.h"
#include "mgmt-test.h"
#include "test_sdram.h"
#include "test_mkmif.h"
+#include "test-fmc.h"
#include <stdlib.h>
@@ -107,6 +110,75 @@ static int cmd_test_sdram(struct cli_def *cli, const char *command, char *argv[]
return CLI_OK;
}
+static int cmd_test_fmc(struct cli_def *cli, const char *command, char *argv[], int argc)
+{
+ int i, num_cycles = 1, num_rounds = 100000;
+
+ if (argc >= 1) {
+ num_cycles = strtol(argv[0], NULL, 0);
+ if (num_cycles > 100000) num_cycles = 100000;
+ if (num_cycles < 1) num_cycles = 1;
+ }
+
+ if (argc == 2) {
+ num_rounds = strtol(argv[1], NULL, 0);
+ if (num_rounds > 1000000) num_rounds = 1000000;
+ if (num_rounds < 1) num_rounds = 1;
+ }
+
+ cli_print(cli, "Checking if FPGA has loaded it's bitstream");
+ // Blink blue LED until the FPGA reports it has loaded it's bitstream
+ led_on(LED_BLUE);
+ while (! fpgacfg_check_done()) {
+ for (i = 0; i < 4; i++) {
+ HAL_Delay(500);
+ led_toggle(LED_BLUE);
+ }
+ }
+
+ // prepare fmc interface
+ cli_print(cli, "Initializing FMC interface");
+ fmc_init();
+
+ // turn on green led, turn off other leds
+ led_on(LED_GREEN);
+ led_off(LED_YELLOW);
+ led_off(LED_RED);
+ led_off(LED_BLUE);
+
+ // vars
+ volatile int data_test_ok = 0, addr_test_ok = 0, successful_runs = 0, failed_runs = 0, sleep = 0;
+
+ for (i = 1; i <= num_cycles; i++) {
+ cli_print(cli, "Starting FMC test (%i/%i)", i, num_cycles);
+
+ // test data bus
+ data_test_ok = test_fpga_data_bus(cli, num_rounds);
+ // test address bus
+ addr_test_ok = test_fpga_address_bus(cli, num_rounds);
+
+ cli_print(cli, "Data: %i, addr %i", data_test_ok, addr_test_ok);
+
+ if (data_test_ok == num_rounds &&
+ addr_test_ok == num_rounds) {
+ // toggle yellow led to indicate, that we are alive
+ led_toggle(LED_YELLOW);
+
+ successful_runs++;
+ sleep = 0;
+ } else {
+ led_on(LED_RED);
+ failed_runs++;
+ sleep = 2000;
+ }
+
+ cli_print(cli, "Success %i, failed %i runs\r\n", successful_runs, failed_runs);
+ HAL_Delay(sleep);
+ }
+
+ return CLI_OK;
+}
+
void configure_cli_test(struct cli_def *cli)
{
struct cli_command *c = cli_register_command(cli, NULL, "test", NULL, 0, 0, NULL);
@@ -116,4 +188,7 @@ void configure_cli_test(struct cli_def *cli)
/* test mkmif */
cli_register_command(cli, c, "mkmif", cmd_test_mkmif, 0, 0, "Run Master Key Memory Interface tests");
+
+ /* test fmc */
+ cli_register_command(cli, c, "fmc", cmd_test_fmc, 0, 0, "Run FMC bus tests");
}
diff --git a/projects/cli-test/test-fmc.c b/projects/cli-test/test-fmc.c
new file mode 100644
index 0000000..ea9afef
--- /dev/null
+++ b/projects/cli-test/test-fmc.c
@@ -0,0 +1,197 @@
+/*
+ * test-fmc.c
+ * -----------
+ * FPGA communication bus (FMC) tests.
+ *
+ * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ * be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ This requires a special bitstream with a special test register.
+ See core/platform/novena/fmc/rtl/novena_fmc_top.v, sections marked
+ `ifdef test:
+ //----------------------------------------------------------------
+ // Dummy Register
+ //
+ // General-purpose register to test FMC interface using STM32
+ // demo program instead of core selector logic.
+ //
+ // This register is a bit tricky, but it allows testing of both
+ // data and address buses. Reading from FPGA will always return
+ // value, which is currently stored in the test register,
+ // regardless of read transaction address. Writing to FPGA has
+ // two variants: a) writing to address 0 will store output data
+ // data value in the test register, b) writing to any non-zero
+ // address will store _address_ of write transaction in the test
+ // register.
+ //
+ // To test data bus, write some different patterns to address 0,
+ // then readback from any address and compare.
+ //
+ // To test address bus, write anything to some different non-zero
+ // addresses, then readback from any address and compare returned
+ // value with previously written address.
+ //
+ //----------------------------------------------------------------
+ */
+
+#include "stm-init.h"
+#include "stm-fmc.h"
+#include "stm-uart.h"
+
+#include "test-fmc.h"
+
+static RNG_HandleTypeDef rng_inst;
+
+/* These are some interesting-to-look-at-in-the-debugger values that are declared
+ * volatile so that the compiler wouldn't optimize/obscure them.
+ */
+volatile uint32_t data_diff = 0;
+volatile uint32_t addr_diff = 0;
+
+
+int test_fpga_data_bus(struct cli_def *cli, uint32_t test_rounds)
+{
+ int c, ok;
+ uint32_t rnd, buf;
+ HAL_StatusTypeDef hal_result;
+
+ /* initialize stm32 rng */
+ rng_inst.Instance = RNG;
+ HAL_RNG_Init(&rng_inst);
+
+ /* run some rounds of data bus test */
+ for (c = 0; c < test_rounds; c++) {
+ data_diff = 0;
+ /* try to generate "random" number */
+ hal_result = HAL_RNG_GenerateRandomNumber(&rng_inst, &rnd);
+ if (hal_result != HAL_OK) {
+ cli_print(cli, "STM32 RNG failed");
+ break;
+ }
+
+ /* write value to fpga at address 0 */
+ ok = fmc_write_32(0, &rnd);
+ if (ok != 0) {
+ cli_print(cli, "FMC write failed: 0x%x", ok);
+ break;
+ }
+
+ /* read value from fpga */
+ ok = fmc_read_32(0, &buf);
+ if (ok != 0) {
+ cli_print(cli, "FMC read failed: 0x%x", ok);
+ break;
+ }
+
+ /* compare (abort testing in case of error) */
+ data_diff = buf ^ rnd;
+ if (data_diff) {
+ cli_print(cli, "Data bus FAIL: expected %lx got %lx", rnd, buf);
+ uart_send_string2(STM_UART_MGMT, (char *) "Binary diff: ");
+ uart_send_number2(STM_UART_MGMT, data_diff, 32, 2);
+ uart_send_string2(STM_UART_MGMT, "\r\n");
+
+ break;
+ }
+ }
+
+ if (! data_diff) {
+ cli_print(cli, "Sample of data bus test data: expected 0x%lx got 0x%lx", rnd, buf);
+ }
+
+ /* return number of successful tests */
+ return c;
+}
+
+int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds)
+{
+ int c, ok;
+ uint32_t rnd, buf;
+ HAL_StatusTypeDef hal_result;
+
+ /* initialize stm32 rng */
+ rng_inst.Instance = RNG;
+ HAL_RNG_Init(&rng_inst);
+
+ /* run some rounds of address bus test */
+ for (c = 0; c < test_rounds; c++) {
+ addr_diff = 0;
+ /* try to generate "random" number */
+ hal_result = HAL_RNG_GenerateRandomNumber(&rng_inst, &rnd);
+ if (hal_result != HAL_OK) break;
+
+ /* there are 26 physicaly connected address lines on the alpha,
+ but "only" 24 usable for now (the top two ones are used by FMC
+ to choose bank, and we only have one bank set up currently)
+ */
+ rnd &= 0x3fffffc;
+
+ /* don't test zero addresses (fpga will store data, not address) */
+ if (rnd == 0) continue;
+
+ /* write dummy value to fpga at some non-zero address */
+ ok = fmc_write_32(rnd, &buf);
+ if (ok != 0) {
+ cli_print(cli, "FMC write failed: 0x%x", ok);
+ break;
+ }
+
+ /* read value from fpga */
+ ok = fmc_read_32(0, &buf);
+ if (ok != 0) {
+ cli_print(cli, "FMC read failed: 0x%x", ok);
+ break;
+ }
+
+ /* fpga receives address of 32-bit word, while we need
+ byte address here to compare
+ */
+ buf <<= 2;
+
+ /* compare (abort testing in case of error) */
+ addr_diff = buf ^ rnd;
+ if (addr_diff) {
+ cli_print(cli, "Address bus FAIL: expected 0x%lx got 0x%lx", rnd, buf);
+ uart_send_string2(STM_UART_MGMT, (char *) "Binary diff: ");
+ uart_send_number2(STM_UART_MGMT, addr_diff, 32, 2);
+ uart_send_string2(STM_UART_MGMT, "\r\n");
+
+ break;
+ }
+ }
+
+ if (! addr_diff) {
+ cli_print(cli, "Sample of address bus test data: expected 0x%lx got 0x%lx", rnd, buf);
+ }
+
+ /* return number of successful tests */
+ return c;
+}
+
diff --git a/projects/cli-test/test-fmc.h b/projects/cli-test/test-fmc.h
new file mode 100644
index 0000000..c49da48
--- /dev/null
+++ b/projects/cli-test/test-fmc.h
@@ -0,0 +1,43 @@
+/*
+ * test-fmc.h
+ * ------------
+ * Prototypes and defines for testing the FMC bus comms with the FPGA.
+ *
+ * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ * be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __STM32_CLI_TEST_FMC_H
+#define __STM32_CLI_TEST_FMC_H
+
+#include "mgmt-cli.h"
+
+extern int test_fpga_data_bus(struct cli_def *cli, uint32_t test_rounds);
+extern int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds);
+
+
+#endif /* __STM32_CLI_TEST_FMC_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 14:11:35 +0000