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authorFredrik Thulin <fredrik@thulin.net>2016-06-16 16:17:20 +0200
committerFredrik Thulin <fredrik@thulin.net>2016-06-16 16:17:20 +0200
commitb61dc669d8b01b49b3a5eb5b494d4270bb4c1b0b (patch)
treed888d6c2453d9da7df27db96a4df54d58d2431bd /stm-sdram.c
parentbba436de5395bda8c83a31720a4243eba2646086 (diff)
parente961e9818193acbb18c503830a554e52285e096b (diff)
Merge branch 'master' into ft-ks_flash
Diffstat (limited to 'stm-sdram.c')
-rw-r--r--stm-sdram.c31
1 files changed, 25 insertions, 6 deletions
diff --git a/stm-sdram.c b/stm-sdram.c
index 22fd8ab..8648d47 100644
--- a/stm-sdram.c
+++ b/stm-sdram.c
@@ -37,12 +37,29 @@
#include "stm-fmc.h"
#include "stm-led.h"
+/* Mode Register Bits */
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
+
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
+
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
SDRAM_HandleTypeDef hsdram1;
SDRAM_HandleTypeDef hsdram2;
-void _sdram_init_gpio(void);
-HAL_StatusTypeDef _sdram_init_fmc(void);
-HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2);
+static void _sdram_init_gpio(void);
+static HAL_StatusTypeDef _sdram_init_fmc(void);
+static HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2);
HAL_StatusTypeDef sdram_init(void)
@@ -74,7 +91,7 @@ HAL_StatusTypeDef sdram_init(void)
return HAL_OK;
}
-void _sdram_init_gpio(void)
+static void _sdram_init_gpio(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
@@ -90,7 +107,7 @@ void _sdram_init_gpio(void)
fmc_af_gpio(GPIOI, GPIO_PIN_4 | GPIO_PIN_5);
}
-HAL_StatusTypeDef _sdram_init_fmc()
+static HAL_StatusTypeDef _sdram_init_fmc()
{
HAL_StatusTypeDef status;
FMC_SDRAM_TimingTypeDef SdramTiming;
@@ -179,11 +196,13 @@ HAL_StatusTypeDef _sdram_init_fmc()
return HAL_SDRAM_Init(&hsdram2, &SdramTiming);
}
-HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2)
+static HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2)
{
HAL_StatusTypeDef ok; // status
FMC_SDRAM_CommandTypeDef cmd; // command
+#define HAL_Delay(n) for (int i = 0; i < 1000 * n; ++i)
+
/*
* enable clocking
*/