diff options
author | Fredrik Thulin <fredrik@thulin.net> | 2016-05-18 21:14:52 +0200 |
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committer | Fredrik Thulin <fredrik@thulin.net> | 2016-05-18 21:14:52 +0200 |
commit | 523d1f66453e9b92835ecc661085e4575426e661 (patch) | |
tree | 008ff6e22deeecbcb6fc9571db1fd7ecce306ea1 /stm-init.c | |
parent | 5e32bc524c4987cfe33cccdb544e3f8d66802895 (diff) |
Add FPGA bitstream upload command to cli-test.
This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:
filetransfer --fpga /path/to/bitstream
The bitstream is identified by 'file' e.g. like this:
alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164
Diffstat (limited to 'stm-init.c')
-rw-r--r-- | stm-init.c | 12 |
1 files changed, 9 insertions, 3 deletions
@@ -81,6 +81,12 @@ void stm_init(void) /* Initialize all configured peripherals */ #ifdef HAL_GPIO_MODULE_ENABLED MX_GPIO_Init(); + #ifdef HAL_SPI_MODULE_ENABLED + /* Give the FPGA access to it's bitstream ASAP (maybe this should actually + * be done in the application, before calling stm_init()). + */ + fpgacfg_give_access_to_fpga(); + #endif #endif #ifdef HAL_UART_MODULE_ENABLED MX_USART1_UART_Init(); @@ -161,9 +167,9 @@ static void MX_GPIO_Init(void) /* Set up GPIOs to manage access to the FPGA config memory. */ /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); + __GPIOI_CLK_ENABLE(); + __GPIOF_CLK_ENABLE(); + __GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(PROM_FPGA_DIS_GPIO_Port, PROM_FPGA_DIS_Pin, GPIO_PIN_RESET); |