diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-07-07 00:40:13 +0300 |
---|---|---|
committer | Paul Selkirk <paul@psgd.org> | 2018-12-12 10:40:54 -0500 |
commit | 7d78334b762315de69fc0c380f3bb7315b0e2a10 (patch) | |
tree | f930f46a2872ec362901f09350e2407d409e3bbd /stm-fmc.h | |
parent | a89dcb22ca549ae17742a8ee3c08f2d7fd606771 (diff) |
Changed FMC initialization code to match the new sync FMC arbiter. Removed
unnecessary code (no more double read, yay!)
Diffstat (limited to 'stm-fmc.h')
-rw-r--r-- | stm-fmc.h | 52 |
1 files changed, 4 insertions, 48 deletions
@@ -39,12 +39,6 @@ #define FMC_FPGA_BASE_ADDR 0x60000000 #define FMC_FPGA_ADDR_MASK 0x03FFFFFC // there are 26 physical lines, but "only" 24 usable for now -#define FMC_FPGA_NWAIT_MAX_POLL_TICKS 10 - -#define FMC_GPIO_PORT_NWAIT GPIOD -#define FMC_GPIO_PIN_NWAIT GPIO_PIN_6 - -#define FMC_NWAIT_IDLE GPIO_PIN_SET #define fmc_af_gpio(port, pins) \ GPIO_InitStruct.Pin = pins; \ @@ -58,60 +52,22 @@ extern void fmc_init(void); -static inline HAL_StatusTypeDef _fmc_nwait_idle(void) -{ - int cnt; - - // poll NWAIT (number of iterations is limited) - for (cnt=0; cnt<FMC_FPGA_NWAIT_MAX_POLL_TICKS; cnt++) - { - // read pin state - if (HAL_GPIO_ReadPin(FMC_GPIO_PORT_NWAIT, FMC_GPIO_PIN_NWAIT) == FMC_NWAIT_IDLE) - return HAL_OK; - } - - return HAL_ERROR; -} - -static inline HAL_StatusTypeDef fmc_write_32(const uint32_t addr, const uint32_t data) +static inline void fmc_write_32(const uint32_t addr, const uint32_t data) { // calculate target fpga address uint32_t *ptr = (uint32_t *) (FMC_FPGA_BASE_ADDR + (addr & FMC_FPGA_ADDR_MASK)); // write data to fpga *ptr = data; - - // wait for transaction to complete - return _fmc_nwait_idle(); } -static inline HAL_StatusTypeDef fmc_read_32(const uint32_t addr, uint32_t * const data) +static inline void fmc_read_32(const uint32_t addr, uint32_t * const data) { // calculate target fpga address uint32_t *ptr = (uint32_t *) (FMC_FPGA_BASE_ADDR + (addr & FMC_FPGA_ADDR_MASK)); - /* Pavel says: - * The short story is like, on one hand STM32 has a dedicated FMC_NWAIT - * pin, that can be used in variable-latency data transfer mode. On the - * other hand STM32 also has a very nasty hardware bug associated with - * FMC_WAIT, that causes processor to freeze under certain conditions. - * Because of this FMC_NWAIT cannot be used and FPGA can't properly signal - * to STM32, when data transfer is done. Because of that we have to read - * two times. - */ - - HAL_StatusTypeDef status; - - *data = *ptr; - status = _fmc_nwait_idle(); - - if (status != HAL_OK) - return status; - - *data = *ptr; - status = _fmc_nwait_idle(); - - return status; + // read data from fpga + *data = *ptr; } #endif /* __STM_FMC_H */ |