Merge branch 'master' of git.cryptech.is:sw/stm32

1 files changed, 42 insertions, 0 deletions

diff --git a/projects/cli-test/test_sdram.h b/projects/cli-test/test_sdram.h
new file mode 100644
index 0000000..b848d18
--- /dev/null
+++ b/projects/cli-test/test_sdram.h
@@ -0,0 +1,42 @@
+/*
+ * test_sdram.h
+ * ------------
+ * Prototypes and defines for testing the 2x512 MBit SDRAM working memory.
+ *
+ * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software
+ *   without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+extern uint32_t lfsr1;
+extern uint32_t lfsr2;
+
+extern int test_sdram_sequential(uint32_t *base_addr);
+extern int test_sdram_random(uint32_t *base_addr);
+extern int test_sdrams_interleaved(uint32_t *base_addr1, uint32_t *base_addr2);
+
+extern uint32_t lfsr_next_32(uint32_t lfsr);
+extern uint32_t lfsr_next_24(uint32_t lfsr);