Merge branch 'master' of git.cryptech.is.:sw/stm32

7 files changed, 76 insertions, 99 deletions

diff --git a/libraries/libcli/Makefile b/libraries/libcli/Makefile
index bbd686d..26bfdf8 100644
--- a/libraries/libcli/Makefile
+++ b/libraries/libcli/Makefile
@@ -1,10 +1,4 @@
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../..)
-endif
+vpath %.c ${LIBCLI_SRC}
+vpath %.h ${LIBCLI_SRC}
 
-REPO := ${CRYPTECH_ROOT}/user/ft/libcli
-
-vpath %.c ${REPO}
-vpath %.h ${REPO}
-
-include ${REPO}/Makefile
+include ${LIBCLI_SRC}/Makefile
diff --git a/libraries/libhal/Makefile b/libraries/libhal/Makefile
index fbc3473..bf870b9 100644
--- a/libraries/libhal/Makefile
+++ b/libraries/libhal/Makefile
@@ -1,10 +1,4 @@
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../..)
-endif
+vpath %.c ${LIBHAL_SRC}
+vpath %.h ${LIBHAL_SRC}
 
-REPO := ${CRYPTECH_ROOT}/sw/libhal
-
-vpath %.c ${REPO}
-vpath %.h ${REPO}
-
-include ${REPO}/Makefile
+include ${LIBHAL_SRC}/Makefile
diff --git a/libraries/libhal/tests/Makefile b/libraries/libhal/tests/Makefile
index 7553427..e148174 100644
--- a/libraries/libhal/tests/Makefile
+++ b/libraries/libhal/tests/Makefile
@@ -1,10 +1,4 @@
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../../..)
-endif
+vpath %.c ${LIBHAL_SRC}/tests
+vpath %.h ${LIBHAL_SRC}/tests
 
-REPO := ${CRYPTECH_ROOT}/sw/libhal
-
-vpath %.c ${REPO}/tests
-vpath %.h ${REPO}/tests
-
-include ${REPO}/tests/Makefile
+include ${LIBHAL_SRC}/tests/Makefile
diff --git a/libraries/libhal/utils/Makefile b/libraries/libhal/utils/Makefile
index 43fbe0d..6f21c2f 100644
--- a/libraries/libhal/utils/Makefile
+++ b/libraries/libhal/utils/Makefile
@@ -1,10 +1,4 @@
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../../..)
-endif
+vpath %.c ${LIBHAL_SRC}/utils
+vpath %.h ${LIBHAL_SRC}/utils
 
-REPO := ${CRYPTECH_ROOT}/sw/libhal
-
-vpath %.c ${REPO}/utils
-vpath %.h ${REPO}/utils
-
-include ${REPO}/utils/Makefile
+include ${LIBHAL_SRC}/utils/Makefile
diff --git a/libraries/libtfm/Makefile b/libraries/libtfm/Makefile
index 4dfcb45..6da552d 100644
--- a/libraries/libtfm/Makefile
+++ b/libraries/libtfm/Makefile
@@ -2,24 +2,18 @@
 # This duplicates more of sw/thirdparty/libtfm/Makefile than I
 # would like, but it does the job.  Prettier makefiles can wait for another day.
 
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../..)
-endif
-
-REPO := ${CRYPTECH_ROOT}/sw/thirdparty/libtfm
-
-# vpath %.c ${REPO}
-# vpath %.h ${REPO}
+# vpath %.c ${LIBTFM_SRC}
+# vpath %.h ${LIBTFM_SRC}
 
 BITS := 8192
 
-HDR  := ${REPO}/tomsfastmath/src/headers/tfm.h
+HDR  := ${LIBTFM_SRC}/tomsfastmath/src/headers/tfm.h
 LIB  := tomsfastmath/libtfm.a
 
 #CFLAGS	+= -DTFM_X86
 #CFLAGS	+= -DTFM_NO_ASM
 
-CFLAGS	+= -fPIC -Wall -W -Wshadow -I${REPO}/tomsfastmath/src/headers -g3 -DFP_MAX_SIZE="(${BITS}*2+(8*DIGIT_BIT))"
+CFLAGS	+= -fPIC -Wall -W -Wshadow -I${LIBTFM_SRC}/tomsfastmath/src/headers -g3 -DFP_MAX_SIZE="(${BITS}*2+(8*DIGIT_BIT))"
 
 TARGETS	:= $(notdir ${HDR} ${LIB})
 
@@ -42,5 +36,5 @@ $(notdir ${LIB}): ${LIB}
 	ln -f $^ $@
 
 ${LIB}: ${HDR}
-	(cd ${REPO} && find tomsfastmath/src -type d) | xargs mkdir -p
+	(cd ${LIBTFM_SRC} && find tomsfastmath/src -type d) | xargs mkdir -p
 	cd tomsfastmath; ${MAKE} CFLAGS='${CFLAGS}'
diff --git a/libraries/libtfm/tomsfastmath/Makefile b/libraries/libtfm/tomsfastmath/Makefile
index 7141763..695aa92 100644
--- a/libraries/libtfm/tomsfastmath/Makefile
+++ b/libraries/libtfm/tomsfastmath/Makefile
@@ -1,8 +1,4 @@
-ifndef CRYPTECH_ROOT
-  CRYPTECH_ROOT := $(abspath ../../../../..)
-endif
+vpath %.c ${LIBTFM_SRC}/tomsfastmath
+vpath %.h ${LIBTFM_SRC}/tomsfastmath
 
-vpath %.c ${CRYPTECH_ROOT}/sw/thirdparty/libtfm/tomsfastmath
-vpath %.h ${CRYPTECH_ROOT}/sw/thirdparty/libtfm/tomsfastmath
-
-include ${CRYPTECH_ROOT}/sw/thirdparty/libtfm/tomsfastmath/makefile
+include ${LIBTFM_SRC}/tomsfastmath/makefile
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
index bdf38fc..8010aef 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
@@ -1413,25 +1413,35 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
   }
   else /* FMC_Bank2_SDRAM */                      
   {
-///////////////////////////////
-// BEGIN PIECE OF WEIRD CODE //
-///////////////////////////////
-//
-//    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-//    
-//    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
-//    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
-//                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
-//                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-//    
-//    tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
-//                        Init->ReadBurst          |\
-//                        Init->ReadPipeDelay);  
-//
-///////////////////////////////
-// END PIECE OF WEIRD CODE   //
-///////////////////////////////
-		
+#if 0 /* broken code */
+    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+    
+    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+    
+    tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\
+                        Init->ReadBurst          |\
+                        Init->ReadPipeDelay);  
+    
+    tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
+    
+    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+    tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+    tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\
+                       Init->RowBitsNumber      |\
+                       Init->MemoryDataWidth    |\
+                       Init->InternalBankNumber |\
+                       Init->CASLatency         |\
+                       Init->WriteProtection);
+
+    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+    Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
+#else
     tmpr2 = Device->SDCR[FMC_SDRAM_BANK1];
     
     /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
@@ -1446,10 +1456,8 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
                        Init->CASLatency         |\
                        Init->WriteProtection);
 
-//
-//    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
-//
     Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
+#endif
   }  
   
   return HAL_OK;
@@ -1500,27 +1508,32 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim
   }
   else /* FMC_Bank2_SDRAM */
   {  
-///////////////////////////////
-// BEGIN PIECE OF WEIRD CODE //
-///////////////////////////////
-//
-//    tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
-//    
-//    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
-//    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
-//                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
-//                          FMC_SDTR1_TRCD));
-//    
-//    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
-//                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
-//                       (((Timing->SelfRefreshTime)-1) << 8)      |\
-//                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
-//                       (((Timing->RCDDelay)-1) << 24));   
-//		
-///////////////////////////////
-// END PIECE OF WEIRD CODE   //
-///////////////////////////////
+#if 0 /* broken code */
+    tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
+    
+    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+                          FMC_SDTR1_TRCD));
+    
+    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\
+                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+                       (((Timing->SelfRefreshTime)-1) << 8)      |\
+                       (((Timing->WriteRecoveryTime)-1) <<16)    |\
+                       (((Timing->RCDDelay)-1) << 24));   
+    
+    tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
+    
+    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+    tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+                          FMC_SDTR1_TRCD));
+    tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\
+                        (((Timing->RPDelay)-1) << 20)); 
 
+    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
+    Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
+#else
     tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
     
     /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
@@ -1534,10 +1547,8 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim
                        (((Timing->WriteRecoveryTime)-1U) <<16U)    |\
                        (((Timing->RCDDelay)-1U) << 24U));
 
-//
-//    Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
-//
     Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
+#endif
   }   
   
   return HAL_OK;