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authorFredrik Thulin <fredrik@thulin.net>2016-05-23 21:58:32 +0200
committerFredrik Thulin <fredrik@thulin.net>2016-05-23 21:58:32 +0200
commit50f9d40503e5f9cb24241c4c584db3cb94af07aa (patch)
treed3e86e09f808271b065e368fb788267f27316eb7 /libraries/mbed/targets/cmsis/TARGET_STM
parent578d7f5757613898d36fd999a409e5b9f5796136 (diff)
commit bugfix from Pavel fixing initialization of the second SDRAM chip
Diffstat (limited to 'libraries/mbed/targets/cmsis/TARGET_STM')
-rw-r--r--libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c98
1 files changed, 61 insertions, 37 deletions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
index bf28b4b..bdf38fc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c
@@ -1413,23 +1413,31 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
}
else /* FMC_Bank2_SDRAM */
{
- tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
-
- /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
- tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
- FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
- FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
-
- tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
- Init->ReadBurst |\
- Init->ReadPipeDelay);
-
- tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
+///////////////////////////////
+// BEGIN PIECE OF WEIRD CODE //
+///////////////////////////////
+//
+// tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
+//
+// /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+// tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+// FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+// FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+//
+// tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
+// Init->ReadBurst |\
+// Init->ReadPipeDelay);
+//
+///////////////////////////////
+// END PIECE OF WEIRD CODE //
+///////////////////////////////
+
+ tmpr2 = Device->SDCR[FMC_SDRAM_BANK1];
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
- tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
- FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
- FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+ tmpr2 &= ((uint32_t)~(FMC_SDCR2_NC | FMC_SDCR2_NR | FMC_SDCR2_MWID | \
+ FMC_SDCR2_NB | FMC_SDCR2_CAS | FMC_SDCR2_WP | \
+ FMC_SDCR2_SDCLK | FMC_SDCR2_RBURST | FMC_SDCR2_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
Init->RowBitsNumber |\
@@ -1438,7 +1446,9 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe
Init->CASLatency |\
Init->WriteProtection);
- Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+//
+// Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
+//
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
}
@@ -1490,30 +1500,44 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim
}
else /* FMC_Bank2_SDRAM */
{
- tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
-
- /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
- tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
- FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
- FMC_SDTR1_TRCD));
-
- tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
- (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
- (((Timing->SelfRefreshTime)-1) << 8) |\
- (((Timing->WriteRecoveryTime)-1) <<16) |\
- (((Timing->RCDDelay)-1) << 24));
-
+///////////////////////////////
+// BEGIN PIECE OF WEIRD CODE //
+///////////////////////////////
+//
+// tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
+//
+// /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+// tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+// FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+// FMC_SDTR1_TRCD));
+//
+// tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
+// (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
+// (((Timing->SelfRefreshTime)-1) << 8) |\
+// (((Timing->WriteRecoveryTime)-1) <<16) |\
+// (((Timing->RCDDelay)-1) << 24));
+//
+///////////////////////////////
+// END PIECE OF WEIRD CODE //
+///////////////////////////////
+
tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
- tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
- FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
- FMC_SDTR1_TRCD));
- tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
- (((Timing->RPDelay)-1) << 20));
-
- Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
- Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
+ tmpr2 &= ((uint32_t)~(FMC_SDTR2_TMRD | FMC_SDTR2_TXSR | FMC_SDTR2_TRAS | \
+ FMC_SDTR2_TRC | FMC_SDTR2_TWR | FMC_SDTR2_TRP | \
+ FMC_SDTR2_TRCD));
+
+ tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
+ (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
+ (((Timing->SelfRefreshTime)-1U) << 8U) |\
+ (((Timing->WriteRecoveryTime)-1U) <<16U) |\
+ (((Timing->RCDDelay)-1U) << 24U));
+
+//
+// Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
+//
+ Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
}
return HAL_OK;