/*
* stm-ice40mkm.h
* --------------
* Functions for configuring the Lattice iCE40-based master key memory.
*
* Copyright 2021 The Commons Conservancy Cryptech Project
* SPDX-License-Identifier: BSD-3-Clause
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STM32_ICE40MKM_H
#define __STM32_ICE40MKM_H
#include "stm32f4xx_hal.h"
/* iCE40 UltraPlus 5K bitstream parameters */
/*
* the bitstream itself is 104073 bytes
* iCEcube2 adds an extra trailing zero byte
* the bitstream fits in two 64K 256-page sectors
*/
#define ICE40_BITSTREAM_SECTORS 2
/*
* the preamble of the bitstream
*/
#define ICE40_MAGIC_MARKER {0x7e, 0xaa, 0x99, 0x7e}
/* Pins connected to the iCE40 */
/* all pins are connected to I/O port C */
#define ICE40MKM_Port GPIOC
/* active-low reset input */
#define ICE40MKM_CRESET_B_Pin GPIO_PIN_8
/* config done output */
#define ICE40MKM_CDONE_Pin GPIO_PIN_13
/* active-low chip select */
#define ICE40MKM_SPI_CS_N_Pin GPIO_PIN_9
#define ICE40MKM_GPIO_INIT() \
__GPIOC_CLK_ENABLE(); \
gpio_output(ICE40MKM_Port, ICE40MKM_SPI_CS_N_Pin, GPIO_PIN_SET); \
gpio_output(ICE40MKM_Port, ICE40MKM_CRESET_B_Pin, GPIO_PIN_RESET); \
gpio_input(ICE40MKM_Port, ICE40MKM_CDONE_Pin, GPIO_PULLDOWN)
/* macros to set/clear reset and chip-select */
#define _ice40mkm_chip_select() {HAL_GPIO_WritePin(ICE40MKM_Port, ICE40MKM_SPI_CS_N_Pin, GPIO_PIN_RESET);}
#define _ice40mkm_chip_deselect() {HAL_GPIO_WritePin(ICE40MKM_Port, ICE40MKM_SPI_CS_N_Pin, GPIO_PIN_SET);}
#define _ice40mkm_reset_assert() {HAL_GPIO_WritePin(ICE40MKM_Port, ICE40MKM_CRESET_B_Pin, GPIO_PIN_RESET);}
#define _ice40mkm_reset_deassert() {HAL_GPIO_WritePin(ICE40MKM_Port, ICE40MKM_CRESET_B_Pin, GPIO_PIN_SET);}
/* macro to read config done output */
#define _ice40mkm_cdone() (HAL_GPIO_ReadPin(ICE40MKM_Port, ICE40MKM_CDONE_Pin) == GPIO_PIN_SET ? 1 : 0)
/* prototypes */
extern void ice40mkm_init(void);
extern int ice40mkm_configure(void);
#endif /* __STM32_ICE40MKM_H */
