stm32f4xx_hal_cryp.h « TARGET_STM32F4 « TARGET_STM « cmsis « targets « mbed « libraries - sw/stm32

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class="n">DstAddress, uint32_t DataLength) { /* Clear DBM bit */ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; } /* Memory to Peripheral */ else { /* Configure DMA Stream source address */ hdma->Instance->PAR = SrcAddress; /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } } /** * @brief Returns the DMA Stream base address depending on stream number * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24; /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; if (stream_number > 3) { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4); } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)); } return hdma->StreamBaseAddress; } /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/