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authorRob Austein <sra@hactrn.net>2016-03-09 00:49:13 -0500
committerRob Austein <sra@hactrn.net>2016-03-09 00:49:13 -0500
commit8db1d753745bb7b253cf969ff2fb32464b601bf5 (patch)
tree880effa0d7ba08ba70599d203215961246b1a85d /verilog_constants.h
parent8f9c3d1e3c9b2f882032a551b8ca46684ab030ae (diff)
Optional (compile time conditional) software hash cores. At the
moment this is all-or-nothing, but could easily be tweaked to allow compile-time selection of particular hashes.
Diffstat (limited to 'verilog_constants.h')
-rw-r--r--verilog_constants.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/verilog_constants.h b/verilog_constants.h
index 879d2af..dfd102a 100644
--- a/verilog_constants.h
+++ b/verilog_constants.h
@@ -8,7 +8,7 @@
* hand-edited.
*
* Authors: Joachim Strombergson, Paul Selkirk, Rob Austein
- * Copyright (c) 2015, NORDUnet A/S All rights reserved.
+ * Copyright (c) 2015-2016, NORDUnet A/S All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -81,6 +81,7 @@
#define MODE_SHA_512_256 (1 << 2)
#define MODE_SHA_384 (2 << 2)
#define MODE_SHA_512 (3 << 2)
+#define MODE_SHA_MASK (3 << 2)
/*
* RNG cores.