From 8db1d753745bb7b253cf969ff2fb32464b601bf5 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Wed, 9 Mar 2016 00:49:13 -0500 Subject: Optional (compile time conditional) software hash cores. At the moment this is all-or-nothing, but could easily be tweaked to allow compile-time selection of particular hashes. --- verilog_constants.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'verilog_constants.h') diff --git a/verilog_constants.h b/verilog_constants.h index 879d2af..dfd102a 100644 --- a/verilog_constants.h +++ b/verilog_constants.h @@ -8,7 +8,7 @@ * hand-edited. * * Authors: Joachim Strombergson, Paul Selkirk, Rob Austein - * Copyright (c) 2015, NORDUnet A/S All rights reserved. + * Copyright (c) 2015-2016, NORDUnet A/S All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are @@ -81,6 +81,7 @@ #define MODE_SHA_512_256 (1 << 2) #define MODE_SHA_384 (2 << 2) #define MODE_SHA_512 (3 << 2) +#define MODE_SHA_MASK (3 << 2) /* * RNG cores. -- cgit v1.2.3