Tweak build-shadow-tree.py to adjust an existing tree as well as creating a new one.

Original design intent was that the build tree be created once then
left alone, but this turns out to be short-sighted: we really don't
want to have to re-synthesize all of the Verilog code just because
somebody added a new C file to the firmware.

1 files changed, 1 insertions, 3 deletions

diff --git a/Makefile b/Makefile
index 5d62630..0ff5e25 100644
--- a/Makefile
+++ b/Makefile
@@ -58,9 +58,7 @@ sandblast: clean
 
 firmware: shadow ${FIRMWARE_TARBALL}
 
-shadow: build
-
-build:
+shadow:
 	./build-shadow-tree.py
 
 ${FIRMWARE_TARBALL}: ${BITSTREAM} $(sort ${ELVES} ${ELVES:.elf=.bin})