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authorRob Austein <sra@hactrn.net>2016-06-28 23:07:03 -0400
committerRob Austein <sra@hactrn.net>2016-06-28 23:07:03 -0400
commitc07e57d9bd3f5fad8eb36dcda5144a0a2b6224e9 (patch)
treeb755b0647d984d5c5f3c120f196de1c15dcda9a3 /.gitmodules
parent731c5de44a9c4a87c6922e6152ef4a89f6e62815 (diff)
Tweak build-shadow-tree.py to adjust an existing tree as well as creating a new one.
Original design intent was that the build tree be created once then left alone, but this turns out to be short-sighted: we really don't want to have to re-synthesize all of the Verilog code just because somebody added a new C file to the firmware.
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