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-rw-r--r--eagle/lbr/Alpha-IC.lbr1560
1 files changed, 1559 insertions, 1 deletions
diff --git a/eagle/lbr/Alpha-IC.lbr b/eagle/lbr/Alpha-IC.lbr
index 6486c84..453e73b 100644
--- a/eagle/lbr/Alpha-IC.lbr
+++ b/eagle/lbr/Alpha-IC.lbr
@@ -6,7 +6,7 @@
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
-<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
<layer number="2" name="Route2" color="1" fill="3" visible="no" active="yes"/>
@@ -244,6 +244,1092 @@ Auto generated by &lt;i&gt;make-symbol-device-package-bsdl.ulp Rev. 44&lt;/i&gt;
<text x="-3.88" y="11.635" size="1.27" layer="25">&gt;NAME</text>
<text x="-5.88" y="-13.905" size="1.27" layer="27">&gt;VALUE</text>
</package>
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<symbol name="IS45S32160F-TSOP86L">
@@ -334,6 +1420,249 @@ Auto generated by &lt;i&gt;make-symbol-device-package-bsdl.ulp Rev. 44&lt;/i&gt;
<text x="-15.24" y="8.89" size="1.778" layer="95">&gt;NAME</text>
<text x="-15.24" y="2.54" size="1.778" layer="96">&gt;VALUE</text>
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+<pin name="VSS@170" x="20.32" y="-20.32" length="short" direction="pwr" rot="R180"/>
+<pin name="VSS@184" x="20.32" y="-22.86" length="short" direction="pwr" rot="R180"/>
+<pin name="VSS@202" x="20.32" y="-25.4" length="short" direction="pwr" rot="R180"/>
+<wire x1="-17.78" y1="-35.56" x2="-17.78" y2="38.1" width="0.254" layer="94"/>
+<wire x1="-17.78" y1="-35.56" x2="17.78" y2="-35.56" width="0.254" layer="94"/>
+<text x="-17.78" y="-40.64" size="1.778" layer="95">&gt;NAME</text>
+<text x="-17.78" y="-45.72" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="VCAP1@92" x="-2.54" y="40.64" length="short" rot="R270"/>
+<pin name="VCAP2@148" x="2.54" y="40.64" length="short" rot="R270"/>
+</symbol>
+<symbol name="STM32F429_LQFP-208_FMC">
+<description>The STM FMC bus</description>
+<wire x1="-30.48" y1="-68.58" x2="25.4" y2="-68.58" width="0.254" layer="94"/>
+<wire x1="25.4" y1="-68.58" x2="25.4" y2="60.96" width="0.254" layer="94"/>
+<wire x1="25.4" y1="60.96" x2="-30.48" y2="60.96" width="0.254" layer="94"/>
+<wire x1="-30.48" y1="-68.58" x2="-30.48" y2="60.96" width="0.254" layer="94"/>
+<text x="-30.48" y="68.58" size="1.778" layer="95">&gt;NAME</text>
+<text x="-30.48" y="63.5" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="PH13/FMC_D21" x="27.94" y="0" length="short" rot="R180"/>
+<pin name="PH14/FMC_D22" x="27.94" y="-2.54" length="short" rot="R180"/>
+<pin name="PH15/FMC_D23" x="27.94" y="-5.08" length="short" rot="R180"/>
+<pin name="PI0/FMC_D24" x="27.94" y="-7.62" length="short" rot="R180"/>
+<pin name="PI1/FMC_D25" x="27.94" y="-10.16" length="short" rot="R180"/>
+<pin name="PI2/FMC_D26" x="27.94" y="-12.7" length="short" rot="R180"/>
+<pin name="PE7/FMC_D4" x="27.94" y="43.18" length="short" rot="R180"/>
+<pin name="PE8/FMC_D5" x="27.94" y="40.64" length="short" rot="R180"/>
+<pin name="PE9/FMC_D6" x="27.94" y="38.1" length="short" rot="R180"/>
+<pin name="PE10/FMC_D7" x="27.94" y="35.56" length="short" rot="R180"/>
+<pin name="PE11/FMC_D8" x="27.94" y="33.02" length="short" rot="R180"/>
+<pin name="PE12/FMC_D9" x="27.94" y="30.48" length="short" rot="R180"/>
+<pin name="PE13/FMC_D10" x="27.94" y="27.94" length="short" rot="R180"/>
+<pin name="PE14/FMC_D11" x="27.94" y="25.4" length="short" rot="R180"/>
+<pin name="PE15/FMC_D12" x="27.94" y="22.86" length="short" rot="R180"/>
+<pin name="PD8/FMC_D13" x="27.94" y="20.32" length="short" rot="R180"/>
+<pin name="PD9/FMC_D14" x="27.94" y="17.78" length="short" rot="R180"/>
+<pin name="PD10/FMC_D15" x="27.94" y="15.24" length="short" rot="R180"/>
+<pin name="PD14/FMC_D0" x="27.94" y="53.34" length="short" rot="R180"/>
+<pin name="PD15/FMC_D1" x="27.94" y="50.8" length="short" rot="R180"/>
+<pin name="PD0/FMC_D2" x="27.94" y="48.26" length="short" rot="R180"/>
+<pin name="PD1/FMC_D3" x="27.94" y="45.72" length="short" rot="R180"/>
+<pin name="PI6/FMC_D28" x="27.94" y="-17.78" length="short" rot="R180"/>
+<pin name="PI7/FMC_D29" x="27.94" y="-20.32" length="short" rot="R180"/>
+<pin name="PH8/FMC_D16" x="27.94" y="12.7" length="short" rot="R180"/>
+<pin name="PH9/FMC_D17" x="27.94" y="10.16" length="short" rot="R180"/>
+<pin name="PH10/FMC_D18" x="27.94" y="7.62" length="short" rot="R180"/>
+<pin name="PH11/FMC_D19" x="27.94" y="5.08" length="short" rot="R180"/>
+<pin name="PH12/FMC_D20" x="27.94" y="2.54" length="short" rot="R180"/>
+<pin name="PI9/FMC_D30" x="27.94" y="-22.86" length="short" rot="R180"/>
+<pin name="PI10/FMC_D31" x="27.94" y="-25.4" length="short" rot="R180"/>
+<pin name="PI3/FMC_D27" x="27.94" y="-15.24" length="short" rot="R180"/>
+<pin name="FMC_A23/PE2" x="-33.02" y="-5.08" length="short"/>
+<pin name="FMC_A19/PE3" x="-33.02" y="5.08" length="short"/>
+<pin name="FMC_A20/PE4" x="-33.02" y="2.54" length="short"/>
+<pin name="FMC_A21/PE5" x="-33.02" y="0" length="short"/>
+<pin name="FMC_A22/PE6" x="-33.02" y="-2.54" length="short"/>
+<pin name="FMC_A0/PF0" x="-33.02" y="53.34" length="short"/>
+<pin name="FMC_A1/PF1" x="-33.02" y="50.8" length="short"/>
+<pin name="FMC_A2/PF2" x="-33.02" y="48.26" length="short"/>
+<pin name="FMC_A3/PF3" x="-33.02" y="45.72" length="short"/>
+<pin name="FMC_A4/PF4" x="-33.02" y="43.18" length="short"/>
+<pin name="FMC_A5/PF5" x="-33.02" y="40.64" length="short"/>
+<pin name="FMC_A6/PF12" x="-33.02" y="38.1" length="short"/>
+<pin name="FMC_A7/PF13" x="-33.02" y="35.56" length="short"/>
+<pin name="FMC_A8/PF14" x="-33.02" y="33.02" length="short"/>
+<pin name="FMC_A9/PF15" x="-33.02" y="30.48" length="short"/>
+<pin name="FMC_A10/PG0" x="-33.02" y="27.94" length="short"/>
+<pin name="FMC_A11/PG1" x="-33.02" y="25.4" length="short"/>
+<pin name="FMC_A16/PD11" x="-33.02" y="12.7" length="short"/>
+<pin name="FMC_A17/PD12" x="-33.02" y="10.16" length="short"/>
+<pin name="FMC_A18/PD13" x="-33.02" y="7.62" length="short"/>
+<pin name="FMC_A12/PG2" x="-33.02" y="22.86" length="short"/>
+<pin name="FMC_A13/PG3" x="-33.02" y="20.32" length="short"/>
+<pin name="FMC_A14/PG4" x="-33.02" y="17.78" length="short"/>
+<pin name="FMC_A15/PG5" x="-33.02" y="15.24" length="short"/>
+<pin name="FMC_A24/PG13" x="-33.02" y="-7.62" length="short"/>
+<pin name="FMC_A25/PG14" x="-33.02" y="-10.16" length="short"/>
+<pin name="FMC_CLK/PD3" x="-33.02" y="-40.64" length="short"/>
+<pin name="FMC_NOE/PD4" x="-33.02" y="-43.18" length="short"/>
+<pin name="FMC_NWE/PD5" x="-33.02" y="-45.72" length="short"/>
+<pin name="FMC_NWAIT/PD6" x="-33.02" y="-48.26" length="short"/>
+<pin name="FMC_NE1/PD7" x="-33.02" y="-50.8" length="short"/>
+<pin name="PG15/FMC_SDNCAS" x="27.94" y="-55.88" length="short" rot="R180"/>
+<pin name="PB5/FMC_SDCKE1" x="27.94" y="-50.8" length="short" rot="R180"/>
+<pin name="PB6/FMC_SDNE1" x="27.94" y="-43.18" length="short" rot="R180"/>
+<pin name="FMC_NL/PB7" x="-33.02" y="-33.02" length="short"/>
+<pin name="FMC_NBL2/PI4" x="-33.02" y="-22.86" length="short"/>
+<pin name="FMC_NBL3/PI5" x="-33.02" y="-25.4" length="short"/>
+<pin name="FMC_NBL0/PE0" x="-33.02" y="-17.78" length="short"/>
+<pin name="FMC_NBL1/PE1" x="-33.02" y="-20.32" length="short"/>
+<pin name="PG8/FMC_SDCLK" x="27.94" y="-33.02" length="short" rot="R180"/>
+<pin name="PF11/FMC_SDNRAS" x="27.94" y="-58.42" length="short" rot="R180"/>
+<pin name="PC0/FMC_SDNWE" x="27.94" y="-35.56" length="short" rot="R180"/>
+<pin name="PC2/FMC_SDNE0" x="27.94" y="-40.64" length="short" rot="R180"/>
+<pin name="PC3/FMC_SDCKE0" x="27.94" y="-48.26" length="short" rot="R180"/>
+</symbol>
</symbols>
<devicesets>
<deviceset name="IS45S32160F" prefix="IC">
@@ -435,6 +1764,235 @@ Clock frequency: 166, 143 MHz</description>
</device>
</devices>
</deviceset>
+<deviceset name="STM32F429BIT6">
+<description>STM32F429 Cortex-M4 CPU
+180 MHz, 256 KB RAM, 2 MB Flash</description>
+<gates>
+<gate name="IO" symbol="STM32F429_LQFP-208_IO" x="30.48" y="-10.16"/>
+<gate name="CFG" symbol="STM32F429_LQFP-208_CFG" x="-78.74" y="-12.7"/>
+<gate name="PWR" symbol="STM32F429_LQFP-208_PWR" x="-154.94" y="-12.7"/>
+<gate name="FMC" symbol="STM32F429_LQFP-208_FMC" x="129.54" y="5.08"/>
+</gates>
+<devices>
+<device name="" package="LQFP-208">
+<connects>
+<connect gate="CFG" pin="BOOT0@197" pad="197"/>
+<connect gate="CFG" pin="NRST" pad="34"/>
+<connect gate="CFG" pin="OSC_IN/PH0" pad="32"/>
+<connect gate="CFG" pin="OSC_OUT/PH1" pad="33"/>
+<connect gate="CFG" pin="PA13/JTMS-SWDIO" pad="147"/>
+<connect gate="CFG" pin="PA14/JTCK-SWCLK" pad="159"/>
+<connect gate="CFG" pin="PA15/JTDI" pad="160"/>
+<connect gate="CFG" pin="PB2/BOOT1" pad="63"/>
+<connect gate="CFG" pin="PB3/JTDO/TRACESWO" pad="192"/>
+<connect gate="CFG" pin="PB4/NJTRST" pad="193"/>
+<connect gate="CFG" pin="PDR_ON@203" pad="203"/>
+<connect gate="CFG" pin="VREF+@41" pad="41"/>
+<connect gate="FMC" pin="FMC_A0/PF0" pad="16"/>
+<connect gate="FMC" pin="FMC_A1/PF1" pad="17"/>
+<connect gate="FMC" pin="FMC_A10/PG0" pad="77"/>
+<connect gate="FMC" pin="FMC_A11/PG1" pad="78"/>
+<connect gate="FMC" pin="FMC_A12/PG2" pad="129"/>
+<connect gate="FMC" pin="FMC_A13/PG3" pad="130"/>
+<connect gate="FMC" pin="FMC_A14/PG4" pad="131"/>
+<connect gate="FMC" pin="FMC_A15/PG5" pad="132"/>
+<connect gate="FMC" pin="FMC_A16/PD11" pad="111"/>
+<connect gate="FMC" pin="FMC_A17/PD12" pad="112"/>
+<connect gate="FMC" pin="FMC_A18/PD13" pad="113"/>
+<connect gate="FMC" pin="FMC_A19/PE3" pad="2"/>
+<connect gate="FMC" pin="FMC_A2/PF2" pad="18"/>
+<connect gate="FMC" pin="FMC_A20/PE4" pad="3"/>
+<connect gate="FMC" pin="FMC_A21/PE5" pad="4"/>
+<connect gate="FMC" pin="FMC_A22/PE6" pad="5"/>
+<connect gate="FMC" pin="FMC_A23/PE2" pad="1"/>
+<connect gate="FMC" pin="FMC_A24/PG13" pad="182"/>
+<connect gate="FMC" pin="FMC_A25/PG14" pad="183"/>
+<connect gate="FMC" pin="FMC_A3/PF3" pad="22"/>
+<connect gate="FMC" pin="FMC_A4/PF4" pad="23"/>
+<connect gate="FMC" pin="FMC_A5/PF5" pad="24"/>
+<connect gate="FMC" pin="FMC_A6/PF12" pad="71"/>
+<connect gate="FMC" pin="FMC_A7/PF13" pad="74"/>
+<connect gate="FMC" pin="FMC_A8/PF14" pad="75"/>
+<connect gate="FMC" pin="FMC_A9/PF15" pad="76"/>
+<connect gate="FMC" pin="FMC_CLK/PD3" pad="167"/>
+<connect gate="FMC" pin="FMC_NBL0/PE0" pad="200"/>
+<connect gate="FMC" pin="FMC_NBL1/PE1" pad="201"/>
+<connect gate="FMC" pin="FMC_NBL2/PI4" pad="205"/>
+<connect gate="FMC" pin="FMC_NBL3/PI5" pad="206"/>
+<connect gate="FMC" pin="FMC_NE1/PD7" pad="173"/>
+<connect gate="FMC" pin="FMC_NL/PB7" pad="196"/>
+<connect gate="FMC" pin="FMC_NOE/PD4" pad="168"/>
+<connect gate="FMC" pin="FMC_NWAIT/PD6" pad="172"/>
+<connect gate="FMC" pin="FMC_NWE/PD5" pad="169"/>
+<connect gate="FMC" pin="PB5/FMC_SDCKE1" pad="194"/>
+<connect gate="FMC" pin="PB6/FMC_SDNE1" pad="195"/>
+<connect gate="FMC" pin="PC0/FMC_SDNWE" pad="35"/>
+<connect gate="FMC" pin="PC2/FMC_SDNE0" pad="37"/>
+<connect gate="FMC" pin="PC3/FMC_SDCKE0" pad="38"/>
+<connect gate="FMC" pin="PD0/FMC_D2" pad="164"/>
+<connect gate="FMC" pin="PD1/FMC_D3" pad="165"/>
+<connect gate="FMC" pin="PD10/FMC_D15" pad="110"/>
+<connect gate="FMC" pin="PD14/FMC_D0" pad="116"/>
+<connect gate="FMC" pin="PD15/FMC_D1" pad="117"/>
+<connect gate="FMC" pin="PD8/FMC_D13" pad="108"/>
+<connect gate="FMC" pin="PD9/FMC_D14" pad="109"/>
+<connect gate="FMC" pin="PE10/FMC_D7" pad="84"/>
+<connect gate="FMC" pin="PE11/FMC_D8" pad="85"/>
+<connect gate="FMC" pin="PE12/FMC_D9" pad="86"/>
+<connect gate="FMC" pin="PE13/FMC_D10" pad="87"/>
+<connect gate="FMC" pin="PE14/FMC_D11" pad="88"/>
+<connect gate="FMC" pin="PE15/FMC_D12" pad="89"/>
+<connect gate="FMC" pin="PE7/FMC_D4" pad="79"/>
+<connect gate="FMC" pin="PE8/FMC_D5" pad="80"/>
+<connect gate="FMC" pin="PE9/FMC_D6" pad="81"/>
+<connect gate="FMC" pin="PF11/FMC_SDNRAS" pad="70"/>
+<connect gate="FMC" pin="PG15/FMC_SDNCAS" pad="191"/>
+<connect gate="FMC" pin="PG8/FMC_SDCLK" pad="135"/>
+<connect gate="FMC" pin="PH10/FMC_D18" pad="100"/>
+<connect gate="FMC" pin="PH11/FMC_D19" pad="101"/>
+<connect gate="FMC" pin="PH12/FMC_D20" pad="102"/>
+<connect gate="FMC" pin="PH13/FMC_D21" pad="151"/>
+<connect gate="FMC" pin="PH14/FMC_D22" pad="152"/>
+<connect gate="FMC" pin="PH15/FMC_D23" pad="153"/>
+<connect gate="FMC" pin="PH8/FMC_D16" pad="98"/>
+<connect gate="FMC" pin="PH9/FMC_D17" pad="99"/>
+<connect gate="FMC" pin="PI0/FMC_D24" pad="154"/>
+<connect gate="FMC" pin="PI1/FMC_D25" pad="155"/>
+<connect gate="FMC" pin="PI10/FMC_D31" pad="12"/>
+<connect gate="FMC" pin="PI2/FMC_D26" pad="156"/>
+<connect gate="FMC" pin="PI3/FMC_D27" pad="157"/>
+<connect gate="FMC" pin="PI6/FMC_D28" pad="207"/>
+<connect gate="FMC" pin="PI7/FMC_D29" pad="208"/>
+<connect gate="FMC" pin="PI9/FMC_D30" pad="11"/>
+<connect gate="IO" pin="FMC_CD/PF9" pad="30"/>
+<connect gate="IO" pin="FMC_INT2/PG6" pad="133"/>
+<connect gate="IO" pin="FMC_INT3/PG7" pad="134"/>
+<connect gate="IO" pin="FMC_INTR/PF10" pad="31"/>
+<connect gate="IO" pin="FMC_NCE4_1/FMC_NE3/PG10" pad="179"/>
+<connect gate="IO" pin="FMC_NCE4_2/PG11" pad="180"/>
+<connect gate="IO" pin="FMC_NE2/FMC_NCE3/PG9" pad="178"/>
+<connect gate="IO" pin="FMC_NE4/PG12" pad="181"/>
+<connect gate="IO" pin="FMC_NIORD/PF6" pad="27"/>
+<connect gate="IO" pin="FMC_NIOWR/PF8" pad="29"/>
+<connect gate="IO" pin="FMC_NREG/PF7" pad="28"/>
+<connect gate="IO" pin="FMC_SDCKE0/PH2" pad="46"/>
+<connect gate="IO" pin="FMC_SDCKE1/PH7" pad="97"/>
+<connect gate="IO" pin="FMC_SDNE1/PH6" pad="96"/>
+<connect gate="IO" pin="I2C2_SCL/PH4" pad="48"/>
+<connect gate="IO" pin="I2C2_SDA/FMC_SDNWE/PH5" pad="49"/>
+<connect gate="IO" pin="PA4" pad="53"/>
+<connect gate="IO" pin="PA8" pad="142"/>
+<connect gate="IO" pin="PB0" pad="61"/>
+<connect gate="IO" pin="PB1" pad="62"/>
+<connect gate="IO" pin="PB10" pad="90"/>
+<connect gate="IO" pin="PB11" pad="91"/>
+<connect gate="IO" pin="PB12" pad="104"/>
+<connect gate="IO" pin="PB8/I2C1_SCL" pad="198"/>
+<connect gate="IO" pin="PB9/I2C1_SDA" pad="199"/>
+<connect gate="IO" pin="PC1" pad="36"/>
+<connect gate="IO" pin="PC13" pad="8"/>
+<connect gate="IO" pin="PC14" pad="9"/>
+<connect gate="IO" pin="PC15" pad="10"/>
+<connect gate="IO" pin="PC4" pad="57"/>
+<connect gate="IO" pin="PC5" pad="58"/>
+<connect gate="IO" pin="PC6" pad="138"/>
+<connect gate="IO" pin="PC7" pad="139"/>
+<connect gate="IO" pin="PH3/FMC_SDNE0" pad="47"/>
+<connect gate="IO" pin="PI11" pad="13"/>
+<connect gate="IO" pin="PI12" pad="19"/>
+<connect gate="IO" pin="PI13" pad="20"/>
+<connect gate="IO" pin="PI14" pad="21"/>
+<connect gate="IO" pin="PI15" pad="64"/>
+<connect gate="IO" pin="PI8" pad="7"/>
+<connect gate="IO" pin="PJ0" pad="65"/>
+<connect gate="IO" pin="PJ1" pad="66"/>
+<connect gate="IO" pin="PJ10" pad="122"/>
+<connect gate="IO" pin="PJ11" pad="123"/>
+<connect gate="IO" pin="PJ12" pad="174"/>
+<connect gate="IO" pin="PJ13" pad="175"/>
+<connect gate="IO" pin="PJ14" pad="176"/>
+<connect gate="IO" pin="PJ15" pad="177"/>
+<connect gate="IO" pin="PJ2" pad="67"/>
+<connect gate="IO" pin="PJ3" pad="68"/>
+<connect gate="IO" pin="PJ4" pad="69"/>
+<connect gate="IO" pin="PJ5" pad="95"/>
+<connect gate="IO" pin="PJ6" pad="118"/>
+<connect gate="IO" pin="PJ7" pad="119"/>
+<connect gate="IO" pin="PJ8" pad="120"/>
+<connect gate="IO" pin="PJ9" pad="121"/>
+<connect gate="IO" pin="PK0" pad="126"/>
+<connect gate="IO" pin="PK1" pad="127"/>
+<connect gate="IO" pin="PK2" pad="128"/>
+<connect gate="IO" pin="PK3" pad="186"/>
+<connect gate="IO" pin="PK4" pad="187"/>
+<connect gate="IO" pin="PK5" pad="188"/>
+<connect gate="IO" pin="PK6" pad="189"/>
+<connect gate="IO" pin="PK7" pad="190"/>
+<connect gate="IO" pin="SDIO_CK/SPI3_MOSI/PC12" pad="163"/>
+<connect gate="IO" pin="SDIO_CMD/PD2" pad="166"/>
+<connect gate="IO" pin="SDIO_D0/PC8" pad="140"/>
+<connect gate="IO" pin="SDIO_D1/PC9" pad="141"/>
+<connect gate="IO" pin="SDIO_D2/SPI3_SCK/PC10" pad="161"/>
+<connect gate="IO" pin="SDIO_D3/SPI3_MISO/PC11" pad="162"/>
+<connect gate="IO" pin="SPI1_MISO/PA6" pad="55"/>
+<connect gate="IO" pin="SPI1_MOSI/PA7" pad="56"/>
+<connect gate="IO" pin="SPI1_SCK/PA5" pad="54"/>
+<connect gate="IO" pin="SPI2_MISO/PB14" pad="106"/>
+<connect gate="IO" pin="SPI2_MOSI/PB15" pad="107"/>
+<connect gate="IO" pin="SPI2_SCK/PB13" pad="105"/>
+<connect gate="IO" pin="USART1_CTS/PA11" pad="145"/>
+<connect gate="IO" pin="USART1_RTS/PA12" pad="146"/>
+<connect gate="IO" pin="USART1_RX/PA10" pad="144"/>
+<connect gate="IO" pin="USART1_TX/PA9" pad="143"/>
+<connect gate="IO" pin="USART2_CTS/WKUP/PA0" pad="43"/>
+<connect gate="IO" pin="USART2_RTS/PA1" pad="44"/>
+<connect gate="IO" pin="USART2_RX/PA3" pad="50"/>
+<connect gate="IO" pin="USART2_TX/PA2" pad="45"/>
+<connect gate="PWR" pin="VBAT@6" pad="6"/>
+<connect gate="PWR" pin="VCAP1@92" pad="92"/>
+<connect gate="PWR" pin="VCAP2@148" pad="148"/>
+<connect gate="PWR" pin="VDD@103" pad="103"/>
+<connect gate="PWR" pin="VDD@115" pad="115"/>
+<connect gate="PWR" pin="VDD@124" pad="124"/>
+<connect gate="PWR" pin="VDD@137" pad="137"/>
+<connect gate="PWR" pin="VDD@15" pad="15"/>
+<connect gate="PWR" pin="VDD@150" pad="150"/>
+<connect gate="PWR" pin="VDD@158" pad="158"/>
+<connect gate="PWR" pin="VDD@171" pad="171"/>
+<connect gate="PWR" pin="VDD@185" pad="185"/>
+<connect gate="PWR" pin="VDD@204" pad="204"/>
+<connect gate="PWR" pin="VDD@26" pad="26"/>
+<connect gate="PWR" pin="VDD@39" pad="39"/>
+<connect gate="PWR" pin="VDD@52" pad="52"/>
+<connect gate="PWR" pin="VDD@59" pad="59"/>
+<connect gate="PWR" pin="VDD@73" pad="73"/>
+<connect gate="PWR" pin="VDD@83" pad="83"/>
+<connect gate="PWR" pin="VDD@94" pad="94"/>
+<connect gate="PWR" pin="VDDA@42" pad="42"/>
+<connect gate="PWR" pin="VSS@114" pad="114"/>
+<connect gate="PWR" pin="VSS@125" pad="125"/>
+<connect gate="PWR" pin="VSS@136" pad="136"/>
+<connect gate="PWR" pin="VSS@14" pad="14"/>
+<connect gate="PWR" pin="VSS@149" pad="149"/>
+<connect gate="PWR" pin="VSS@170" pad="170"/>
+<connect gate="PWR" pin="VSS@184" pad="184"/>
+<connect gate="PWR" pin="VSS@202" pad="202"/>
+<connect gate="PWR" pin="VSS@25" pad="25"/>
+<connect gate="PWR" pin="VSS@51" pad="51"/>
+<connect gate="PWR" pin="VSS@60" pad="60"/>
+<connect gate="PWR" pin="VSS@72" pad="72"/>
+<connect gate="PWR" pin="VSS@82" pad="82"/>
+<connect gate="PWR" pin="VSS@93" pad="93"/>
+<connect gate="PWR" pin="VSSA@40" pad="40"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="OC_FARNELL" value="2469581" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
</devicesets>
</library>
</drawing>