diff options
| author | Fredrik Thulin <fredrik@thulin.net> | 2015-12-01 16:58:07 +0100 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2015-12-01 16:58:07 +0100 |
| commit | 7744f0e3b45b5f0406853de918443e1636785302 (patch) | |
| tree | 88f0b62b0d6057c1bb89dfbcb094c5e4935432f2 /eagle | |
| parent | 0e6e4994659c64b7f0ccde0bd7d54f9b302555ae (diff) | |
fixed most of the FMC bus, grouped components.
Diffstat (limited to 'eagle')
| -rw-r--r-- | eagle/alpha/rev02/rev02.brd | 6990 | ||||
| -rw-r--r-- | eagle/alpha/rev02/rev02.sch | 557 |
2 files changed, 3728 insertions, 3819 deletions
diff --git a/eagle/alpha/rev02/rev02.brd b/eagle/alpha/rev02/rev02.brd index 0c7755d..1f523cf 100644 --- a/eagle/alpha/rev02/rev02.brd +++ b/eagle/alpha/rev02/rev02.brd @@ -6,7 +6,7 @@ <setting alwaysvectorfont="no"/> <setting verticaltext="up"/> </settings> -<grid distance="20" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="25" altunitdist="mil" altunit="mil"/> +<grid distance="40" unitdist="mil" unit="mil" style="lines" multiple="1" display="yes" altdistance="25" altunitdist="mil" altunit="mil"/> <layers> <layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> <layer number="2" name="POWER" color="1" fill="3" visible="no" active="yes"/> @@ -141,53 +141,53 @@ </layers> <board> <plain> -<wire x1="101.7808" y1="78.8456" x2="1.7808" y2="78.8456" width="0" layer="20"/> -<wire x1="1.7808" y1="78.8456" x2="1.7808" y2="8.8456" width="0" layer="20"/> -<wire x1="1.7808" y1="8.8456" x2="101.7808" y2="8.8456" width="0" layer="20"/> -<wire x1="101.7808" y1="8.8456" x2="101.7808" y2="78.8456" width="0" layer="20"/> -<text x="53.0352" y="70.7136" size="1.27" layer="21" font="vector" ratio="15">https://cryptech.is/ +<wire x1="120.0688" y1="80.7176" x2="20.0688" y2="80.7176" width="0" layer="20"/> +<wire x1="20.0688" y1="80.7176" x2="20.0688" y2="0.7176" width="0" layer="20"/> +<wire x1="20.0688" y1="0.7176" x2="120.0688" y2="0.7176" width="0" layer="20"/> +<wire x1="120.0688" y1="0.7176" x2="120.0688" y2="80.7176" width="0" layer="20"/> +<text x="98.7552" y="75.7936" size="1.27" layer="21" font="vector" ratio="15">https://cryptech.is/ Alpha rev02</text> -<text x="94.7244" y="72.7916" size="1.27" layer="1" font="vector" ratio="17" distance="51" rot="R180" align="bottom-center">rev 02</text> -<text x="22.5552" y="27.7368" size="0.8128" layer="21">5V</text> -<text x="27.432" y="27.7368" size="0.8128" layer="21">GND</text> -<text x="24.6888" y="27.7368" size="0.8128" layer="21">3V3</text> -<text x="90.0374" y="72.6864" size="1.016" layer="21" font="vector">GND +<text x="113.0124" y="64.6636" size="1.27" layer="1" font="vector" ratio="17" distance="51" rot="R180" align="bottom-center">rev 02</text> +<text x="40.8432" y="19.6088" size="0.8128" layer="21">5V</text> +<text x="45.72" y="19.6088" size="0.8128" layer="21">GND</text> +<text x="42.9768" y="19.6088" size="0.8128" layer="21">3V3</text> +<text x="108.3254" y="64.5584" size="1.016" layer="21" font="vector">GND pad</text> -<text x="14.2328" y="45.027" size="0.8128" layer="21" font="vector" rot="R270">NOISY +<text x="32.5208" y="36.899" size="0.8128" layer="21" font="vector" rot="R270">NOISY DIODE</text> -<rectangle x1="93.029" y1="74.1406" x2="97.474" y2="78.5856" layer="30" rot="R180"/> -<rectangle x1="93.029" y1="74.1406" x2="97.474" y2="78.5856" layer="29" rot="R180"/> -<text x="37.4904" y="12.4968" size="0.8128" layer="21">3V3</text> -<text x="40.8432" y="12.4968" size="0.8128" layer="21">1</text> -<text x="43.2816" y="12.4968" size="0.8128" layer="21">2</text> -<text x="45.72" y="12.4968" size="0.8128" layer="21">3</text> -<text x="48.1584" y="12.4968" size="0.8128" layer="21">4</text> -<text x="50.9016" y="12.4968" size="0.8128" layer="21">5</text> -<text x="53.34" y="12.4968" size="0.8128" layer="21">6</text> -<text x="56.0832" y="12.4968" size="0.8128" layer="21">7</text> -<text x="58.5216" y="12.4968" size="0.8128" layer="21">8</text> -<text x="60.3504" y="12.4968" size="0.8128" layer="21">GND</text> -<text x="31.0896" y="21.6408" size="0.8128" layer="21">RST</text> -<text x="33.8328" y="21.6408" size="0.8128" layer="21">SCK</text> -<text x="36.2712" y="21.6408" size="0.8128" layer="21">MISO</text> -<text x="31.0896" y="14.6304" size="0.8128" layer="21">GND</text> -<text x="34.1376" y="14.6304" size="0.8128" layer="21">SI</text> -<text x="35.9664" y="14.6304" size="0.8128" layer="21">3V3</text> -<text x="63.5508" y="12.8016" size="0.8128" layer="21">GND</text> -<text x="66.294" y="12.8016" size="0.8128" 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</signal> <signal name="FMC_NL"> <contactref element="U$1" pad="196"/> -<wire x1="57.2012" y1="47.0892" x2="56.1108" y2="47.0892" width="0.3048" layer="1"/> -<wire x1="50.7972" y1="52.4028" x2="56.1108" y2="47.0892" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="38.9612" x2="74.3988" y2="38.9612" width="0.3048" layer="1"/> +<wire x1="69.0852" y1="44.2748" x2="74.3988" y2="38.9612" width="0.3048" layer="1"/> +<contactref element="U7" pad="R6"/> +<wire x1="46.0808" y1="63.2088" x2="69.0852" y2="44.2748" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_D28" class="2"> <contactref element="U$1" pad="207"/> -<wire x1="57.2012" y1="41.6028" x2="51.5388" y2="41.6028" width="0.3048" layer="1"/> -<wire x1="51.5388" y1="41.6028" x2="48.1584" y2="44.9832" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="33.4748" x2="69.8268" y2="33.4748" width="0.3048" layer="1"/> +<wire x1="69.8268" y1="33.4748" x2="66.4464" y2="36.8552" width="0.3048" layer="1"/> +<contactref element="U7" pad="U5"/> +<wire x1="66.4464" y1="36.8552" x2="44.0808" y2="64.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_D29" class="2"> <contactref element="U$1" pad="208"/> -<wire x1="57.2012" y1="41.0948" x2="51.1324" y2="41.0948" width="0.3048" layer="1"/> -<wire x1="51.1324" y1="41.0948" x2="47.5488" y2="44.6784" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="32.9668" x2="69.4204" y2="32.9668" width="0.3048" layer="1"/> +<wire x1="69.4204" y1="32.9668" x2="65.8368" y2="36.5504" width="0.3048" layer="1"/> +<contactref element="U7" pad="W6"/> +<wire x1="65.8368" y1="36.5504" x2="42.0808" y2="63.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_D27" class="2"> <contactref element="U$1" pad="157"/> -<wire x1="57.2012" y1="66.5964" x2="53.4084" y2="66.5964" width="0.3048" layer="1"/> -<wire x1="53.4084" y1="66.5964" x2="50.6448" y2="63.8328" width="0.3048" layer="1"/> -<wire x1="50.6448" y1="63.8328" x2="50.292" y2="63.8328" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="58.4684" x2="71.6964" y2="58.4684" width="0.3048" layer="1"/> +<wire x1="71.6964" y1="58.4684" x2="68.9328" y2="55.7048" width="0.3048" layer="1"/> +<wire x1="68.9328" y1="55.7048" x2="68.58" y2="55.7048" width="0.3048" layer="1"/> +<contactref element="U7" pad="T5"/> +<wire x1="45.0808" y1="64.2088" x2="68.58" y2="55.7048" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_D3" class="2"> <contactref element="U$1" pad="165"/> -<wire x1="57.2012" y1="62.5832" x2="50.3224" y2="62.5832" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="54.4552" x2="68.6104" y2="54.4552" width="0.3048" layer="1"/> +<contactref element="U7" pad="U2"/> +<wire x1="44.0808" y1="67.2088" x2="68.6104" y2="54.4552" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_NOE"> <contactref element="U$1" pad="168"/> -<wire x1="57.2012" y1="61.0846" x2="50.5918" y2="61.0846" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="52.9566" x2="68.8798" y2="52.9566" width="0.3048" layer="1"/> +<contactref element="U7" pad="T6"/> +<wire x1="45.0808" y1="63.2088" x2="68.8798" y2="52.9566" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_NWE"> <contactref element="U$1" pad="169"/> -<wire x1="51.6332" y1="60.602" x2="57.2012" y2="60.602" width="0.3048" layer="1"/> +<wire x1="69.9212" y1="52.474" x2="75.4892" y2="52.474" width="0.3048" layer="1"/> +<contactref element="U7" pad="AA6"/> +<wire x1="40.0808" y1="63.2088" x2="69.9212" y2="52.474" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_NWAIT"> <contactref element="U$1" pad="172"/> -<wire x1="57.2012" y1="59.1034" x2="55.669" y2="59.1034" width="0.3048" layer="1"/> -<wire x1="55.669" y1="59.1034" x2="51.102" y2="54.5364" width="0.3048" layer="1"/> +<wire x1="75.4892" y1="50.9754" x2="73.957" y2="50.9754" width="0.3048" layer="1"/> +<wire x1="73.957" y1="50.9754" x2="69.39" y2="46.4084" width="0.3048" layer="1"/> +<contactref element="U7" pad="Y6"/> +<wire x1="41.0808" y1="63.2088" x2="69.39" y2="46.4084" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_A19" class="3"> <contactref element="U$1" pad="2"/> -<wire x1="59.538" y1="39.266" x2="59.538" y2="37.9788" width="0.3048" layer="1"/> -<wire x1="59.538" y1="37.9788" x2="59.1792" y2="37.62" width="0.3048" layer="1"/> -<wire x1="59.1792" y1="37.62" x2="53.6928" y2="37.62" width="0.3048" layer="1"/> -<wire x1="53.6928" y1="37.62" x2="47.244" y2="44.0688" width="0.3048" layer="1"/> +<wire x1="77.826" y1="31.138" x2="77.826" y2="29.8508" width="0.3048" layer="1"/> +<wire x1="77.826" y1="29.8508" x2="77.4672" y2="29.492" width="0.3048" layer="1"/> +<wire x1="77.4672" y1="29.492" x2="71.9808" y2="29.492" width="0.3048" layer="1"/> +<wire x1="71.9808" y1="29.492" x2="65.532" y2="35.9408" width="0.3048" layer="1"/> +<contactref element="U7" pad="V10"/> +<wire x1="43.0808" y1="59.2088" x2="65.532" y2="35.9408" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_A20"> <contactref element="U$1" pad="3"/> -<wire x1="60.0206" y1="39.266" x2="60.0206" y2="37.547" width="0.3048" layer="1"/> -<wire x1="60.0206" y1="37.547" x2="59.484" y2="37.0104" width="0.3048" layer="1"/> -<wire x1="59.484" y1="37.0104" x2="53.388" y2="37.0104" width="0.3048" layer="1"/> -<wire x1="46.9392" y1="43.4592" x2="53.388" y2="37.0104" width="0.3048" layer="1"/> +<wire x1="78.3086" y1="31.138" x2="78.3086" y2="29.419" width="0.3048" layer="1"/> +<wire x1="78.3086" y1="29.419" x2="77.772" y2="28.8824" width="0.3048" layer="1"/> +<wire x1="77.772" y1="28.8824" x2="71.676" y2="28.8824" width="0.3048" layer="1"/> +<wire x1="65.2272" y1="35.3312" x2="71.676" y2="28.8824" width="0.3048" layer="1"/> +<contactref element="U7" pad="W10"/> +<wire x1="65.2272" y1="35.3312" x2="42.0808" y2="59.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_A21"> <contactref element="U$1" pad="4"/> -<wire x1="60.5286" y1="39.266" x2="60.5286" y2="37.1406" width="0.3048" layer="1"/> -<wire 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y1="35.7912" x2="52.7304" y2="35.7912" width="0.3048" layer="1"/> -<wire x1="52.7304" y1="35.7912" x2="45.8724" y2="42.6492" width="0.3048" layer="1"/> +<wire x1="82.3218" y1="31.138" x2="82.3218" y2="28.2506" width="0.3048" layer="1"/> +<wire x1="82.3218" y1="28.2506" x2="81.7344" y2="27.6632" width="0.3048" layer="1"/> +<wire x1="81.7344" y1="27.6632" x2="71.0184" y2="27.6632" width="0.3048" layer="1"/> +<wire x1="71.0184" y1="27.6632" x2="64.1604" y2="34.5212" width="0.3048" layer="1"/> +<contactref element="U7" pad="W5"/> +<wire x1="64.1604" y1="34.5212" x2="42.0808" y2="64.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_D31" class="2"> <contactref element="U$1" pad="12"/> -<wire x1="64.5418" y1="39.266" x2="64.5418" y2="35.9722" width="0.3048" layer="1"/> -<wire x1="64.5418" y1="35.9722" x2="63.7512" y2="35.1816" width="0.3048" layer="1"/> -<wire x1="63.7512" y1="35.1816" x2="52.4256" y2="35.1816" width="0.3048" layer="1"/> -<wire x1="52.4256" y1="35.1816" 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<signal name="FMC_A5" class="3"> <contactref element="U$1" pad="24"/> -<wire x1="70.5362" y1="39.266" x2="70.5362" y2="33.1274" width="0.3048" layer="1"/> -<wire x1="70.5362" y1="33.1274" x2="68.9328" y2="31.524" width="0.3048" layer="1"/> -<wire x1="68.9328" y1="31.524" x2="50.6448" y2="31.524" width="0.3048" layer="1"/> -<wire x1="50.6448" y1="31.524" x2="43.0248" y2="39.144" width="0.3048" layer="1"/> +<wire x1="88.8242" y1="31.138" x2="88.8242" y2="24.9994" width="0.3048" layer="1"/> +<wire x1="88.8242" y1="24.9994" x2="87.2208" y2="23.396" width="0.3048" layer="1"/> +<wire x1="87.2208" y1="23.396" x2="68.9328" y2="23.396" width="0.3048" layer="1"/> +<wire x1="68.9328" y1="23.396" x2="61.3128" y2="31.016" width="0.3048" layer="1"/> +<contactref element="U7" pad="AA13"/> +<wire x1="61.3128" y1="31.016" x2="40.0808" y2="56.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_A6" class="3"> <contactref element="U$1" pad="71"/> -<wire x1="86.3604" y1="50.0864" x2="84.1424" y2="50.0864" width="0.3048" layer="1"/> -<wire x1="84.1424" y1="50.0864" x2="81.1248" y2="47.0688" width="0.3048" layer="1"/> -<wire x1="81.1248" y1="47.0688" x2="76.248" y2="47.0688" width="0.3048" layer="1"/> -<via x="76.248" y="47.0688" extent="1-16" drill="0.6" shape="square"/> -<wire x1="75.6768" y1="46.7256" x2="76.248" y2="47.0688" width="0.3048" layer="16"/> +<wire x1="104.6484" y1="41.9584" x2="102.4304" y2="41.9584" width="0.3048" layer="1"/> +<wire x1="102.4304" y1="41.9584" x2="99.4128" y2="38.9408" width="0.3048" layer="1"/> +<wire x1="99.4128" y1="38.9408" x2="94.536" y2="38.9408" width="0.3048" layer="1"/> +<via x="94.536" y="38.9408" extent="1-16" drill="0.6" shape="square"/> +<wire x1="93.9648" y1="38.5976" x2="94.536" y2="38.9408" width="0.3048" layer="16"/> +<contactref element="U7" pad="AB13"/> +<wire x1="39.0808" y1="56.2088" x2="93.9648" y2="38.5976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_A7" class="3"> <contactref element="U$1" pad="74"/> -<wire x1="86.3604" y1="51.585" x2="84.7266" y2="51.585" width="0.3048" layer="1"/> -<wire x1="84.7266" y1="51.585" x2="81.4296" y2="48.288" width="0.3048" layer="1"/> -<wire x1="81.4296" y1="48.288" x2="74.4192" y2="48.288" width="0.3048" layer="1"/> -<via x="74.4192" y="48.288" extent="1-16" drill="0.6" shape="square"/> -<wire x1="73.3568" y1="47.2256" x2="74.4192" y2="48.288" width="0.3048" layer="16"/> +<wire x1="104.6484" y1="43.457" x2="103.0146" y2="43.457" width="0.3048" layer="1"/> +<wire x1="103.0146" y1="43.457" x2="99.7176" y2="40.16" width="0.3048" layer="1"/> +<wire x1="99.7176" y1="40.16" x2="92.7072" y2="40.16" width="0.3048" layer="1"/> +<via x="92.7072" y="40.16" extent="1-16" drill="0.6" shape="square"/> +<wire x1="91.6448" y1="39.0976" x2="92.7072" y2="40.16" width="0.3048" layer="16"/> +<contactref element="U7" pad="AA15"/> +<wire x1="40.0808" y1="54.2088" x2="91.6448" y2="39.0976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_A8" class="3"> <contactref element="U$1" pad="75"/> -<wire x1="72.028" y1="47.7256" x2="72.8952" y2="48.5928" width="0.3048" layer="16"/> -<wire x1="86.3604" y1="52.093" x2="84.3202" y2="52.093" width="0.3048" layer="1"/> -<wire x1="84.3202" y1="52.093" x2="81.7344" y2="49.5072" width="0.3048" layer="1"/> -<via x="72.8952" y="48.5928" extent="1-16" drill="0.6" shape="square"/> -<wire x1="81.7344" y1="49.5072" x2="73.8096" y2="49.5072" width="0.3048" layer="1"/> -<wire x1="73.8096" y1="49.5072" x2="72.8952" y2="48.5928" width="0.3048" layer="1"/> +<wire x1="90.316" y1="39.5976" x2="91.1832" y2="40.4648" width="0.3048" layer="16"/> +<wire x1="104.6484" y1="43.965" x2="102.6082" y2="43.965" width="0.3048" layer="1"/> +<wire x1="102.6082" y1="43.965" x2="100.0224" y2="41.3792" width="0.3048" layer="1"/> +<via x="91.1832" y="40.4648" extent="1-16" drill="0.6" shape="square"/> +<wire x1="100.0224" y1="41.3792" x2="92.0976" y2="41.3792" width="0.3048" layer="1"/> +<wire x1="92.0976" y1="41.3792" x2="91.1832" y2="40.4648" width="0.3048" layer="1"/> +<contactref element="U7" pad="AB15"/> +<wire x1="39.0808" y1="54.2088" x2="90.316" y2="39.5976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_A9" class="3"> <contactref element="U$1" pad="76"/> -<wire x1="86.3604" y1="52.601" x2="83.9138" y2="52.601" width="0.3048" layer="1"/> -<wire x1="83.9138" y1="52.601" x2="81.4296" y2="50.1168" width="0.3048" layer="1"/> -<via x="71.0664" y="49.812" extent="1-16" drill="0.6" shape="square"/> -<wire x1="70.3464" y1="48.2256" x2="71.0184" y2="48.8976" width="0.3048" layer="16"/> -<wire x1="71.0184" y1="48.8976" x2="71.0184" y2="50.0688" width="0.3048" layer="16"/> -<wire x1="71.0184" y1="50.0688" x2="71.0664" y2="49.812" width="0.3048" layer="16"/> -<wire x1="81.4296" y1="50.1168" x2="71.3712" y2="50.1168" width="0.3048" layer="1"/> -<wire x1="71.3712" y1="50.1168" x2="71.0664" y2="49.812" width="0.3048" layer="1"/> +<wire x1="104.6484" y1="44.473" x2="102.2018" y2="44.473" width="0.3048" layer="1"/> +<wire x1="102.2018" y1="44.473" x2="99.7176" y2="41.9888" width="0.3048" layer="1"/> +<via x="89.3544" y="41.684" extent="1-16" drill="0.6" shape="square"/> +<wire x1="88.6344" y1="40.0976" x2="89.3064" y2="40.7696" width="0.3048" layer="16"/> +<wire x1="89.3064" y1="40.7696" x2="89.3064" y2="41.9408" width="0.3048" layer="16"/> +<wire x1="89.3064" y1="41.9408" x2="89.3544" y2="41.684" width="0.3048" layer="16"/> +<wire x1="99.7176" y1="41.9888" x2="89.6592" y2="41.9888" width="0.3048" layer="1"/> +<wire x1="89.6592" y1="41.9888" x2="89.3544" y2="41.684" width="0.3048" layer="1"/> +<contactref element="U7" pad="Y13"/> +<wire x1="41.0808" y1="56.2088" x2="88.6344" y2="40.0976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_A10" class="3"> <contactref element="U$1" pad="77"/> -<wire x1="86.3604" y1="53.0836" x2="83.482" y2="53.0836" width="0.3048" layer="1"/> -<wire x1="83.482" y1="53.0836" x2="81.4296" y2="51.0312" width="0.3048" layer="1"/> -<via x="67.104" y="49.2024" extent="1-16" drill="0.6" shape="square"/> -<wire x1="67.104" y1="49.2024" x2="66.7992" y2="49.5072" width="0.3048" layer="16"/> -<wire x1="66.8224" y1="49.2256" x2="67.104" y2="49.2024" width="0.3048" layer="16"/> -<wire x1="81.4296" y1="51.0312" x2="70.104" y2="51.0312" width="0.3048" layer="1"/> -<wire x1="70.104" y1="51.0312" x2="68.2752" y2="49.2024" width="0.3048" layer="1"/> -<wire x1="68.2752" y1="49.2024" x2="67.104" y2="49.2024" width="0.3048" layer="1"/> +<wire x1="104.6484" y1="44.9556" x2="101.77" y2="44.9556" width="0.3048" layer="1"/> +<wire x1="101.77" y1="44.9556" x2="99.7176" y2="42.9032" width="0.3048" layer="1"/> +<via x="85.392" y="41.0744" extent="1-16" drill="0.6" shape="square"/> +<wire x1="85.392" y1="41.0744" x2="85.0872" y2="41.3792" width="0.3048" layer="16"/> +<wire x1="85.1104" y1="41.0976" x2="85.392" y2="41.0744" width="0.3048" layer="16"/> +<wire x1="99.7176" y1="42.9032" x2="88.392" y2="42.9032" width="0.3048" layer="1"/> +<wire x1="88.392" y1="42.9032" x2="86.5632" y2="41.0744" width="0.3048" layer="1"/> +<wire x1="86.5632" y1="41.0744" x2="85.392" y2="41.0744" width="0.3048" layer="1"/> +<contactref element="U7" pad="AA14"/> +<wire x1="40.0808" y1="55.2088" x2="85.0872" y2="41.3792" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_A11" class="3"> <contactref element="U$1" pad="78"/> -<wire x1="86.3604" y1="53.5916" x2="83.0756" y2="53.5916" width="0.3048" layer="1"/> -<wire x1="83.0756" y1="53.5916" x2="81.1248" y2="51.6408" width="0.3048" layer="1"/> -<via x="65.2752" y="50.4216" extent="1-16" drill="0.6" shape="square"/> -<wire x1="65.2752" y1="50.4216" x2="64.056" y2="50.4216" width="0.3048" layer="16"/> -<wire x1="63.36" y1="49.7256" x2="64.056" y2="50.4216" width="0.3048" layer="16"/> -<wire x1="81.1248" y1="51.6408" x2="69.7992" y2="51.6408" width="0.3048" layer="1"/> -<wire x1="69.7992" y1="51.6408" x2="68.58" y2="50.4216" width="0.3048" layer="1"/> -<wire x1="68.58" y1="50.4216" x2="65.2752" y2="50.4216" width="0.3048" layer="1"/> +<wire x1="104.6484" y1="45.4636" x2="101.3636" y2="45.4636" width="0.3048" layer="1"/> +<wire x1="101.3636" y1="45.4636" x2="99.4128" y2="43.5128" width="0.3048" layer="1"/> +<via x="83.5632" y="42.2936" extent="1-16" drill="0.6" shape="square"/> +<wire x1="83.5632" y1="42.2936" x2="82.344" y2="42.2936" width="0.3048" layer="16"/> +<wire x1="81.648" y1="41.5976" x2="82.344" y2="42.2936" width="0.3048" layer="16"/> +<wire x1="99.4128" y1="43.5128" x2="88.0872" y2="43.5128" width="0.3048" layer="1"/> +<wire x1="88.0872" y1="43.5128" x2="86.868" y2="42.2936" width="0.3048" layer="1"/> +<wire x1="86.868" y1="42.2936" x2="83.5632" y2="42.2936" width="0.3048" layer="1"/> +<contactref element="U7" pad="W14"/> +<wire x1="42.0808" y1="55.2088" x2="81.648" y2="41.5976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_D4" class="2"> <contactref element="U$1" pad="79"/> -<wire x1="78.0768" y1="53.1648" x2="78.3816" y2="52.86" width="0.3048" layer="16"/> -<via x="78.3816" y="52.86" extent="1-16" drill="0.6" shape="square"/> -<wire x1="86.3604" y1="54.0996" x2="79.6212" y2="54.0996" width="0.3048" layer="1"/> -<wire x1="79.6212" y1="54.0996" x2="78.3816" y2="52.86" width="0.3048" layer="1"/> -<wire x1="61.9216" y1="50.7256" x2="63.4464" y2="52.2504" width="0.3048" layer="16"/> -<wire x1="63.4464" y1="52.2504" x2="77.724" y2="52.2504" width="0.3048" layer="16"/> -<wire x1="77.724" y1="52.2504" x2="78.3336" y2="52.86" width="0.3048" layer="16"/> -<wire x1="78.3336" y1="52.86" x2="78.3816" y2="52.86" width="0.3048" layer="16"/> +<wire x1="96.3648" y1="45.0368" x2="96.6696" y2="44.732" width="0.3048" layer="16"/> +<via x="96.6696" y="44.732" extent="1-16" drill="0.6" shape="square"/> +<wire x1="104.6484" y1="45.9716" x2="97.9092" y2="45.9716" width="0.3048" layer="1"/> +<wire x1="97.9092" y1="45.9716" x2="96.6696" y2="44.732" width="0.3048" layer="1"/> +<wire x1="80.2096" y1="42.5976" x2="81.7344" y2="44.1224" width="0.3048" layer="16"/> +<wire x1="81.7344" y1="44.1224" x2="96.012" y2="44.1224" width="0.3048" layer="16"/> +<wire x1="96.012" y1="44.1224" x2="96.6216" y2="44.732" width="0.3048" layer="16"/> +<wire x1="96.6216" y1="44.732" x2="96.6696" y2="44.732" width="0.3048" layer="16"/> +<contactref element="U7" pad="V2"/> +<wire x1="43.0808" y1="67.2088" x2="80.2096" y2="42.5976" width="0" layer="19" extent="1-16"/> </signal> <signal name="FMC_D20" class="2"> <contactref element="U$1" pad="102"/> -<wire x1="86.3604" y1="65.6058" x2="77.2182" y2="65.6058" width="0.3048" layer="1"/> -<via x="74.724" y="64.4424" extent="1-16" drill="0.6" shape="square"/> -<wire x1="77.2182" y1="65.6058" x2="76.0548" y2="64.4424" width="0.3048" layer="1"/> -<wire x1="76.0548" y1="64.4424" x2="74.724" y2="64.4424" width="0.3048" layer="1"/> -<wire x1="72.0448" y1="62.7256" x2="73.7616" y2="64.4424" width="0.3048" layer="16"/> -<wire x1="73.7616" y1="64.4424" x2="74.724" y2="64.4424" width="0.3048" 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y2="17.9324" width="0.4064" layer="1"/> +<wire x1="55.5244" y1="11.4808" x2="55.4736" y2="11.5316" width="0.4064" layer="1"/> +<wire x1="55.4736" y1="11.5316" x2="55.4736" y2="11.9888" width="0.4064" layer="1"/> +<wire x1="55.4736" y1="11.9888" x2="51.5112" y2="15.9512" width="0.4064" layer="1"/> <contactref element="JP4" pad="2"/> -<wire x1="33.2232" y1="24.0792" x2="31.242" y2="26.0604" width="0.4064" layer="1"/> -<wire x1="44.3738" y1="21.4376" x2="38.9636" y2="21.4376" width="0.4064" layer="1"/> -<wire x1="38.9636" y1="21.4376" x2="37.1856" y2="19.6596" width="0.4064" layer="1"/> -<wire x1="36.068" y1="25.146" x2="34.29" y2="25.146" width="0.4064" layer="1"/> -<wire x1="19.3548" y1="26.0604" x2="18.8976" y2="25.6032" width="0.4064" layer="1"/> -<wire x1="18.8976" y1="25.6032" x2="18.8976" y2="24.892" width="0.4064" layer="1"/> -<wire x1="18.8976" y1="24.892" x2="18.8722" y2="24.8666" width="0.4064" layer="1"/> -<wire x1="34.29" y1="25.146" x2="33.2232" y2="24.0792" width="0.4064" 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element="U7" pad="T6"/> -</signal> -<signal name="FPGA_FMC_NWAIT"> -<contactref element="U7" pad="Y6"/> -</signal> -<signal name="FPGA_FMC_NWE"> -<contactref element="U7" pad="AA6"/> -</signal> <signal name="FPGA_PROM_SCLK"> <contactref element="IC3" pad="6"/> <contactref element="U7" pad="L12"/> -<wire x1="15.4352" y1="-5.2912" x2="48.1838" y2="-2.1082" width="0" layer="19" extent="1-1"/> +<wire x1="50.0808" y1="57.2088" x2="109.7534" y2="96.901" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_MOSI"> <contactref element="IC3" pad="5"/> <contactref element="U7" pad="P22"/> -<wire x1="25.4352" y1="-8.2912" x2="49.4538" y2="-2.1082" width="0" layer="19" extent="1-1"/> +<wire x1="47.0808" y1="47.2088" x2="109.7534" y2="95.631" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_CS_N"> <contactref element="IC3" pad="1"/> <contactref element="R9" pad="1"/> -<wire x1="61.0244" y1="-90.5256" x2="45.6438" y2="-8.255" width="0" layer="19" extent="1-1"/> +<wire x1="103.6066" y1="99.441" x2="111.926" y2="99.568" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_MISO"> <contactref element="IC3" pad="2"/> <contactref element="U7" pad="R22"/> -<wire x1="25.4352" y1="-9.2912" x2="46.9138" y2="-8.255" width="0" layer="19" extent="1-1"/> +<wire x1="46.0808" y1="47.2088" x2="103.6066" y2="98.171" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_W_N"> <contactref element="IC3" pad="3"/> <contactref element="R20" pad="2"/> <contactref element="JP7" pad="1"/> -<wire x1="41.7576" y1="-46.0756" x2="48.1838" y2="-8.255" width="0" layer="19" extent="1-1"/> -<wire x1="68.2108" y1="-90.5256" x2="41.7576" y2="-46.0756" width="0" layer="19" extent="1-1"/> +<wire x1="103.6066" y1="96.901" x2="113.626" y2="97.536" width="0" layer="19" extent="1-1"/> +<wire x1="100.584" y1="96.266" x2="103.6066" y2="96.901" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_TAMPER_0"> <contactref element="U7" pad="F15"/> @@ -9800,87 +9724,87 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <signal name="FPGA_GPIO_A_0"> <contactref element="U7" pad="C15"/> <contactref element="SV1" pad="7"/> -<wire x1="18.4352" y1="2.7088" x2="77.978" y2="1.4732" width="0" layer="19" extent="1-1"/> +<wire x1="31.242" y1="75.946" x2="58.0808" y2="54.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_1"> <contactref element="U7" pad="E13"/> <contactref element="SV1" pad="8"/> -<wire x1="16.4352" y1="0.7088" x2="77.978" y2="4.0132" width="0" layer="19" extent="1-1"/> +<wire x1="31.242" y1="78.486" x2="56.0808" y2="56.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_2"> <contactref element="U7" pad="E14"/> <contactref element="SV1" pad="9"/> -<wire x1="17.4352" y1="0.7088" x2="80.518" y2="1.4732" width="0" layer="19" extent="1-1"/> +<wire x1="33.782" y1="75.946" x2="56.0808" y2="55.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_3"> <contactref element="U7" pad="E16"/> <contactref element="SV1" pad="10"/> -<wire x1="19.4352" y1="0.7088" x2="80.518" y2="4.0132" width="0" layer="19" extent="1-1"/> +<wire x1="33.782" y1="78.486" x2="56.0808" y2="53.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_4"> <contactref element="U7" pad="D16"/> <contactref element="SV1" pad="13"/> -<wire x1="19.4352" y1="1.7088" x2="85.598" y2="1.4732" width="0" layer="19" extent="1-1"/> +<wire x1="57.0808" y1="53.2088" x2="38.862" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_5"> <contactref element="U7" pad="D14"/> <contactref element="SV1" pad="14"/> -<wire x1="17.4352" y1="1.7088" x2="85.598" y2="4.0132" width="0" layer="19" extent="1-1"/> +<wire x1="57.0808" y1="55.2088" x2="38.862" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_6"> <contactref element="U7" pad="D15"/> <contactref element="SV1" pad="15"/> -<wire x1="18.4352" y1="1.7088" x2="88.138" y2="1.4732" width="0" layer="19" extent="1-1"/> +<wire x1="57.0808" y1="54.2088" x2="41.402" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_7"> <contactref element="U7" pad="B15"/> <contactref element="SV1" pad="16"/> -<wire x1="18.4352" y1="3.7088" x2="88.138" y2="4.0132" width="0" layer="19" extent="1-1"/> +<wire x1="59.0808" y1="54.2088" x2="41.402" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_0"> <contactref element="U7" pad="B16"/> <contactref element="SV2" pad="7"/> -<wire x1="11.2268" y1="-23.8252" x2="19.4352" y2="3.7088" width="0" layer="19" extent="1-1"/> +<wire x1="59.0808" y1="53.2088" x2="65.786" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_1"> <contactref element="U7" pad="C13"/> <contactref element="SV2" pad="8"/> -<wire x1="11.2268" y1="-21.2852" x2="16.4352" y2="2.7088" width="0" layer="19" extent="1-1"/> +<wire x1="58.0808" y1="56.2088" x2="65.786" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_2"> <contactref element="U7" pad="B13"/> <contactref element="SV2" pad="9"/> -<wire x1="13.7668" y1="-23.8252" x2="16.4352" y2="3.7088" width="0" layer="19" extent="1-1"/> +<wire x1="59.0808" y1="56.2088" x2="68.326" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_3"> <contactref element="U7" pad="A15"/> <contactref element="SV2" pad="10"/> -<wire x1="13.7668" y1="-21.2852" x2="18.4352" y2="4.7088" width="0" layer="19" extent="1-1"/> +<wire x1="60.0808" y1="54.2088" x2="68.326" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_4"> <contactref element="U7" pad="A16"/> <contactref element="SV2" pad="13"/> -<wire x1="18.8468" y1="-23.8252" x2="19.4352" y2="4.7088" width="0" layer="19" extent="1-1"/> +<wire x1="60.0808" y1="53.2088" x2="73.406" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_5"> <contactref element="U7" pad="A13"/> <contactref element="SV2" pad="14"/> -<wire x1="18.8468" y1="-21.2852" x2="16.4352" y2="4.7088" width="0" layer="19" extent="1-1"/> +<wire x1="60.0808" y1="56.2088" x2="73.406" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_6"> <contactref element="U7" pad="A14"/> <contactref element="SV2" pad="15"/> -<wire x1="21.3868" y1="-23.8252" x2="17.4352" y2="4.7088" width="0" layer="19" extent="1-1"/> +<wire x1="60.0808" y1="55.2088" x2="75.946" y2="75.946" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_B_7"> <contactref element="U7" pad="B17"/> <contactref element="SV2" pad="16"/> -<wire x1="21.3868" y1="-21.2852" x2="20.4352" y2="3.7088" width="0" layer="19" extent="1-1"/> +<wire x1="59.0808" y1="52.2088" x2="75.946" y2="78.486" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GCLK"> <contactref element="U7" pad="D17"/> <contactref element="Q5" pad="3"/> -<wire x1="43.0076" y1="-21.1004" x2="20.4352" y2="1.7088" width="0" layer="19" extent="1-1"/> +<wire x1="57.0808" y1="52.2088" x2="90.658" y2="98.686" width="0" layer="19" extent="1-1"/> </signal> <signal name="DIGITIZED_NOISE"> <contactref element="U7" pad="W19"/> @@ -9888,65 +9812,65 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <signal name="FPGA_GPIO_LED_2"> <contactref element="U7" pad="W22"/> <contactref element="R31" pad="2"/> -<wire x1="25.4352" y1="-13.2912" x2="73.6972" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="18.122" y1="47.752" x2="42.0808" y2="47.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_LED_3"> <contactref element="U7" pad="AA20"/> <contactref element="R32" pad="2"/> -<wire x1="23.4352" y1="-15.2912" x2="78.574" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="18.122" y1="49.784" x2="40.0808" y2="49.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_M2"> 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width="0" layer="19" extent="1-1"/> +<wire x1="22.352" y1="62.738" x2="24.55" y2="62.992" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROGRAM_B"> <contactref element="U7" pad="N12"/> <contactref element="R25" pad="1"/> -<wire x1="88.4564" y1="-90.5256" x2="15.4352" y2="-7.2912" width="0" layer="19" extent="1-1"/> +<wire x1="11.342" y1="18.288" x2="48.0808" y2="57.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_DONE_INT"> <contactref element="U7" pad="G11"/> <contactref element="LED15" pad="C"/> <contactref element="R34" pad="2"/> -<wire x1="88.3276" y1="-95.4024" x2="87.4776" y2="-39.7884" width="0" layer="19" extent="1-1"/> -<wire x1="14.4352" y1="-1.2912" x2="87.4776" y2="-39.7884" width="0" layer="19" extent="1-1"/> +<wire x1="7.378" y1="37.592" x2="54.0808" y2="58.2088" width="0" layer="19" extent="1-1"/> +<wire x1="5.93" y1="37.592" x2="7.378" y2="37.592" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_M0"> <contactref element="U7" pad="U11"/> <contactref element="R24" pad="1"/> -<wire x1="14.4352" y1="-11.2912" x2="82.97" y2="-90.5256" width="0" layer="19" extent="1-1"/> +<wire x1="4.23" y1="42.672" x2="44.0808" y2="58.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_M1"> <contactref element="U7" pad="U10"/> <contactref element="R23" pad="2"/> -<wire x1="13.4352" y1="-11.2912" x2="79.1836" y2="-90.5256" width="0" layer="19" extent="1-1"/> +<wire x1="5.93" y1="44.704" x2="44.0808" y2="59.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="VPGA_VCCO_3V3"> <contactref element="R24" pad="2"/> @@ -9957,12 +9881,12 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <signal name="FPGA_GPIO_LED_0"> <contactref element="U7" pad="T20"/> <contactref element="R22" pad="2"/> -<wire x1="23.4352" y1="-10.2912" x2="59.0668" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="18.122" y1="43.688" x2="45.0808" y2="49.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_LED_1"> <contactref element="U7" pad="W21"/> <contactref element="R30" pad="2"/> -<wire x1="24.4352" y1="-13.2912" x2="68.8204" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="18.122" y1="45.72" x2="42.0808" y2="48.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_MKM_CS_N"> <contactref element="U7" pad="T21"/> @@ -9979,49 +9903,49 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <signal name="N$27"> <contactref element="LED11" pad="A"/> <contactref element="R22" pad="1"/> -<wire x1="74.0664" y1="-41.2884" x2="57.3668" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="14.974" y1="45.72" x2="16.422" y2="43.688" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$28"> <contactref element="LED12" pad="A"/> <contactref element="R30" pad="1"/> -<wire x1="67.1204" y1="-95.4024" x2="77.4192" y2="-41.2884" width="0" layer="19" extent="1-1"/> +<wire x1="14.974" y1="46.736" x2="16.422" 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y2="18.288" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$34"> <contactref element="R33" pad="1"/> <contactref element="LED15" pad="A"/> -<wire x1="81.7508" y1="-95.4024" x2="87.4776" y2="-41.2884" width="0" layer="19" extent="1-1"/> +<wire x1="8.878" y1="37.592" x2="10.326" y2="37.592" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_DONE"> <contactref element="R34" pad="1"/> @@ -10029,7 +9953,7 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <signal name="N$35"> <contactref element="U$5" pad="P$30"/> <contactref element="C115" pad="1"/> -<wire x1="27.8224" y1="-20.0456" x2="11.6468" y2="-66.1416" width="0" layer="19" extent="1-1"/> +<wire x1="138.342" y1="61.976" x2="146.6944" y2="61.2344" width="0" layer="19" extent="1-1"/> </signal> <signal name="VCC_5V0"> <contactref element="C87" pad="1"/> @@ -10071,63 +9995,63 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <contactref element="C111" pad="+"/> <contactref element="C112" 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x1="154.6996" y1="95.1992" x2="154.598" y2="97.536" width="0" layer="19" extent="1-1"/> +<wire x1="151.55" y1="97.536" x2="154.598" y2="97.536" width="0" layer="19" extent="1-1"/> +<wire x1="148.17" y1="99.568" x2="151.55" y2="97.536" width="0" layer="19" extent="1-1"/> +<wire x1="147.704" y1="96.52" x2="148.17" y2="99.568" width="0" layer="19" extent="1-1"/> +<wire x1="142.624" y1="96.52" x2="147.704" y2="96.52" width="0" layer="19" extent="1-1"/> +<wire x1="139.802" y1="99.568" x2="142.624" y2="96.52" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="91.3144" x2="142.624" y2="96.52" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="90.8144" x2="140.0928" y2="91.3144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="90.3144" x2="140.0928" y2="90.8144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="89.8144" x2="140.0928" y2="90.3144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="89.3144" x2="140.0928" y2="89.8144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="88.8144" x2="140.0928" y2="89.3144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="88.3144" x2="140.0928" y2="88.8144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="87.8144" x2="140.0928" y2="88.3144" width="0" layer="19" extent="1-1"/> +<wire x1="140.0928" y1="87.3144" x2="140.0928" y2="87.8144" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$49"> <contactref element="U$7" pad="P$56"/> <contactref element="R51" pad="1"/> <contactref element="R52" pad="2"/> <contactref element="C99" pad="2"/> -<wire x1="88.3276" y1="-85.6488" x2="59.7168" y2="3.2904" width="0" layer="19" extent="1-1"/> -<wire x1="39.5596" y1="-90.5256" x2="88.3276" y2="-85.6488" width="0" layer="19" extent="1-1"/> -<wire x1="32.0684" y1="-90.5256" x2="39.5596" y2="-90.5256" width="0" layer="19" extent="1-1"/> +<wire x1="154.598" y1="99.568" x2="156.298" y2="97.536" width="0" layer="19" extent="1-1"/> +<wire x1="146.47" y1="99.568" x2="154.598" y2="99.568" width="0" layer="19" extent="1-1"/> +<wire x1="147.0928" y1="93.7144" x2="146.47" y2="99.568" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$50"> <contactref element="Q3" pad="3"/> <contactref element="LED16" pad="C"/> -<wire x1="90.8304" y1="-39.7884" x2="90.2208" y2="-20.5408" width="0" layer="19" extent="1-1"/> +<wire x1="152.6208" y1="69.9008" x2="158.3316" y2="71.7296" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$51"> <contactref element="R61" pad="1"/> <contactref element="LED16" pad="A"/> -<wire x1="90.8304" y1="-41.2884" x2="41.5172" y2="-100.2792" width="0" layer="19" extent="1-1"/> +<wire x1="156.63" y1="70.104" x2="156.8316" y2="71.7296" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$52"> <contactref element="C103" pad="1"/> <contactref element="U$8" pad="P$9"/> -<wire x1="82.3604" y1="-71.0184" x2="37.2872" y2="-15.8496" width="0" layer="19" extent="1-1"/> +<wire x1="147.0152" y1="18.6944" x2="154.4964" y2="22.4536" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$53"> <contactref element="U$8" pad="P$3"/> <contactref element="R68" pad="2"/> -<wire x1="30.9372" y1="-15.8496" x2="62.7244" y2="-100.2792" width="0" layer="19" extent="1-1"/> +<wire x1="139.026" y1="13.208" x2="140.6652" y2="18.6944" width="0" layer="19" extent="1-1"/> </signal> <signal name="PWR_18V"> <contactref element="U$8" pad="P$2"/> @@ -10340,31 +10264,43 @@ http://www.semiconductors.philips.com/pip/2N7002T.html<br> <contactref element="C86" pad="1"/> <contactref element="C140" pad="1"/> <contactref element="C141" pad="1"/> -<wire x1="11.6468" y1="-56.388" x2="52.9708" y2="-100.2792" width="0" layer="19" extent="1-1"/> -<wire x1="46.1488" y1="-31.0896" x2="11.6468" y2="-56.388" width="0" layer="19" extent="1-1"/> -<wire x1="53.1592" y1="-31.0896" x2="46.1488" y2="-31.0896" width="0" layer="19" extent="1-1"/> -<wire x1="60.1696" y1="-31.0896" x2="53.1592" y2="-31.0896" width="0" layer="19" extent="1-1"/> -<wire x1="29.6672" y1="-15.8496" x2="46.1488" y2="-31.0896" width="0" layer="19" extent="1-1"/> -<wire x1="28.3972" y1="-15.8496" x2="29.6672" y2="-15.8496" width="0" layer="19" extent="1-1"/> +<wire x1="141.856" y1="13.208" x2="149.186" y2="13.208" width="0" layer="19" extent="1-1"/> +<wire x1="141.856" y1="10.16" x2="141.856" y2="13.208" width="0" layer="19" extent="1-1"/> +<wire x1="141.856" y1="7.112" x2="141.856" y2="10.16" width="0" layer="19" extent="1-1"/> +<wire x1="137.326" y1="7.112" x2="141.856" y2="7.112" width="0" layer="19" extent="1-1"/> +<wire x1="139.3952" y1="18.6944" x2="141.856" y2="13.208" width="0" layer="19" extent="1-1"/> +<wire x1="138.1252" y1="18.6944" x2="139.3952" y2="18.6944" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$54"> <contactref element="R62" pad="1"/> <contactref element="R64" pad="1"/> <contactref element="R63" pad="2"/> -<wire x1="51.2708" y1="-100.2792" x2="46.394" y2="-100.2792" width="0" layer="19" extent="1-1"/> -<wire x1="75.526" y1="-85.6488" x2="51.2708" y2="-100.2792" width="0" layer="19" extent="1-1"/> +<wire x1="149.186" y1="11.176" x2="147.486" y2="13.208" width="0" layer="19" extent="1-1"/> +<wire x1="147.486" y1="9.144" x2="149.186" y2="11.176" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$55"> <contactref element="R62" pad="2"/> <contactref element="U$8" pad="P$4"/> -<wire x1="32.2072" y1="-15.8496" x2="48.094" y2="-100.2792" width="0" layer="19" extent="1-1"/> +<wire x1="149.186" y1="9.144" x2="141.9352" y2="18.6944" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$56"> <contactref element="U$8" pad="P$7"/> <contactref element="R65" pad="1"/> <contactref element="R66" pad="2"/> -<wire x1="81.9268" y1="-85.6488" x2="51.8804" y2="-95.4024" width="0" layer="19" extent="1-1"/> -<wire x1="36.0172" y1="-15.8496" x2="51.8804" y2="-95.4024" width="0" layer="19" extent="1-1"/> +<wire x1="137.326" y1="11.176" x2="145.7452" y2="18.6944" width="0" layer="19" extent="1-1"/> +<wire x1="139.026" y1="9.144" x2="137.326" y2="11.176" width="0" layer="19" extent="1-1"/> +</signal> +<signal name="FMC_A22"> +<contactref element="U7" pad="Y12"/> +</signal> +<signal name="FMC_A23"> +<contactref element="U7" pad="W12"/> +</signal> +<signal name="FMC_A24"> +<contactref element="U7" pad="V13"/> +</signal> +<signal name="FMC_A25"> +<contactref element="U7" pad="V14"/> </signal> </signals> <errors> diff --git a/eagle/alpha/rev02/rev02.sch b/eagle/alpha/rev02/rev02.sch index 488ca58..5ffbedd 100644 --- a/eagle/alpha/rev02/rev02.sch +++ b/eagle/alpha/rev02/rev02.sch @@ -6,7 +6,7 @@ <setting alwaysvectorfont="no"/> <setting verticaltext="up"/> </settings> -<grid distance="20" unitdist="mil" unit="mil" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> <layers> <layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> <layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> @@ -36901,10 +36901,7 @@ SD Series, Vertical mount</description> <sheet> <description>CrypTech avalanche noise evaluation board, rev 02</description> <plain> -<text x="60.96" y="109.22" size="3.81" layer="91">ARM side of FMC bus</text> <text x="320.04" y="142.24" size="3.81" layer="91">Extra</text> -<text x="58.928" y="59.944" size="1.778" layer="91"><-- FMC_D[...] signals can be swapped</text> -<text x="232.664" y="60.452" size="1.778" layer="91"><-- FMC_A[...] signals can be swapped</text> </plain> <instances> <instance part="FRAME1" gate="G$1" x="22.86" y="-106.68"/> @@ -36926,28 +36923,6 @@ SD Series, Vertical mount</description> <instance part="FID15" gate="G$1" x="396.24" y="127"/> </instances> <busses> -<bus name="FMC_D[0..31],FMC_A[0..19],FMC_NE1,FMC_NOE,FMC_NWE,FMC_NL,FMC_NWAIT"> -<segment> -<wire x1="60.96" y1="99.06" x2="375.92" y2="99.06" width="0.762" layer="92"/> -<label x="55.88" y="101.6" size="1.778" layer="95"/> -</segment> -</bus> -<bus name="FMC_A[20..21],DIGITIZED"> -<segment> -<wire x1="383.54" y1="99.06" x2="388.62" y2="99.06" width="0.762" layer="92"/> -<label x="368.3" y="106.68" size="1.778" layer="95"/> -</segment> -</bus> -<bus name="FPGA_FMC_D[0..31]"> -<segment> -<wire x1="56.388" y1="65.024" x2="218.948" y2="65.024" width="0.762" layer="92"/> -</segment> -</bus> -<bus name="FPGA_FMC_A[0..25]"> -<segment> -<wire x1="230.124" y1="65.532" x2="245.364" y2="65.532" width="0.762" layer="92"/> -</segment> -</bus> </busses> <nets> </nets> @@ -40568,7 +40543,8 @@ one of the two positive (master) sides of the two available MRCC differential pairs)</text> <text x="-53.34" y="45.72" size="1.778" layer="91"><-- FMC_D[...] signals can be swapped</text> -<text x="-38.1" y="-35.56" size="1.778" layer="91"><-- FMC_* control signals can be swapped</text> +<text x="-50.8" y="-40.64" size="1.778" layer="91"><-- FMC_* control signals + can be swapped</text> </plain> <instances> <instance part="U7" gate="B13" x="43.18" y="2.54"/> @@ -40576,20 +40552,26 @@ MRCC differential pairs)</text> <instance part="FRAME12" gate="G$1" x="-124.46" y="-93.98"/> </instances> <busses> -<bus name="FPGA_FMC_A[0..25]"> +<bus name="FMC_A[0..25]"> <segment> <wire x1="78.74" y1="43.18" x2="93.98" y2="43.18" width="0.762" layer="92"/> <wire x1="78.74" y1="43.18" x2="78.74" y2="-27.94" width="0.762" layer="92"/> <label x="78.74" y="43.18" size="1.778" layer="95"/> </segment> </bus> -<bus name="FPGA_FMC_D[0..31]"> +<bus name="FMC_D[0..31]"> <segment> <wire x1="-55.88" y1="-33.02" x2="-55.88" y2="50.8" width="0.762" layer="92"/> <wire x1="-55.88" y1="50.8" x2="-40.64" y2="50.8" width="0.762" layer="92"/> <label x="-55.88" y="50.8" size="1.778" layer="95"/> </segment> </bus> +<bus name="FMC_NE1,FMC_NOE,FMC_NWE,FMC_NL,FMC_NWAIT"> +<segment> +<wire x1="-53.34" y1="-33.02" x2="-53.34" y2="-48.26" width="0.762" layer="92"/> +<label x="-78.74" y="-53.34" size="1.778" layer="95"/> +</segment> +</bus> </busses> <nets> <net name="FPGA_VCCO_3V3" class="0"> @@ -40642,452 +40624,444 @@ MRCC differential pairs)</text> <junction x="53.34" y="43.18"/> </segment> </net> -<net name="FPGA_FMC_A0" class="0"> +<net name="FPGA_FMC_CLK" class="0"> <segment> -<pinref part="U7" gate="B13" pin="IO_0_13"/> -<wire x1="48.26" y1="38.1" x2="78.74" y2="38.1" width="0.1524" layer="91"/> -<label x="53.34" y="38.1" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L12P_T1_MRCC_13"/> +<wire x1="48.26" y1="-20.32" x2="53.34" y2="-20.32" width="0.1524" layer="91"/> +<label x="53.34" y="-20.32" size="1.778" layer="95" xref="yes"/> </segment> </net> -<net name="FPGA_FMC_A1" class="0"> +<net name="FMC_D0" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L1P_T0_13"/> -<wire x1="48.26" y1="35.56" x2="78.74" y2="35.56" width="0.1524" layer="91"/> -<label x="53.34" y="35.56" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_0_34"/> +<wire x1="-55.88" y1="45.72" x2="-86.36" y2="45.72" width="0.1524" layer="91"/> +<label x="-73.66" y="45.72" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A2" class="0"> +<net name="FMC_D1" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L1N_T0_13"/> -<wire x1="48.26" y1="33.02" x2="78.74" y2="33.02" width="0.1524" layer="91"/> -<label x="53.34" y="33.02" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L1P_T0_34"/> +<wire x1="-55.88" y1="43.18" x2="-86.36" y2="43.18" width="0.1524" layer="91"/> +<label x="-73.66" y="43.18" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A3" class="0"> +<net name="FMC_D2" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L2P_T0_13"/> -<wire x1="48.26" y1="30.48" x2="78.74" y2="30.48" width="0.1524" layer="91"/> -<label x="53.34" y="30.48" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L1N_T0_34"/> +<wire x1="-55.88" y1="40.64" x2="-86.36" y2="40.64" width="0.1524" layer="91"/> +<label x="-73.66" y="40.64" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A4" class="0"> +<net name="FMC_D3" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L2N_T0_13"/> -<wire x1="48.26" y1="27.94" x2="78.74" y2="27.94" width="0.1524" layer="91"/> -<label x="53.34" y="27.94" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L2P_T0_34"/> +<wire x1="-55.88" y1="38.1" x2="-86.36" y2="38.1" width="0.1524" layer="91"/> +<label x="-73.66" y="38.1" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A5" class="0"> +<net name="FMC_D4" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L3P_T0_DQS_13"/> -<wire x1="48.26" y1="25.4" x2="78.74" y2="25.4" width="0.1524" layer="91"/> -<label x="53.34" y="25.4" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L2N_T0_34"/> +<wire x1="-55.88" y1="35.56" x2="-86.36" y2="35.56" width="0.1524" layer="91"/> +<label x="-73.66" y="35.56" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A6" class="0"> +<net name="FMC_D5" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L3N_T0_DQS_13"/> -<wire x1="48.26" y1="22.86" x2="78.74" y2="22.86" width="0.1524" layer="91"/> -<label x="53.34" y="22.86" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L3P_T0_DQS_34"/> +<wire x1="-55.88" y1="33.02" x2="-86.36" y2="33.02" width="0.1524" layer="91"/> +<label x="-73.66" y="33.02" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A7" class="0"> +<net name="FMC_D6" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L4P_T0_13"/> -<wire x1="48.26" y1="20.32" x2="78.74" y2="20.32" width="0.1524" layer="91"/> -<label x="53.34" y="20.32" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L3N_T0_DQS_34"/> +<wire x1="-55.88" y1="30.48" x2="-86.36" y2="30.48" width="0.1524" layer="91"/> +<label x="-73.66" y="30.48" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A8" class="0"> +<net name="FMC_D7" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L4N_T0_13"/> -<wire x1="48.26" y1="17.78" x2="78.74" y2="17.78" width="0.1524" layer="91"/> -<label x="53.34" y="17.78" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L4P_T0_34"/> +<wire x1="-55.88" y1="27.94" x2="-86.36" y2="27.94" width="0.1524" layer="91"/> +<label x="-73.66" y="27.94" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A9" class="0"> +<net name="FMC_D8" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L5P_T0_13"/> -<wire x1="48.26" y1="15.24" x2="78.74" y2="15.24" width="0.1524" layer="91"/> -<label x="53.34" y="15.24" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L4N_T0_34"/> +<wire x1="-55.88" y1="25.4" x2="-86.36" y2="25.4" width="0.1524" layer="91"/> +<label x="-73.66" y="25.4" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A10" class="0"> +<net name="FMC_D9" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L5N_T0_13"/> -<wire x1="48.26" y1="12.7" x2="78.74" y2="12.7" width="0.1524" layer="91"/> -<label x="53.34" y="12.7" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L5P_T0_34"/> +<wire x1="-55.88" y1="22.86" x2="-86.36" y2="22.86" width="0.1524" layer="91"/> +<label x="-73.66" y="22.86" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A11" class="0"> +<net name="FMC_D10" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L6P_T0_13"/> -<wire x1="48.26" y1="10.16" x2="78.74" y2="10.16" width="0.1524" layer="91"/> -<label x="53.34" y="10.16" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L5N_T0_34"/> +<wire x1="-55.88" y1="20.32" x2="-86.36" y2="20.32" width="0.1524" layer="91"/> +<label x="-73.66" y="20.32" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A12" class="0"> +<net name="FMC_D11" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L6N_T0_VREF_13"/> -<wire x1="48.26" y1="7.62" x2="78.74" y2="7.62" width="0.1524" layer="91"/> -<label x="53.34" y="7.62" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L6P_T0_34"/> +<wire x1="-55.88" y1="17.78" x2="-86.36" y2="17.78" width="0.1524" layer="91"/> +<label x="-73.66" y="17.78" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A13" class="0"> +<net name="FMC_D12" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L7P_T1_13"/> -<wire x1="48.26" y1="5.08" x2="78.74" y2="5.08" width="0.1524" layer="91"/> -<label x="53.34" y="5.08" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L6N_T0_VREF_34"/> +<wire x1="-55.88" y1="15.24" x2="-86.36" y2="15.24" width="0.1524" layer="91"/> +<label x="-73.66" y="15.24" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A14" class="0"> +<net name="FMC_D13" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L7N_T1_13"/> -<wire x1="48.26" y1="2.54" x2="78.74" y2="2.54" width="0.1524" layer="91"/> -<label x="53.34" y="2.54" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L7P_T1_34"/> +<wire x1="-55.88" y1="12.7" x2="-86.36" y2="12.7" width="0.1524" layer="91"/> +<label x="-73.66" y="12.7" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A15" class="0"> +<net name="FMC_D14" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L8P_T1_13"/> -<wire x1="48.26" y1="0" x2="78.74" y2="0" width="0.1524" layer="91"/> -<label x="53.34" y="0" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L7N_T1_34"/> +<wire x1="-55.88" y1="10.16" x2="-86.36" y2="10.16" width="0.1524" layer="91"/> +<label x="-73.66" y="10.16" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A16" class="0"> +<net name="FMC_D15" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L8N_T1_13"/> -<wire x1="48.26" y1="-2.54" x2="78.74" y2="-2.54" width="0.1524" layer="91"/> -<label x="53.34" y="-2.54" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L8P_T1_34"/> +<wire x1="-55.88" y1="7.62" x2="-86.36" y2="7.62" width="0.1524" layer="91"/> +<label x="-73.66" y="7.62" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A17" class="0"> +<net name="FMC_D16" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L9P_T1_DQS_13"/> -<wire x1="48.26" y1="-5.08" x2="78.74" y2="-5.08" width="0.1524" layer="91"/> -<label x="53.34" y="-5.08" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L8N_T1_34"/> +<wire x1="-55.88" y1="5.08" x2="-86.36" y2="5.08" width="0.1524" layer="91"/> +<label x="-73.66" y="5.08" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A18" class="0"> +<net name="FMC_D17" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L9N_T1_DQS_13"/> -<wire x1="48.26" y1="-7.62" x2="78.74" y2="-7.62" width="0.1524" layer="91"/> -<label x="53.34" y="-7.62" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L9P_T1_DQS_34"/> +<wire x1="-55.88" y1="2.54" x2="-86.36" y2="2.54" width="0.1524" layer="91"/> +<label x="-73.66" y="2.54" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A19" class="0"> +<net name="FMC_D18" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L10P_T1_13"/> -<wire x1="48.26" y1="-10.16" x2="78.74" y2="-10.16" width="0.1524" layer="91"/> -<label x="53.34" y="-10.16" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L9N_T1_DQS_34"/> +<wire x1="-55.88" y1="0" x2="-86.36" y2="0" width="0.1524" layer="91"/> +<label x="-73.66" y="0" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A20" class="0"> +<net name="FMC_D19" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L10N_T1_13"/> -<wire x1="48.26" y1="-12.7" x2="78.74" y2="-12.7" width="0.1524" layer="91"/> -<label x="53.34" y="-12.7" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L10P_T1_34"/> +<wire x1="-55.88" y1="-2.54" x2="-86.36" y2="-2.54" width="0.1524" layer="91"/> +<label x="-73.66" y="-2.54" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A21" class="0"> +<net name="FMC_D20" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L11P_T1_SRCC_13"/> -<wire x1="48.26" y1="-15.24" x2="78.74" y2="-15.24" width="0.1524" layer="91"/> -<label x="53.34" y="-15.24" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L10N_T1_34"/> +<wire x1="-55.88" y1="-5.08" x2="-86.36" y2="-5.08" width="0.1524" layer="91"/> +<label x="-73.66" y="-5.08" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A22" class="0"> +<net name="FMC_D21" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L11N_T1_SRCC_13"/> -<wire x1="48.26" y1="-17.78" x2="78.74" y2="-17.78" width="0.1524" layer="91"/> -<label x="53.34" y="-17.78" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L11P_T1_SRCC_34"/> +<wire x1="-55.88" y1="-7.62" x2="-86.36" y2="-7.62" width="0.1524" layer="91"/> +<label x="-73.66" y="-7.62" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A25" class="0"> +<net name="FMC_D22" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L13N_T2_MRCC_13"/> -<wire x1="48.26" y1="-27.94" x2="78.74" y2="-27.94" width="0.1524" layer="91"/> -<label x="53.34" y="-27.94" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L11N_T1_SRCC_34"/> +<wire x1="-55.88" y1="-10.16" x2="-86.36" y2="-10.16" width="0.1524" layer="91"/> +<label x="-73.66" y="-10.16" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A23" class="0"> +<net name="FMC_D23" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L12N_T1_MRCC_13"/> -<wire x1="48.26" y1="-22.86" x2="78.74" y2="-22.86" width="0.1524" layer="91"/> -<label x="53.34" y="-22.86" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L12P_T1_MRCC_34"/> +<wire x1="-55.88" y1="-12.7" x2="-86.36" y2="-12.7" width="0.1524" layer="91"/> +<label x="-73.66" y="-12.7" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_A24" class="0"> +<net name="FMC_D24" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L13P_T2_MRCC_13"/> -<wire x1="48.26" y1="-25.4" x2="78.74" y2="-25.4" width="0.1524" layer="91"/> -<label x="53.34" y="-25.4" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L12N_T1_MRCC_34"/> +<wire x1="-55.88" y1="-15.24" x2="-86.36" y2="-15.24" width="0.1524" layer="91"/> +<label x="-73.66" y="-15.24" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_CLK" class="0"> +<net name="FMC_D25" class="2"> <segment> -<pinref part="U7" gate="B13" pin="IO_L12P_T1_MRCC_13"/> -<wire x1="48.26" y1="-20.32" x2="73.66" y2="-20.32" width="0.1524" layer="91"/> -<label x="53.34" y="-20.32" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L13P_T2_MRCC_34"/> +<wire x1="-55.88" y1="-17.78" x2="-86.36" y2="-17.78" width="0.1524" layer="91"/> +<label x="-73.66" y="-17.78" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D0" class="0"> +<net name="FMC_D26" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_0_34"/> -<wire x1="-86.36" y1="45.72" x2="-55.88" y2="45.72" width="0.1524" layer="91"/> -<label x="-81.28" y="45.72" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L13N_T2_MRCC_34"/> +<wire x1="-55.88" y1="-20.32" x2="-86.36" y2="-20.32" width="0.1524" layer="91"/> +<label x="-73.66" y="-20.32" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D1" class="0"> +<net name="FMC_D27" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_L1P_T0_34"/> -<wire x1="-86.36" y1="43.18" x2="-55.88" y2="43.18" width="0.1524" layer="91"/> -<label x="-81.28" y="43.18" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L14P_T2_SRCC_34"/> +<wire x1="-55.88" y1="-22.86" x2="-86.36" y2="-22.86" width="0.1524" layer="91"/> +<label x="-73.66" y="-22.86" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D2" class="0"> +<net name="FMC_D28" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_L1N_T0_34"/> -<wire x1="-86.36" y1="40.64" x2="-55.88" y2="40.64" width="0.1524" layer="91"/> -<label x="-81.28" y="40.64" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L14N_T2_SRCC_34"/> +<wire x1="-55.88" y1="-25.4" x2="-86.36" y2="-25.4" width="0.1524" layer="91"/> +<label x="-73.66" y="-25.4" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D3" class="0"> +<net name="FMC_D29" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_L2P_T0_34"/> -<wire x1="-86.36" y1="38.1" x2="-55.88" y2="38.1" width="0.1524" layer="91"/> -<label x="-81.28" y="38.1" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L15P_T2_DQS_34"/> +<wire x1="-55.88" y1="-27.94" x2="-86.36" y2="-27.94" width="0.1524" layer="91"/> +<label x="-73.66" y="-27.94" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D4" class="0"> +<net name="FMC_D30" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_L2N_T0_34"/> -<wire x1="-86.36" y1="35.56" x2="-55.88" y2="35.56" width="0.1524" layer="91"/> -<label x="-81.28" y="35.56" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L15N_T2_DQS_34"/> +<wire x1="-55.88" y1="-30.48" x2="-86.36" y2="-30.48" width="0.1524" layer="91"/> +<label x="-73.66" y="-30.48" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D5" class="0"> +<net name="FMC_D31" class="2"> <segment> -<pinref part="U7" gate="B34" pin="IO_L3P_T0_DQS_34"/> -<wire x1="-86.36" y1="33.02" x2="-55.88" y2="33.02" width="0.1524" layer="91"/> -<label x="-81.28" y="33.02" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L16P_T2_34"/> +<wire x1="-55.88" y1="-33.02" x2="-86.36" y2="-33.02" width="0.1524" layer="91"/> +<label x="-73.66" y="-33.02" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D6" class="0"> +<net name="FMC_NE1" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L3N_T0_DQS_34"/> -<wire x1="-86.36" y1="30.48" x2="-55.88" y2="30.48" width="0.1524" layer="91"/> -<label x="-81.28" y="30.48" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L16N_T2_34"/> +<wire x1="-53.34" y1="-35.56" x2="-86.36" y2="-35.56" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_D7" class="0"> +<net name="FMC_NL" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L4P_T0_34"/> -<wire x1="-86.36" y1="27.94" x2="-55.88" y2="27.94" width="0.1524" layer="91"/> -<label x="-81.28" y="27.94" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L17P_T2_34"/> +<wire x1="-53.34" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_D8" class="0"> +<net name="FMC_NOE" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L4N_T0_34"/> -<wire x1="-86.36" y1="25.4" x2="-55.88" y2="25.4" width="0.1524" layer="91"/> -<label x="-81.28" y="25.4" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L17N_T2_34"/> +<wire x1="-53.34" y1="-40.64" x2="-86.36" y2="-40.64" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_D9" class="0"> +<net name="FMC_NWAIT" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L5P_T0_34"/> -<wire x1="-86.36" y1="22.86" x2="-55.88" y2="22.86" width="0.1524" layer="91"/> -<label x="-81.28" y="22.86" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L18P_T2_34"/> +<wire x1="-53.34" y1="-43.18" x2="-86.36" y2="-43.18" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_D10" class="0"> +<net name="FMC_NWE" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L5N_T0_34"/> -<wire x1="-86.36" y1="20.32" x2="-55.88" y2="20.32" width="0.1524" layer="91"/> -<label x="-81.28" y="20.32" size="1.778" layer="95"/> +<pinref part="U7" gate="B34" pin="IO_L18N_T2_34"/> +<wire x1="-53.34" y1="-45.72" x2="-86.36" y2="-45.72" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_D11" class="0"> +<net name="FMC_A0" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L6P_T0_34"/> -<wire x1="-86.36" y1="17.78" x2="-55.88" y2="17.78" width="0.1524" layer="91"/> -<label x="-81.28" y="17.78" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_0_13"/> +<wire x1="78.74" y1="38.1" x2="48.26" y2="38.1" width="0.1524" layer="91"/> +<label x="60.96" y="38.1" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D12" class="0"> +<net name="FMC_A1" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L6N_T0_VREF_34"/> -<wire x1="-86.36" y1="15.24" x2="-55.88" y2="15.24" width="0.1524" layer="91"/> -<label x="-81.28" y="15.24" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L1P_T0_13"/> +<wire x1="78.74" y1="35.56" x2="48.26" y2="35.56" width="0.1524" layer="91"/> +<label x="60.96" y="35.56" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D13" class="0"> +<net name="FMC_A2" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L7P_T1_34"/> -<wire x1="-86.36" y1="12.7" x2="-55.88" y2="12.7" width="0.1524" layer="91"/> -<label x="-81.28" y="12.7" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L1N_T0_13"/> +<wire x1="78.74" y1="33.02" x2="48.26" y2="33.02" width="0.1524" layer="91"/> +<label x="60.96" y="33.02" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D14" class="0"> +<net name="FMC_A3" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L7N_T1_34"/> -<wire x1="-86.36" y1="10.16" x2="-55.88" y2="10.16" width="0.1524" layer="91"/> -<label x="-81.28" y="10.16" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L2P_T0_13"/> +<wire x1="78.74" y1="30.48" x2="48.26" y2="30.48" width="0.1524" layer="91"/> +<label x="60.96" y="30.48" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D15" class="0"> +<net name="FMC_A4" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L8P_T1_34"/> -<wire x1="-86.36" y1="7.62" x2="-55.88" y2="7.62" width="0.1524" layer="91"/> -<label x="-81.28" y="7.62" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L2N_T0_13"/> +<wire x1="78.74" y1="27.94" x2="48.26" y2="27.94" width="0.1524" layer="91"/> +<label x="60.96" y="27.94" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D16" class="0"> +<net name="FMC_A5" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L8N_T1_34"/> -<wire x1="-86.36" y1="5.08" x2="-55.88" y2="5.08" width="0.1524" layer="91"/> -<label x="-81.28" y="5.08" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L3P_T0_DQS_13"/> +<wire x1="78.74" y1="25.4" x2="48.26" y2="25.4" width="0.1524" layer="91"/> +<label x="60.96" y="25.4" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D17" class="0"> +<net name="FMC_A6" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L9P_T1_DQS_34"/> -<wire x1="-86.36" y1="2.54" x2="-55.88" y2="2.54" width="0.1524" layer="91"/> -<label x="-81.28" y="2.54" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L3N_T0_DQS_13"/> +<wire x1="78.74" y1="22.86" x2="48.26" y2="22.86" width="0.1524" layer="91"/> +<label x="60.96" y="22.86" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D18" class="0"> +<net name="FMC_A7" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L9N_T1_DQS_34"/> -<wire x1="-86.36" y1="0" x2="-55.88" y2="0" width="0.1524" layer="91"/> -<label x="-81.28" y="0" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L4P_T0_13"/> +<wire x1="78.74" y1="20.32" x2="48.26" y2="20.32" width="0.1524" layer="91"/> +<label x="60.96" y="20.32" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D19" class="0"> +<net name="FMC_A8" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L10P_T1_34"/> -<wire x1="-86.36" y1="-2.54" x2="-55.88" y2="-2.54" width="0.1524" layer="91"/> -<label x="-81.28" y="-2.54" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L4N_T0_13"/> +<wire x1="78.74" y1="17.78" x2="48.26" y2="17.78" width="0.1524" layer="91"/> +<label x="60.96" y="17.78" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D20" class="0"> +<net name="FMC_A9" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L10N_T1_34"/> -<wire x1="-86.36" y1="-5.08" x2="-55.88" y2="-5.08" width="0.1524" layer="91"/> -<label x="-81.28" y="-5.08" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L5P_T0_13"/> +<wire x1="78.74" y1="15.24" x2="48.26" y2="15.24" width="0.1524" layer="91"/> +<label x="60.96" y="15.24" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D21" class="0"> +<net name="FMC_A10" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L11P_T1_SRCC_34"/> -<wire x1="-86.36" y1="-7.62" x2="-55.88" y2="-7.62" width="0.1524" layer="91"/> -<label x="-81.28" y="-7.62" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L5N_T0_13"/> +<wire x1="78.74" y1="12.7" x2="48.26" y2="12.7" width="0.1524" layer="91"/> +<label x="60.96" y="12.7" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D22" class="0"> +<net name="FMC_A11" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L11N_T1_SRCC_34"/> -<wire x1="-86.36" y1="-10.16" x2="-55.88" y2="-10.16" width="0.1524" layer="91"/> -<label x="-81.28" y="-10.16" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L6P_T0_13"/> +<wire x1="78.74" y1="10.16" x2="48.26" y2="10.16" width="0.1524" layer="91"/> +<label x="60.96" y="10.16" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D23" class="0"> +<net name="FMC_A12" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L12P_T1_MRCC_34"/> -<wire x1="-86.36" y1="-12.7" x2="-55.88" y2="-12.7" width="0.1524" layer="91"/> -<label x="-81.28" y="-12.7" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L6N_T0_VREF_13"/> +<wire x1="78.74" y1="7.62" x2="48.26" y2="7.62" width="0.1524" layer="91"/> +<label x="60.96" y="7.62" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D24" class="0"> +<net name="FMC_A13" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L12N_T1_MRCC_34"/> -<wire x1="-86.36" y1="-15.24" x2="-55.88" y2="-15.24" width="0.1524" layer="91"/> -<label x="-81.28" y="-15.24" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L7P_T1_13"/> +<wire x1="78.74" y1="5.08" x2="48.26" y2="5.08" width="0.1524" layer="91"/> +<label x="60.96" y="5.08" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D25" class="0"> +<net name="FMC_A14" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L13P_T2_MRCC_34"/> -<wire x1="-86.36" y1="-17.78" x2="-55.88" y2="-17.78" width="0.1524" layer="91"/> -<label x="-81.28" y="-17.78" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L7N_T1_13"/> +<wire x1="78.74" y1="2.54" x2="48.26" y2="2.54" width="0.1524" layer="91"/> +<label x="60.96" y="2.54" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D26" class="0"> +<net name="FMC_A15" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L13N_T2_MRCC_34"/> -<wire x1="-86.36" y1="-20.32" x2="-55.88" y2="-20.32" width="0.1524" layer="91"/> -<label x="-81.28" y="-20.32" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L8P_T1_13"/> +<wire x1="78.74" y1="0" x2="48.26" y2="0" width="0.1524" layer="91"/> +<label x="60.96" y="0" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D27" class="0"> +<net name="FMC_A16" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L14P_T2_SRCC_34"/> -<wire x1="-86.36" y1="-22.86" x2="-55.88" y2="-22.86" width="0.1524" layer="91"/> -<label x="-81.28" y="-22.86" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L8N_T1_13"/> +<wire x1="78.74" y1="-2.54" x2="48.26" y2="-2.54" width="0.1524" layer="91"/> +<label x="60.96" y="-2.54" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D28" class="0"> +<net name="FMC_A17" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L14N_T2_SRCC_34"/> -<wire x1="-86.36" y1="-25.4" x2="-55.88" y2="-25.4" width="0.1524" layer="91"/> -<label x="-81.28" y="-25.4" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L9P_T1_DQS_13"/> +<wire x1="78.74" y1="-5.08" x2="48.26" y2="-5.08" width="0.1524" layer="91"/> +<label x="60.96" y="-5.08" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D29" class="0"> +<net name="FMC_A18" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L15P_T2_DQS_34"/> -<wire x1="-86.36" y1="-27.94" x2="-55.88" y2="-27.94" width="0.1524" layer="91"/> -<label x="-81.28" y="-27.94" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L9N_T1_DQS_13"/> +<wire x1="78.74" y1="-7.62" x2="48.26" y2="-7.62" width="0.1524" layer="91"/> +<label x="60.96" y="-7.62" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D30" class="0"> +<net name="FMC_A19" class="3"> <segment> -<pinref part="U7" gate="B34" pin="IO_L15N_T2_DQS_34"/> -<wire x1="-86.36" y1="-30.48" x2="-55.88" y2="-30.48" width="0.1524" layer="91"/> -<label x="-81.28" y="-30.48" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L10P_T1_13"/> +<wire x1="78.74" y1="-10.16" x2="48.26" y2="-10.16" width="0.1524" layer="91"/> +<label x="60.96" y="-10.16" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_D31" class="0"> +<net name="FMC_A20" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L16P_T2_34"/> -<wire x1="-86.36" y1="-33.02" x2="-55.88" y2="-33.02" width="0.1524" layer="91"/> -<label x="-81.28" y="-33.02" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="IO_L10N_T1_13"/> +<wire x1="78.74" y1="-12.7" x2="48.26" y2="-12.7" width="0.1524" layer="91"/> +<label x="60.96" y="-12.7" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_NE1" class="0"> +<net name="FMC_A21" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L16N_T2_34"/> -<wire x1="-86.36" y1="-35.56" x2="-60.96" y2="-35.56" width="0.1524" layer="91"/> -<label x="-60.96" y="-35.56" size="1.778" layer="95" xref="yes"/> +<pinref part="U7" gate="B13" pin="IO_L11P_T1_SRCC_13"/> +<wire x1="78.74" y1="-15.24" x2="48.26" y2="-15.24" width="0.1524" layer="91"/> +<label x="60.96" y="-15.24" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_NL" class="0"> +<net name="FMC_A22" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L17P_T2_34"/> -<wire x1="-86.36" y1="-38.1" x2="-60.96" y2="-38.1" width="0.1524" layer="91"/> -<label x="-60.96" y="-38.1" size="1.778" layer="95" xref="yes"/> +<pinref part="U7" gate="B13" pin="IO_L11N_T1_SRCC_13"/> +<wire x1="78.74" y1="-17.78" x2="48.26" y2="-17.78" width="0.1524" layer="91"/> +<label x="60.96" y="-17.78" size="1.778" layer="95"/> </segment> </net> -<net name="FPGA_FMC_NOE" class="0"> +<net name="FMC_A23" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L17N_T2_34"/> -<wire x1="-86.36" y1="-40.64" x2="-60.96" y2="-40.64" width="0.1524" layer="91"/> -<label x="-60.96" y="-40.64" size="1.778" layer="95" xref="yes"/> +<pinref part="U7" gate="B13" pin="IO_L12N_T1_MRCC_13"/> +<wire x1="78.74" y1="-22.86" x2="48.26" y2="-22.86" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_NWAIT" class="0"> +<net name="FMC_A24" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L18P_T2_34"/> -<wire x1="-86.36" y1="-43.18" x2="-60.96" y2="-43.18" width="0.1524" layer="91"/> -<label x="-60.96" y="-43.18" size="1.778" layer="95" xref="yes"/> +<pinref part="U7" gate="B13" pin="IO_L13P_T2_MRCC_13"/> +<wire x1="78.74" y1="-25.4" x2="48.26" y2="-25.4" width="0.1524" layer="91"/> </segment> </net> -<net name="FPGA_FMC_NWE" class="0"> +<net name="FMC_A25" class="0"> <segment> -<pinref part="U7" gate="B34" pin="IO_L18N_T2_34"/> -<wire x1="-86.36" y1="-45.72" x2="-60.96" y2="-45.72" width="0.1524" layer="91"/> -<label x="-60.96" y="-45.72" size="1.778" layer="95" xref="yes"/> +<pinref part="U7" gate="B13" pin="IO_L13N_T2_MRCC_13"/> +<wire x1="78.74" y1="-27.94" x2="48.26" y2="-27.94" width="0.1524" layer="91"/> </segment> </net> </nets> @@ -43953,8 +43927,8 @@ load of 100 Ohms just in case (gives 10 mA)</text> </net> <net name="FPGA_VCCINT_1V0" class="0"> <segment> -<wire x1="73.66" y1="10.16" x2="99.06" y2="10.16" width="0.1524" layer="91"/> -<label x="76.2" y="10.16" size="1.778" layer="95"/> +<wire x1="73.66" y1="10.16" x2="78.74" y2="10.16" width="0.1524" layer="91"/> +<label x="78.74" y="10.16" size="1.778" layer="95" xref="yes"/> <pinref part="R53" gate="G$1" pin="2"/> </segment> </net> @@ -43984,9 +43958,8 @@ load of 100 Ohms just in case (gives 10 mA)</text> </net> <net name="POK_VCCINT" class="0"> <segment> -<wire x1="5.08" y1="-55.88" x2="5.08" y2="-40.64" width="0.1524" layer="91"/> -<wire x1="2.54" y1="-55.88" x2="5.08" y2="-55.88" width="0.1524" layer="91"/> -<label x="5.08" y="-53.34" size="1.778" layer="95" rot="R90"/> +<wire x1="2.54" y1="-55.88" x2="10.16" y2="-55.88" width="0.1524" layer="91"/> +<label x="10.16" y="-55.88" size="1.778" layer="95" xref="yes"/> <pinref part="U$7" gate="G$1" pin="POK"/> </segment> </net> @@ -44010,8 +43983,8 @@ load of 100 Ohms just in case (gives 10 mA)</text> <segment> <wire x1="-40.64" y1="0" x2="-50.8" y2="0" width="0.1524" layer="91"/> <wire x1="-50.8" y1="0" x2="-50.8" y2="20.32" width="0.1524" layer="91"/> -<wire x1="-50.8" y1="20.32" x2="-91.44" y2="20.32" width="0.1524" layer="91"/> -<label x="-91.44" y="20.32" size="1.778" layer="95"/> +<wire x1="-50.8" y1="20.32" x2="-63.5" y2="20.32" width="0.1524" layer="91"/> +<label x="-63.5" y="20.32" size="1.778" layer="95" rot="R180" xref="yes"/> <pinref part="U$7" gate="G$1" pin="ENABLE"/> </segment> </net> |