diff options
| author | Fredrik Thulin <fredrik@thulin.net> | 2015-12-01 09:57:27 +0100 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2015-12-01 09:57:27 +0100 |
| commit | 5f92c3dd9a22cfa5708c92b6d9e631fba2794f02 (patch) | |
| tree | 9c9777713a8b25886711f941ba8c863ec777c307 /eagle | |
| parent | 423ed91a77b5f7ec700c70e27408eb144ac2f703 (diff) | |
copied in 15 sheets of FPGA design from pavel
Diffstat (limited to 'eagle')
| -rw-r--r-- | eagle/alpha/rev02/rev02.sch | 21916 |
1 files changed, 21756 insertions, 160 deletions
diff --git a/eagle/alpha/rev02/rev02.sch b/eagle/alpha/rev02/rev02.sch index f99866e..3df1a95 100644 --- a/eagle/alpha/rev02/rev02.sch +++ b/eagle/alpha/rev02/rev02.sch @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="utf-8"?> <!DOCTYPE eagle SYSTEM "eagle.dtd"> -<eagle version="7.3.0"> +<eagle version="7.5.0"> <drawing> <settings> <setting alwaysvectorfont="no"/> @@ -1577,8 +1577,7 @@ for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trim </BODY></HTML></description> <packages> <package name="R0603"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="-0.432" y1="-0.356" x2="0.432" y2="-0.356" width="0.1524" layer="51"/> <wire x1="0.432" y1="0.356" x2="-0.432" y2="0.356" width="0.1524" layer="51"/> <wire x1="-1.473" y1="0.983" x2="1.473" y2="0.983" width="0.0508" layer="39"/> @@ -1587,8 +1586,8 @@ chip</description> <wire x1="-1.473" y1="-0.983" x2="-1.473" y2="0.983" width="0.0508" layer="39"/> <smd name="1" x="-0.85" y="0" dx="1" dy="1.1" layer="1"/> <smd name="2" x="0.85" y="0" dx="1" dy="1.1" layer="1"/> -<text x="-0.889" y="0.889" size="1.27" layer="25">>NAME</text> -<text x="-0.889" y="-2.032" size="1.27" layer="27">>VALUE</text> +<text x="-0.635" y="0.635" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-1.905" size="1.27" layer="27">>VALUE</text> <rectangle x1="0.4318" y1="-0.4318" x2="0.8382" y2="0.4318" layer="51"/> <rectangle x1="-0.8382" y1="-0.4318" x2="-0.4318" y2="0.4318" layer="51"/> <rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/> @@ -2351,8 +2350,7 @@ type RDH, grid 15 mm</description> <hole x="0" y="0" drill="1.3"/> </package> <package name="R0402"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="-0.245" y1="0.224" x2="0.245" y2="0.224" width="0.1524" layer="51"/> <wire x1="0.245" y1="-0.224" x2="-0.245" y2="-0.224" width="0.1524" layer="51"/> <wire x1="-1.473" y1="0.483" x2="1.473" y2="0.483" width="0.0508" layer="39"/> @@ -2361,66 +2359,46 @@ chip</description> <wire x1="-1.473" y1="-0.483" x2="-1.473" y2="0.483" width="0.0508" layer="39"/> <smd name="1" x="-0.65" y="0" dx="0.7" dy="0.9" layer="1"/> <smd name="2" x="0.65" y="0" dx="0.7" dy="0.9" layer="1"/> -<text x="-0.635" y="0.762" size="1.27" layer="25">>NAME</text> -<text x="-0.635" y="-2.032" size="1.27" layer="27">>VALUE</text> +<text x="-0.635" y="0.635" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-1.905" size="1.27" layer="27">>VALUE</text> <rectangle x1="-0.554" y1="-0.3048" x2="-0.254" y2="0.2951" layer="51"/> <rectangle x1="0.2588" y1="-0.3048" x2="0.5588" y2="0.2951" layer="51"/> <rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/> </package> <package name="R0805"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b><p></description> <wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/> <wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/> <wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/> <wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/> <wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/> <wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/> -<smd name="1" x="-0.85" y="0" dx="1.3" dy="1.5" layer="1"/> -<smd name="2" x="0.85" y="0" dx="1.3" dy="1.5" layer="1"/> -<text x="-0.762" y="1.016" size="1.27" layer="25">>NAME</text> -<text x="-0.762" y="-2.286" size="1.27" layer="27">>VALUE</text> +<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/> +<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/> +<text x="-0.635" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-2.54" size="1.27" layer="27">>VALUE</text> <rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/> <rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/> <rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/> </package> <package name="R0805W"> -<description><b>RESISTOR</b><p> -chip, wave soldering</description> +<description><b>RESISTOR</b> wave soldering<p></description> <wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/> <wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/> <wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/> <wire x1="1.973" y1="0.983" x2="1.973" y2="-0.983" width="0.0508" layer="39"/> <wire x1="1.973" y1="-0.983" x2="-1.973" y2="-0.983" width="0.0508" layer="39"/> <wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/> -<smd name="1" x="-0.94" y="0" dx="1.5" dy="1" layer="1"/> -<smd name="2" x="0.94" y="0" dx="1.5" dy="1" layer="1"/> -<text x="-0.635" y="1.016" size="1.27" layer="25">>NAME</text> -<text x="-0.635" y="-2.159" size="1.27" layer="27">>VALUE</text> +<smd name="1" x="-1.0525" y="0" dx="1.5" dy="1" layer="1"/> +<smd name="2" x="1.0525" y="0" dx="1.5" dy="1" layer="1"/> +<text x="-0.635" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-2.54" size="1.27" layer="27">>VALUE</text> <rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/> <rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/> <rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/> </package> -<package name="R1005"> -<description><b>RESISTOR</b><p> -chip</description> -<wire x1="-0.245" y1="0.224" x2="0.245" y2="0.224" width="0.1524" layer="51"/> -<wire x1="0.245" y1="-0.224" x2="-0.245" y2="-0.224" width="0.1524" layer="51"/> -<wire x1="-1.473" y1="0.483" x2="1.473" y2="0.483" width="0.0508" layer="39"/> -<wire x1="1.473" y1="0.483" x2="1.473" y2="-0.483" width="0.0508" layer="39"/> -<wire x1="1.473" y1="-0.483" x2="-1.473" y2="-0.483" width="0.0508" layer="39"/> -<wire x1="-1.473" y1="-0.483" x2="-1.473" y2="0.483" width="0.0508" layer="39"/> -<smd name="1" x="-0.65" y="0" dx="0.7" dy="0.9" layer="1"/> -<smd name="2" x="0.65" y="0" dx="0.7" dy="0.9" layer="1"/> -<text x="-0.635" y="0.762" size="1.27" layer="25">>NAME</text> -<text x="-0.635" y="-2.032" size="1.27" layer="27">>VALUE</text> -<rectangle x1="-0.554" y1="-0.3048" x2="-0.254" y2="0.2951" layer="51"/> -<rectangle x1="0.2588" y1="-0.3048" x2="0.5588" y2="0.2951" layer="51"/> -<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/> -</package> <package name="R1206"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="0.9525" y1="-0.8128" x2="-0.9652" y2="-0.8128" width="0.1524" layer="51"/> <wire x1="0.9525" y1="0.8128" x2="-0.9652" y2="0.8128" width="0.1524" layer="51"/> <wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/> @@ -2429,32 +2407,31 @@ chip</description> <wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/> <smd name="2" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/> <smd name="1" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/> -<text x="-1.397" y="1.143" size="1.27" layer="25">>NAME</text> -<text x="-1.397" y="-2.413" size="1.27" layer="27">>VALUE</text> +<text x="-1.27" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-1.27" y="-2.54" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.6891" y1="-0.8763" x2="-0.9525" y2="0.8763" layer="51"/> <rectangle x1="0.9525" y1="-0.8763" x2="1.6891" y2="0.8763" layer="51"/> <rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/> </package> <package name="R1206W"> <description><b>RESISTOR</b><p> -chip, wave soldering</description> -<wire x1="-0.913" y1="0.8" x2="0.888" y2="0.8" width="0.1524" layer="21"/> -<wire x1="-0.913" y1="-0.8" x2="0.888" y2="-0.8" width="0.1524" layer="21"/> +wave soldering</description> +<wire x1="-0.913" y1="0.8" x2="0.888" y2="0.8" width="0.1524" layer="51"/> +<wire x1="-0.913" y1="-0.8" x2="0.888" y2="-0.8" width="0.1524" layer="51"/> <wire x1="-2.473" y1="0.983" x2="2.473" y2="0.983" width="0.0508" layer="39"/> <wire x1="2.473" y1="0.983" x2="2.473" y2="-0.983" width="0.0508" layer="39"/> <wire x1="2.473" y1="-0.983" x2="-2.473" y2="-0.983" width="0.0508" layer="39"/> <wire x1="-2.473" y1="-0.983" x2="-2.473" y2="0.983" width="0.0508" layer="39"/> <smd name="1" x="-1.499" y="0" dx="1.8" dy="1.2" layer="1"/> <smd name="2" x="1.499" y="0" dx="1.8" dy="1.2" layer="1"/> -<text x="-1.651" y="1.143" size="1.27" layer="25">>NAME</text> -<text x="-1.651" y="-2.413" size="1.27" layer="27">>VALUE</text> +<text x="-1.905" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-1.905" y="-2.54" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.651" y1="-0.8763" x2="-0.9009" y2="0.8738" layer="51"/> <rectangle x1="0.889" y1="-0.8763" x2="1.6391" y2="0.8738" layer="51"/> <rectangle x1="-0.3" y1="-0.7" x2="0.3" y2="0.7" layer="35"/> </package> <package name="R1210"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/> <wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/> <wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/> @@ -2463,66 +2440,62 @@ chip</description> <wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/> <smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1"/> <smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1"/> -<text x="-1.27" y="1.651" size="1.27" layer="25">>NAME</text> -<text x="-1.27" y="-2.921" size="1.27" layer="27">>VALUE</text> +<text x="-2.54" y="1.905" size="1.27" layer="25">>NAME</text> +<text x="-2.54" y="-3.175" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/> <rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/> <rectangle x1="-0.3" y1="-0.8999" x2="0.3" y2="0.8999" layer="35"/> </package> <package name="R1210W"> <description><b>RESISTOR</b><p> -chip, wave soldering</description> -<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="21"/> -<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="21"/> +wave soldering</description> +<wire x1="-0.913" y1="1.219" x2="0.939" y2="1.219" width="0.1524" layer="51"/> +<wire x1="-0.913" y1="-1.219" x2="0.939" y2="-1.219" width="0.1524" layer="51"/> <wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/> <wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/> <smd name="1" x="-1.499" y="0" dx="1.8" dy="1.8" layer="1"/> <smd name="2" x="1.499" y="0" dx="1.8" dy="1.8" layer="1"/> -<text x="-1.651" y="1.524" size="1.27" layer="25">>NAME</text> -<text x="-1.651" y="-2.794" size="1.27" layer="27">>VALUE</text> +<text x="-2.54" y="1.905" size="1.27" layer="25">>NAME</text> +<text x="-2.54" y="-3.175" size="1.27" layer="27">>VALUE</text> <rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/> <rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/> <rectangle x1="-0.3" y1="-0.8001" x2="0.3" y2="0.8001" layer="35"/> </package> <package name="R2010"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/> <wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/> <wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/> <wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/> -<wire x1="-1.027" y1="1.245" x2="1.027" y2="1.245" width="0.1524" layer="21"/> -<wire x1="-1.002" y1="-1.245" x2="1.016" y2="-1.245" width="0.1524" layer="21"/> <smd name="1" x="-2.2" y="0" dx="1.8" dy="2.7" layer="1"/> <smd name="2" x="2.2" y="0" dx="1.8" dy="2.7" layer="1"/> -<text x="-2.159" y="1.651" size="1.27" layer="25">>NAME</text> -<text x="-2.159" y="-2.921" size="1.27" layer="27">>VALUE</text> +<text x="-3.175" y="1.905" size="1.27" layer="25">>NAME</text> +<text x="-3.175" y="-3.175" size="1.27" layer="27">>VALUE</text> <rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/> <rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/> </package> <package name="R2010W"> <description><b>RESISTOR</b><p> -chip, wave soldering</description> -<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="21"/> -<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="21"/> +wave soldering</description> +<wire x1="-1.662" y1="1.245" x2="1.662" y2="1.245" width="0.1524" layer="51"/> +<wire x1="-1.637" y1="-1.245" x2="1.687" y2="-1.245" width="0.1524" layer="51"/> <wire x1="-3.473" y1="1.483" x2="3.473" y2="1.483" width="0.0508" layer="39"/> <wire x1="3.473" y1="1.483" x2="3.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="3.473" y1="-1.483" x2="-3.473" y2="-1.483" width="0.0508" layer="39"/> <wire x1="-3.473" y1="-1.483" x2="-3.473" y2="1.483" width="0.0508" layer="39"/> <smd name="1" x="-2.311" y="0" dx="2" dy="1.8" layer="1"/> <smd name="2" x="2.311" y="0" dx="2" dy="1.8" layer="1"/> -<text x="-2.286" y="1.524" size="1.27" layer="25">>NAME</text> -<text x="-2.286" y="-2.921" size="1.27" layer="27">>VALUE</text> +<text x="-2.54" y="1.905" size="1.27" layer="25">>NAME</text> +<text x="-2.54" y="-3.175" size="1.27" layer="27">>VALUE</text> <rectangle x1="-2.4892" y1="-1.3208" x2="-1.6393" y2="1.3292" layer="51"/> <rectangle x1="1.651" y1="-1.3208" x2="2.5009" y2="1.3292" layer="51"/> </package> <package name="R2012"> -<description><b>RESISTOR</b><p> -chip</description> +<description><b>RESISTOR</b></description> <wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/> <wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/> <wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/> @@ -2531,15 +2504,15 @@ chip</description> <wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/> <smd name="1" x="-0.85" y="0" dx="1.3" dy="1.5" layer="1"/> <smd name="2" x="0.85" y="0" dx="1.3" dy="1.5" layer="1"/> -<text x="-0.762" y="1.016" size="1.27" layer="25">>NAME</text> -<text x="-0.762" y="-2.286" size="1.27" layer="27">>VALUE</text> +<text x="-0.635" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-2.54" size="1.27" layer="27">>VALUE</text> <rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/> <rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/> <rectangle x1="-0.1001" y1="-0.5999" x2="0.1001" y2="0.5999" layer="35"/> </package> <package name="R2012W"> <description><b>RESISTOR</b><p> -chip, wave soldering</description> +wave soldering</description> <wire x1="-0.41" y1="0.635" x2="0.41" y2="0.635" width="0.1524" layer="51"/> <wire x1="-0.41" y1="-0.635" x2="0.41" y2="-0.635" width="0.1524" layer="51"/> <wire x1="-1.973" y1="0.983" x2="1.973" y2="0.983" width="0.0508" layer="39"/> @@ -2548,51 +2521,47 @@ chip, wave soldering</description> <wire x1="-1.973" y1="-0.983" x2="-1.973" y2="0.983" width="0.0508" layer="39"/> <smd name="1" x="-0.94" y="0" dx="1.5" dy="1" layer="1"/> <smd name="2" x="0.94" y="0" dx="1.5" dy="1" layer="1"/> -<text x="-0.635" y="1.016" size="1.27" layer="25">>NAME</text> -<text x="-0.635" y="-2.286" size="1.27" layer="27">>VALUE</text> +<text x="-0.635" y="1.27" size="1.27" layer="25">>NAME</text> +<text x="-0.635" y="-2.54" size="1.27" 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width="0.1016" layer="51"/> +<smd name="+" x="-3.15" y="0" dx="2.4" dy="2.8" layer="1"/> +<smd name="-" x="3.15" y="0" dx="2.4" dy="2.8" layer="1" rot="R180"/> +<text x="-2.54" y="2.54" size="1.016" layer="25">>NAME</text> +<text x="-2.54" y="-3.81" size="1.016" layer="27">>VALUE</text> +<rectangle x1="-3.65" y1="-1.2" x2="-3.45" y2="1.2" layer="51"/> +<rectangle x1="3.45" y1="-1.2" x2="3.65" y2="1.2" layer="51" rot="R180"/> +<rectangle x1="-3.5" y1="-2.1" x2="-2.4" y2="2.1" layer="51"/> +</package> </packages> <symbols> -<symbol name="R-EU"> +<symbol name="R-EU-1"> <wire x1="-2.54" y1="-0.889" x2="2.54" y2="-0.889" width="0.254" layer="94"/> <wire x1="2.54" y1="0.889" x2="-2.54" y2="0.889" width="0.254" layer="94"/> <wire x1="2.54" y1="-0.889" x2="2.54" y2="0.889" width="0.254" layer="94"/> @@ -2900,12 +9007,34 @@ source Beyschlag</description> <pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/> <pin name="1" x="-5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1"/> </symbol> +<symbol name="C-EU-1"> +<wire x1="0" y1="0" x2="0" y2="-0.508" width="0.1524" layer="94"/> +<wire x1="0" y1="-2.54" x2="0" y2="-2.032" width="0.1524" layer="94"/> +<text x="1.524" y="0.381" size="1.778" layer="95">>NAME</text> +<text x="1.524" y="-4.699" size="1.778" layer="96">>VALUE</text> +<rectangle x1="-2.032" y1="-2.032" x2="2.032" y2="-1.524" layer="94"/> +<rectangle x1="-2.032" y1="-1.016" x2="2.032" y2="-0.508" layer="94"/> +<pin name="1" x="0" y="2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/> +<pin name="2" x="0" y="-5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/> +</symbol> +<symbol name="CPOL"> +<wire x1="-1.524" y1="-0.889" x2="1.524" y2="-0.889" width="0.254" layer="94"/> +<wire x1="1.524" y1="-0.889" x2="1.524" y2="0" width="0.254" layer="94"/> +<wire x1="-1.524" y1="0" x2="-1.524" y2="-0.889" width="0.254" layer="94"/> +<wire x1="-1.524" y1="0" x2="1.524" y2="0" width="0.254" layer="94"/> +<text x="1.143" y="0.4826" size="1.778" layer="95">>NAME</text> +<text x="-0.5842" y="0.4064" size="1.27" layer="94" rot="R90">+</text> +<text x="1.143" y="-4.5974" size="1.778" layer="96">>VALUE</text> +<rectangle x1="-1.651" y1="-2.54" x2="1.651" y2="-1.651" layer="94"/> +<pin name="-" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/> +<pin name="+" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/> +</symbol> </symbols> <devicesets> <deviceset name="R-EU_" prefix="R" uservalue="yes"> <description><B>RESISTOR</B>, European symbol</description> <gates> -<gate name="G$1" symbol="R-EU" x="0" y="0"/> +<gate name="G$1" symbol="R-EU-1" x="0" y="0"/> </gates> <devices> <device name="R0402" package="R0402"> @@ -2944,15 +9073,6 @@ source Beyschlag</description> <technology name=""/> </technologies> </device> -<device name="R1005" package="R1005"> -<connects> -<connect gate="G$1" pin="1" pad="1"/> -<connect gate="G$1" pin="2" pad="2"/> -</connects> -<technologies> -<technology name=""/> -</technologies> -</device> <device name="R1206" package="R1206"> <connects> <connect gate="G$1" pin="1" pad="1"/> @@ -3520,6 +9640,2146 @@ source Beyschlag</description> <technology name=""/> </technologies> </device> +<device name="R0201" package="R0201"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VTA52" package="VTA52"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VTA53" package="VTA53"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VTA54" package="VTA54"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VTA55" package="VTA55"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VTA56" package="VTA56"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VMTA55" package="VMTA55"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="VMTB60" package="VMTB60"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="R4527" package="R4527"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC0001" package="WSC0001"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC0002" package="WSC0002"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC01/2" package="WSC01/2"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC2515" package="WSC2515"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC4527" package="WSC4527"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="WSC6927" package="WSC6927"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="R1218" package="R1218"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1812X7R" package="1812X7R"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PRL1632" package="PRL1632"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="01005" package="R01005"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="C-EU" prefix="C" uservalue="yes"> +<description><B>CAPACITOR</B>, European symbol</description> +<gates> +<gate name="G$1" symbol="C-EU-1" x="0" y="0"/> +</gates> +<devices> +<device name="C0402" package="C0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C0504" package="C0504"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C0603" package="C0603"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C0805" package="C0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1206" package="C1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1210" package="C1210"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1310" package="C1310"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1608" package="C1608"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1812" package="C1812"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C1825" package="C1825"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C2012" package="C2012"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C3216" package="C3216"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C3225" package="C3225"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C4532" package="C4532"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C4564" package="C4564"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-024X044" package="C025-024X044"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-025X050" package="C025-025X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-030X050" package="C025-030X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-040X050" package="C025-040X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-050X050" package="C025-050X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-060X050" package="C025-060X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> 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+<device name="075-032X103" package="C075-032X103"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="075-042X103" package="C075-042X103"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="075-052X106" package="C075-052X106"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102-043X133" package="C102-043X133"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102-054X133" package="C102-054X133"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect 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pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMCC" package="SMC_C"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMCD" package="SMC_D"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMCE" package="SMC_E"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> </devices> </deviceset> </devicesets> @@ -5884,6 +14144,29 @@ Source: http://www.vishay.com/docs/10129/hpc0201a.pdf</description> <text x="1.27" y="11.43" size="2.54" layer="94">Document Number:</text> <text x="17.78" y="19.05" size="2.54" layer="94">>DRAWING_NAME</text> </symbol> +<symbol name="A4L-LOC"> +<wire x1="256.54" y1="3.81" x2="256.54" y2="8.89" width="0.1016" layer="94"/> +<wire x1="256.54" y1="8.89" x2="256.54" y2="13.97" width="0.1016" layer="94"/> +<wire x1="256.54" y1="13.97" x2="256.54" y2="19.05" width="0.1016" layer="94"/> +<wire x1="256.54" y1="19.05" x2="256.54" y2="24.13" width="0.1016" layer="94"/> +<wire x1="161.29" y1="3.81" x2="161.29" y2="24.13" width="0.1016" layer="94"/> +<wire x1="161.29" y1="24.13" x2="215.265" y2="24.13" width="0.1016" layer="94"/> +<wire x1="215.265" y1="24.13" x2="256.54" y2="24.13" width="0.1016" layer="94"/> +<wire x1="246.38" y1="3.81" x2="246.38" y2="8.89" width="0.1016" layer="94"/> +<wire x1="246.38" y1="8.89" x2="256.54" y2="8.89" width="0.1016" layer="94"/> +<wire x1="246.38" y1="8.89" x2="215.265" y2="8.89" width="0.1016" layer="94"/> +<wire x1="215.265" y1="8.89" x2="215.265" y2="3.81" width="0.1016" layer="94"/> +<wire x1="215.265" y1="8.89" x2="215.265" y2="13.97" width="0.1016" layer="94"/> +<wire x1="215.265" y1="13.97" x2="256.54" y2="13.97" width="0.1016" layer="94"/> +<wire x1="215.265" y1="13.97" x2="215.265" y2="19.05" width="0.1016" layer="94"/> +<wire x1="215.265" y1="19.05" x2="256.54" y2="19.05" width="0.1016" layer="94"/> +<wire x1="215.265" y1="19.05" x2="215.265" y2="24.13" width="0.1016" layer="94"/> +<text x="217.17" y="15.24" size="2.54" layer="94">>DRAWING_NAME</text> +<text x="217.17" y="10.16" size="2.286" layer="94">>LAST_DATE_TIME</text> +<text x="230.505" y="5.08" size="2.54" layer="94">>SHEET</text> +<text x="216.916" y="4.953" size="2.54" layer="94">Sheet:</text> +<frame x1="0" y1="0" x2="260.35" y2="179.07" columns="6" rows="4" layer="94"/> +</symbol> </symbols> <devicesets> <deviceset name="A3L-LOC" prefix="FRAME" uservalue="yes"> @@ -5914,6 +14197,20 @@ DIN A3, landscape with location and doc. field</description> </device> </devices> </deviceset> +<deviceset name="A4L-LOC" prefix="FRAME" uservalue="yes"> +<description><b>FRAME</b><p> +DIN A4, landscape with location and doc. field</description> +<gates> +<gate name="G$1" symbol="A4L-LOC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> </devicesets> </library> <library name="SparkFun-Aesthetics"> @@ -24611,6 +32908,26 @@ Source: 008-0260-0_E.pdf</description> <text x="-2.54" y="2.54" size="1.27" layer="25">>NAME</text> <text x="-2.54" y="-3.81" size="1.27" layer="27">>VALUE</text> </package> +<package name="ASF"> +<description><b>CRYSTAL CLOCK OSCILLATORS</b><p> +5.0 Vdc or 3.3 Vdc - LOW PROFILE ULTRA MINIATURE CERAMIC SURFACE MOUNT<br> +Source: http://www.abracon.com/Oscillators/asf1-L-L1.pdf</description> +<wire x1="-2.2" y1="1.5" x2="2.2" y2="1.5" width="0.2032" layer="51"/> +<wire x1="2.4" y1="1.3" x2="2.4" y2="-1.3" width="0.2032" layer="21"/> +<wire x1="2.2" y1="-1.5" x2="-2.2" y2="-1.5" width="0.2032" layer="51"/> +<wire x1="-2.4" y1="-1.3" x2="-2.4" y2="1.3" width="0.2032" layer="21"/> +<wire x1="-2.2" y1="1.5" x2="-2.4" y2="1.3" width="0.2032" layer="21" curve="-90"/> +<wire x1="2.4" y1="1.3" x2="2.2" y2="1.5" width="0.2032" layer="21" curve="-90"/> +<wire x1="-2.4" y1="-1.3" x2="-2.2" y2="-1.5" width="0.2032" layer="21" curve="-90"/> +<wire x1="2.2" y1="-1.5" x2="2.4" y2="-1.3" width="0.2032" layer="21" curve="-90"/> +<circle x="-1.9" y="-0.95" radius="0.1802" width="0" layer="51"/> +<smd name="1" x="-1.25" y="-1.15" dx="1.6" dy="1.5" layer="1"/> +<smd name="2" x="1.25" y="-1.15" dx="1.6" dy="1.5" layer="1"/> +<smd name="3" x="1.25" y="1.15" dx="1.6" dy="1.5" layer="1" rot="R180"/> +<smd name="4" x="-1.25" y="1.15" dx="1.6" dy="1.5" layer="1" rot="R180"/> +<text x="-2.54" y="2.54" size="1.27" layer="25">>NAME</text> +<text x="-2.54" y="-3.81" size="1.27" layer="27">>VALUE</text> +</package> </packages> <symbols> <symbol name="Q"> @@ -24629,6 +32946,44 @@ Source: 008-0260-0_E.pdf</description> <pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/> <pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/> </symbol> +<symbol name="QG1"> +<wire x1="-7.62" y1="7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="7.62" y1="-7.62" x2="-7.62" y2="-7.62" width="0.4064" layer="94"/> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="0" width="0.4064" layer="94"/> +<wire x1="7.62" y1="0" x2="7.62" y2="5.08" width="0.4064" layer="94"/> +<wire x1="7.62" y1="5.08" x2="7.62" y2="7.62" width="0.4064" layer="94"/> +<wire x1="-7.62" y1="7.62" x2="7.62" y2="7.62" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="5.08" x2="2.54" y2="2.54" width="0.4064" layer="94"/> +<wire x1="2.54" y1="2.54" x2="6.35" y2="0" width="0.4064" layer="94"/> +<wire x1="6.35" y1="0" x2="-1.27" y2="-5.08" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="-5.08" x2="-1.27" y2="-3.175" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="-3.175" x2="-1.27" y2="3.175" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="3.175" x2="-1.27" y2="5.08" width="0.4064" layer="94"/> +<wire x1="-3.81" y1="3.175" x2="-1.27" y2="3.175" width="0.1524" layer="94"/> +<wire x1="-3.81" y1="-3.175" x2="-1.27" y2="-3.175" width="0.1524" layer="94"/> +<wire x1="6.35" y1="0" x2="7.62" y2="0" width="0.1524" layer="94"/> +<wire x1="7.62" y1="5.08" x2="2.54" y2="5.08" width="0.1524" layer="94"/> +<wire x1="2.54" y1="5.08" x2="2.54" y2="2.54" width="0.1524" layer="94"/> +<wire x1="-4.826" y1="-0.381" x2="-4.826" y2="0.381" width="0.254" layer="94"/> +<wire x1="-4.826" y1="0.381" x2="-2.794" y2="0.381" width="0.254" layer="94"/> +<wire x1="-2.794" y1="0.381" x2="-2.794" y2="-0.381" width="0.254" layer="94"/> +<wire x1="-4.826" y1="-0.381" x2="-2.794" y2="-0.381" width="0.254" layer="94"/> +<wire x1="-5.08" y1="-1.016" x2="-3.81" y2="-1.016" width="0.254" layer="94"/> +<wire x1="-3.81" y1="-1.016" x2="-2.54" y2="-1.016" width="0.254" layer="94"/> +<wire x1="-3.81" y1="1.016" x2="-3.81" y2="3.175" width="0.1524" layer="94"/> +<wire x1="-3.81" y1="-3.175" x2="-3.81" y2="-1.016" width="0.1524" layer="94"/> +<wire x1="-5.08" y1="1.016" x2="-2.54" y2="1.016" width="0.254" layer="94"/> +<text x="-7.62" y="8.255" size="1.778" layer="95">>NAME</text> +<text x="-7.62" y="-10.16" size="1.778" layer="96">>VALUE</text> +<text x="-6.985" y="-5.842" size="1.524" layer="95">GND</text> +<text x="-6.985" y="4.318" size="1.524" layer="95">VCC</text> +<text x="4.064" y="-3.556" size="1.524" layer="95">FO</text> +<text x="3.81" y="5.588" size="1.524" layer="95">OE</text> +<pin name="GND" x="-12.7" y="-5.08" visible="pad" length="middle" direction="pwr"/> +<pin name="VCC" x="-12.7" y="5.08" visible="pad" length="middle" direction="pwr"/> +<pin name="FO" x="12.7" y="0" visible="pad" length="middle" direction="out" rot="R180"/> +<pin name="OE" x="12.7" y="5.08" visible="pad" length="middle" direction="in" rot="R180"/> +</symbol> </symbols> <devicesets> <deviceset name="CRYSTAL" prefix="Q" uservalue="yes"> @@ -24933,6 +33288,7515 @@ Source: 008-0260-0_E.pdf</description> </device> </devices> </deviceset> +<deviceset name="ASF*" prefix="Q"> +<description><b>CRYSTAL CLOCK OSCILLATORS</b><p> +5.0 Vdc or 3.3 Vdc - LOW PROFILE ULTRA MINIATURE CERAMIC SURFACE MOUNT<br> +Source: http://www.abracon.com/Oscillators/asf1-L-L1.pdf</description> +<gates> +<gate name="G$1" symbol="QG1" x="0" y="0"/> +</gates> +<devices> +<device name="" package="ASF"> +<connects> +<connect gate="G$1" pin="FO" pad="3"/> +<connect gate="G$1" pin="GND" pad="2"/> +<connect gate="G$1" pin="OE" pad="1"/> +<connect gate="G$1" pin="VCC" pad="4"/> +</connects> +<technologies> +<technology name="1"> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="" constant="no"/> +<attribute name="OC_FARNELL" value="unknown" constant="no"/> +<attribute name="OC_NEWARK" value="unknown" constant="no"/> +</technology> +<technology name="L"> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="ASFLM1-50.000MHZ-C-T" constant="no"/> +<attribute name="OC_FARNELL" value="1838931" constant="no"/> +<attribute name="OC_NEWARK" value="99M0411" constant="no"/> +</technology> +<technology name="L1"> +<attribute name="MF" value="Abracon Corporation" constant="no"/> +<attribute name="MPN" value="ASFL1-125.000MHZ-EC-T" constant="no"/> +<attribute name="OC_FARNELL" value="1838931" constant="no"/> +<attribute name="OC_NEWARK" value="19M1882" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="Xilinx_XC7A200TFBG484"> +<packages> +<package name="FF484"> +<description><b>FF484 FBG484</b></description> +<wire x1="-11.5" y1="11.5" x2="-11.5" y2="-11.5" width="0.254" layer="21"/> +<wire x1="-11.5" y1="-11.5" x2="11.5" y2="-11.5" width="0.254" layer="21"/> +<wire x1="11.5" y1="-11.5" x2="11.5" y2="11.5" width="0.254" layer="21"/> +<wire x1="11.5" y1="11.5" x2="-11.5" y2="11.5" width="0.254" layer="21"/> +<wire x1="-9.75" y1="8.75" x2="-9.75" y2="-8.75" width="0.127" layer="51"/> +<wire x1="-9.75" y1="-8.75" x2="-8.75" y2="-9.75" width="0.127" layer="51" curve="90"/> +<wire x1="-8.75" y1="-9.75" x2="8.75" y2="-9.75" width="0.127" layer="51"/> +<wire x1="8.75" y1="-9.75" x2="9.75" y2="-8.75" width="0.127" layer="51" curve="90"/> +<wire x1="9.75" y1="-8.75" x2="9.75" y2="8.75" width="0.127" layer="51"/> +<wire x1="9.75" y1="8.75" x2="8.75" y2="9.75" width="0.127" layer="51" curve="90"/> +<wire x1="8.75" y1="9.75" x2="-8.75" y2="9.75" width="0.127" layer="51"/> +<wire x1="-8.75" y1="9.75" x2="-9.75" y2="8.75" width="0.127" layer="51" curve="90"/> +<wire x1="-8.75" y1="8.25" x2="-8.75" y2="-8.25" width="0.127" layer="51"/> +<wire x1="-8.75" y1="-8.25" x2="-8.25" y2="-8.75" width="0.127" layer="51" curve="90"/> +<wire x1="-8.25" y1="-8.75" x2="8.25" y2="-8.75" width="0.127" layer="51"/> +<wire x1="8.25" y1="-8.75" x2="8.75" y2="-8.25" width="0.127" layer="51" curve="90"/> +<wire x1="8.75" y1="-8.25" x2="8.75" y2="8.25" width="0.127" layer="51"/> +<wire x1="8.75" y1="8.25" x2="8.25" y2="8.75" width="0.127" layer="51" curve="90"/> +<wire x1="8.25" y1="8.75" x2="-8.25" y2="8.75" width="0.127" layer="51"/> +<wire x1="-8.25" y1="8.75" x2="-8.75" y2="8.25" width="0.127" layer="51" curve="90"/> +<circle x="-10.5" y="10.5" radius="0.5" width="0.127" layer="21"/> +<smd name="A1" x="-10.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A2" x="-9.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A3" x="-8.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A4" x="-7.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A5" x="-6.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A6" x="-5.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A7" x="-4.5" y="10.5" dx="0.5" dy="0.5" layer="1" roundness="100"/> +<smd name="A8" x="-3.5" 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x="5.08" y="-2.54" length="middle" rot="R180"/> +<pin name="VREFN_0" x="5.08" y="-5.08" length="middle" rot="R180"/> +<pin name="GNDADC_0" x="5.08" y="-7.62" length="middle" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="XC7A200TFBG484" prefix="U"> +<description>Xilinx FPGA: XC7A200TFBG484</description> +<gates> +<gate name="B0" symbol="XC7A200TFBG484_0" x="0" y="0"/> +<gate name="B13" symbol="XC7A200TFBG484_13" x="45.72" y="0"/> +<gate name="B14" symbol="XC7A200TFBG484_14" x="91.44" y="0"/> +<gate name="B15" symbol="XC7A200TFBG484_15" x="137.16" y="0"/> +<gate name="B16" symbol="XC7A200TFBG484_16" x="182.88" y="0"/> +<gate name="B34" symbol="XC7A200TFBG484_34" x="228.6" y="0"/> +<gate name="B35" symbol="XC7A200TFBG484_35" x="274.32" y="0"/> +<gate name="B216" symbol="XC7A200TFBG484_216" x="320.04" y="0"/> +<gate name="BGNDA" symbol="XC7A200TFBG484_GNDA" x="365.76" y="0"/> +<gate name="BGNDB" symbol="XC7A200TFBG484_GNDB" x="411.48" y="0"/> +<gate name="BMGTAVCC" symbol="XC7A200TFBG484_MGTAVCC" x="457.2" y="0"/> +<gate name="BMGTAVTT" symbol="XC7A200TFBG484_MGTAVTT" x="502.92" y="0"/> +<gate name="BTDIODE" symbol="XC7A200TFBG484_TDIODE" x="548.64" y="0"/> +<gate name="BVCCAUX" symbol="XC7A200TFBG484_VCCAUX" x="594.36" y="0"/> +<gate name="BVCCBRAM" symbol="XC7A200TFBG484_VCCBRAM" x="640.08" y="0"/> +<gate name="BVCCINT" symbol="XC7A200TFBG484_VCCINT" x="685.8" y="0"/> +<gate name="BXADC" symbol="XC7A200TFBG484_XADC" x="731.52" y="0"/> +</gates> +<devices> +<device name="" package="FF484"> +<connects> +<connect gate="B0" pin="CCLK_0" pad="L12"/> +<connect gate="B0" pin="CFGBVS_0" pad="U8"/> +<connect gate="B0" pin="DONE_0" pad="G11"/> +<connect gate="B0" pin="INIT_B_0" pad="U12"/> +<connect gate="B0" pin="M0_0" pad="U11"/> +<connect gate="B0" pin="M1_0" pad="U10"/> +<connect gate="B0" pin="M2_0" pad="U9"/> +<connect gate="B0" pin="PROGRAM_B_0" pad="N12"/> +<connect gate="B0" pin="TCK_0" pad="V12"/> +<connect gate="B0" pin="TDI_0" pad="R13"/> +<connect gate="B0" pin="TDO_0" pad="U13"/> +<connect gate="B0" pin="TMS_0" pad="T13"/> +<connect gate="B0" pin="VCCBATT_0" pad="E12"/> +<connect gate="B0" pin="VCCO_0@0" pad="F12"/> +<connect gate="B0" pin="VCCO_0@1" pad="T12"/> +<connect gate="B13" pin="IO_0_13" pad="Y17"/> +<connect gate="B13" pin="IO_L10N_T1_13" pad="W10"/> +<connect gate="B13" pin="IO_L10P_T1_13" pad="V10"/> +<connect gate="B13" pin="IO_L11N_T1_SRCC_13" pad="Y12"/> +<connect gate="B13" pin="IO_L11P_T1_SRCC_13" pad="Y11"/> +<connect gate="B13" pin="IO_L12N_T1_MRCC_13" pad="W12"/> +<connect gate="B13" pin="IO_L12P_T1_MRCC_13" pad="W11"/> +<connect gate="B13" pin="IO_L13N_T2_MRCC_13" pad="V14"/> +<connect gate="B13" pin="IO_L13P_T2_MRCC_13" pad="V13"/> +<connect gate="B13" pin="IO_L14N_T2_SRCC_13" pad="V15"/> +<connect gate="B13" pin="IO_L14P_T2_SRCC_13" pad="U15"/> +<connect gate="B13" pin="IO_L15N_T2_DQS_13" pad="T15"/> +<connect gate="B13" pin="IO_L15P_T2_DQS_13" pad="T14"/> +<connect gate="B13" pin="IO_L16N_T2_13" pad="W16"/> +<connect gate="B13" pin="IO_L16P_T2_13" pad="W15"/> +<connect gate="B13" pin="IO_L17N_T2_13" pad="U16"/> +<connect gate="B13" pin="IO_L17P_T2_13" pad="T16"/> +<connect gate="B13" pin="IO_L1N_T0_13" pad="AA16"/> +<connect gate="B13" pin="IO_L1P_T0_13" pad="Y16"/> +<connect gate="B13" pin="IO_L2N_T0_13" pad="AB17"/> +<connect gate="B13" pin="IO_L2P_T0_13" pad="AB16"/> +<connect gate="B13" pin="IO_L3N_T0_DQS_13" pad="AB13"/> +<connect gate="B13" pin="IO_L3P_T0_DQS_13" pad="AA13"/> +<connect gate="B13" pin="IO_L4N_T0_13" pad="AB15"/> +<connect gate="B13" pin="IO_L4P_T0_13" pad="AA15"/> +<connect gate="B13" pin="IO_L5N_T0_13" pad="AA14"/> +<connect gate="B13" pin="IO_L5P_T0_13" pad="Y13"/> +<connect gate="B13" pin="IO_L6N_T0_VREF_13" pad="Y14"/> +<connect gate="B13" pin="IO_L6P_T0_13" pad="W14"/> +<connect gate="B13" pin="IO_L7N_T1_13" pad="AB12"/> +<connect gate="B13" pin="IO_L7P_T1_13" pad="AB11"/> +<connect gate="B13" pin="IO_L8N_T1_13" pad="AB10"/> +<connect gate="B13" pin="IO_L8P_T1_13" pad="AA9"/> +<connect gate="B13" pin="IO_L9N_T1_DQS_13" pad="AA11"/> +<connect gate="B13" pin="IO_L9P_T1_DQS_13" pad="AA10"/> +<connect gate="B13" pin="VCCO_13@0" pad="V16"/> +<connect gate="B13" pin="VCCO_13@1" pad="W13"/> +<connect gate="B13" pin="VCCO_13@2" pad="Y10"/> +<connect gate="B13" pin="VCCO_13@3" pad="AA17"/> +<connect gate="B13" pin="VCCO_13@4" pad="AB14"/> +<connect gate="B14" pin="IO_0_14" pad="P20"/> +<connect gate="B14" pin="IO_25_14" pad="N15"/> +<connect gate="B14" pin="IO_L10N_T1_D15_14" pad="AB22"/> +<connect gate="B14" pin="IO_L10P_T1_D14_14" pad="AB21"/> +<connect gate="B14" pin="IO_L11N_T1_SRCC_14" pad="V20"/> +<connect gate="B14" pin="IO_L11P_T1_SRCC_14" pad="U20"/> +<connect gate="B14" pin="IO_L12N_T1_MRCC_14" pad="W20"/> +<connect gate="B14" pin="IO_L12P_T1_MRCC_14" pad="W19"/> +<connect gate="B14" pin="IO_L13N_T2_MRCC_14" pad="Y19"/> +<connect gate="B14" pin="IO_L13P_T2_MRCC_14" pad="Y18"/> +<connect gate="B14" pin="IO_L14N_T2_SRCC_14" pad="V19"/> +<connect gate="B14" pin="IO_L14P_T2_SRCC_14" pad="V18"/> +<connect gate="B14" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/> +<connect gate="B14" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/> +<connect gate="B14" pin="IO_L16N_T2_A15_D31_14" pad="W17"/> +<connect gate="B14" pin="IO_L16P_T2_CSI_B_14" pad="V17"/> +<connect gate="B14" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/> +<connect gate="B14" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/> +<connect gate="B14" pin="IO_L18N_T2_A11_D27_14" pad="U18"/> +<connect gate="B14" pin="IO_L18P_T2_A12_D28_14" pad="U17"/> +<connect gate="B14" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/> +<connect gate="B14" pin="IO_L19P_T3_A10_D26_14" pad="P14"/> +<connect gate="B14" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/> +<connect gate="B14" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/> +<connect gate="B14" pin="IO_L20N_T3_A07_D23_14" pad="T18"/> +<connect gate="B14" pin="IO_L20P_T3_A08_D24_14" pad="R18"/> +<connect gate="B14" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/> +<connect gate="B14" pin="IO_L21P_T3_DQS_14" pad="N17"/> +<connect gate="B14" pin="IO_L22N_T3_A04_D20_14" pad="R16"/> +<connect gate="B14" pin="IO_L22P_T3_A05_D21_14" pad="P15"/> +<connect gate="B14" pin="IO_L23N_T3_A02_D18_14" pad="N14"/> +<connect gate="B14" pin="IO_L23P_T3_A03_D19_14" pad="N13"/> +<connect gate="B14" pin="IO_L24N_T3_A00_D16_14" pad="R17"/> +<connect gate="B14" pin="IO_L24P_T3_A01_D17_14" pad="P16"/> +<connect gate="B14" pin="IO_L2N_T0_D03_14" pad="R21"/> +<connect gate="B14" pin="IO_L2P_T0_D02_14" pad="P21"/> +<connect gate="B14" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/> +<connect gate="B14" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/> +<connect gate="B14" pin="IO_L4N_T0_D05_14" pad="U21"/> +<connect gate="B14" pin="IO_L4P_T0_D04_14" pad="T21"/> +<connect gate="B14" pin="IO_L5N_T0_D07_14" pad="R19"/> +<connect gate="B14" pin="IO_L5P_T0_D06_14" pad="P19"/> +<connect gate="B14" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/> +<connect gate="B14" pin="IO_L6P_T0_FCS_B_14" pad="T19"/> +<connect gate="B14" pin="IO_L7N_T1_D10_14" pad="W22"/> +<connect gate="B14" pin="IO_L7P_T1_D09_14" pad="W21"/> +<connect gate="B14" pin="IO_L8N_T1_D12_14" pad="AA21"/> +<connect gate="B14" pin="IO_L8P_T1_D11_14" pad="AA20"/> +<connect gate="B14" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/> +<connect gate="B14" pin="IO_L9P_T1_DQS_14" pad="Y21"/> +<connect gate="B14" pin="VCCO_14@0" pad="M14"/> +<connect gate="B14" pin="VCCO_14@1" pad="P18"/> +<connect gate="B14" pin="VCCO_14@2" pad="R15"/> +<connect gate="B14" pin="VCCO_14@3" pad="T22"/> +<connect gate="B14" pin="VCCO_14@4" pad="U19"/> +<connect gate="B14" pin="VCCO_14@5" pad="Y20"/> +<connect gate="B15" pin="IO_0_15" pad="J16"/> +<connect gate="B15" pin="IO_25_15" pad="M17"/> +<connect gate="B15" pin="IO_L10N_T1_AD11N_15" pad="L21"/> +<connect gate="B15" pin="IO_L10P_T1_AD11P_15" pad="M21"/> +<connect gate="B15" pin="IO_L11N_T1_SRCC_15" pad="J21"/> +<connect gate="B15" pin="IO_L11P_T1_SRCC_15" pad="J20"/> +<connect gate="B15" pin="IO_L12N_T1_MRCC_15" pad="H19"/> +<connect gate="B15" pin="IO_L12P_T1_MRCC_15" pad="J19"/> +<connect gate="B15" pin="IO_L13N_T2_MRCC_15" pad="K19"/> +<connect gate="B15" pin="IO_L13P_T2_MRCC_15" pad="K18"/> +<connect gate="B15" pin="IO_L14N_T2_SRCC_15" pad="L20"/> +<connect gate="B15" pin="IO_L14P_T2_SRCC_15" pad="L19"/> +<connect gate="B15" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/> +<connect gate="B15" pin="IO_L15P_T2_DQS_15" pad="N22"/> +<connect gate="B15" pin="IO_L16N_T2_A27_15" pad="L18"/> +<connect gate="B15" pin="IO_L16P_T2_A28_15" pad="M18"/> +<connect gate="B15" pin="IO_L17N_T2_A25_15" pad="N19"/> +<connect gate="B15" pin="IO_L17P_T2_A26_15" pad="N18"/> +<connect gate="B15" pin="IO_L18N_T2_A23_15" pad="M20"/> +<connect gate="B15" pin="IO_L18P_T2_A24_15" pad="N20"/> +<connect gate="B15" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/> +<connect gate="B15" pin="IO_L19P_T3_A22_15" pad="K13"/> +<connect gate="B15" pin="IO_L1N_T0_AD0N_15" pad="G13"/> +<connect gate="B15" pin="IO_L1P_T0_AD0P_15" pad="H13"/> +<connect gate="B15" pin="IO_L20N_T3_A19_15" pad="L13"/> +<connect gate="B15" pin="IO_L20P_T3_A20_15" pad="M13"/> +<connect gate="B15" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/> +<connect gate="B15" pin="IO_L21P_T3_DQS_15" pad="K17"/> +<connect gate="B15" pin="IO_L22N_T3_A16_15" pad="L15"/> +<connect gate="B15" pin="IO_L22P_T3_A17_15" pad="L14"/> +<connect gate="B15" pin="IO_L23N_T3_FWE_B_15" pad="K16"/> +<connect gate="B15" pin="IO_L23P_T3_FOE_B_15" pad="L16"/> +<connect gate="B15" pin="IO_L24N_T3_RS0_15" pad="M16"/> +<connect gate="B15" pin="IO_L24P_T3_RS1_15" pad="M15"/> +<connect gate="B15" pin="IO_L2N_T0_AD8N_15" pad="G16"/> +<connect gate="B15" pin="IO_L2P_T0_AD8P_15" pad="G15"/> +<connect gate="B15" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/> +<connect gate="B15" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/> +<connect gate="B15" pin="IO_L4N_T0_15" pad="G18"/> +<connect gate="B15" pin="IO_L4P_T0_15" pad="G17"/> +<connect gate="B15" pin="IO_L5N_T0_AD9N_15" pad="H15"/> +<connect gate="B15" pin="IO_L5P_T0_AD9P_15" pad="J15"/> +<connect gate="B15" pin="IO_L6N_T0_VREF_15" pad="H18"/> +<connect gate="B15" pin="IO_L6P_T0_15" pad="H17"/> +<connect gate="B15" pin="IO_L7N_T1_AD2N_15" pad="H22"/> +<connect gate="B15" pin="IO_L7P_T1_AD2P_15" pad="J22"/> +<connect gate="B15" pin="IO_L8N_T1_AD10N_15" pad="G20"/> +<connect gate="B15" pin="IO_L8P_T1_AD10P_15" pad="H20"/> +<connect gate="B15" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/> +<connect gate="B15" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/> +<connect gate="B15" pin="VCCO_15@0" pad="G19"/> +<connect gate="B15" pin="VCCO_15@1" pad="H16"/> +<connect gate="B15" pin="VCCO_15@2" pad="J13"/> +<connect gate="B15" pin="VCCO_15@3" pad="K20"/> +<connect gate="B15" pin="VCCO_15@4" pad="L17"/> +<connect gate="B15" pin="VCCO_15@5" pad="N21"/> +<connect gate="B16" pin="IO_0_16" pad="F15"/> +<connect gate="B16" pin="IO_25_16" pad="F21"/> +<connect gate="B16" pin="IO_L10N_T1_16" pad="A14"/> +<connect gate="B16" pin="IO_L10P_T1_16" pad="A13"/> +<connect gate="B16" pin="IO_L11N_T1_SRCC_16" pad="B18"/> +<connect gate="B16" pin="IO_L11P_T1_SRCC_16" pad="B17"/> +<connect gate="B16" pin="IO_L12N_T1_MRCC_16" pad="C17"/> +<connect gate="B16" pin="IO_L12P_T1_MRCC_16" pad="D17"/> +<connect gate="B16" pin="IO_L13N_T2_MRCC_16" pad="C19"/> +<connect gate="B16" pin="IO_L13P_T2_MRCC_16" pad="C18"/> +<connect gate="B16" pin="IO_L14N_T2_SRCC_16" pad="D19"/> +<connect gate="B16" pin="IO_L14P_T2_SRCC_16" pad="E19"/> +<connect gate="B16" pin="IO_L15N_T2_DQS_16" pad="E18"/> +<connect gate="B16" pin="IO_L15P_T2_DQS_16" pad="F18"/> +<connect gate="B16" pin="IO_L16N_T2_16" pad="A20"/> +<connect gate="B16" pin="IO_L16P_T2_16" pad="B20"/> +<connect gate="B16" pin="IO_L17N_T2_16" pad="A19"/> +<connect gate="B16" pin="IO_L17P_T2_16" pad="A18"/> +<connect gate="B16" pin="IO_L18N_T2_16" pad="F20"/> +<connect gate="B16" pin="IO_L18P_T2_16" pad="F19"/> +<connect gate="B16" pin="IO_L19N_T3_VREF_16" pad="C20"/> +<connect gate="B16" pin="IO_L19P_T3_16" pad="D20"/> +<connect gate="B16" pin="IO_L1N_T0_16" pad="F14"/> +<connect gate="B16" pin="IO_L1P_T0_16" pad="F13"/> +<connect gate="B16" pin="IO_L20N_T3_16" pad="B22"/> +<connect gate="B16" pin="IO_L20P_T3_16" pad="C22"/> +<connect gate="B16" pin="IO_L21N_T3_DQS_16" pad="A21"/> +<connect gate="B16" pin="IO_L21P_T3_DQS_16" pad="B21"/> +<connect gate="B16" pin="IO_L22N_T3_16" pad="D22"/> +<connect gate="B16" pin="IO_L22P_T3_16" pad="E22"/> +<connect gate="B16" pin="IO_L23N_T3_16" pad="D21"/> +<connect gate="B16" pin="IO_L23P_T3_16" pad="E21"/> +<connect gate="B16" pin="IO_L24N_T3_16" pad="G22"/> +<connect gate="B16" pin="IO_L24P_T3_16" pad="G21"/> +<connect gate="B16" pin="IO_L2N_T0_16" pad="E17"/> +<connect gate="B16" pin="IO_L2P_T0_16" pad="F16"/> +<connect gate="B16" pin="IO_L3N_T0_DQS_16" pad="C15"/> +<connect gate="B16" pin="IO_L3P_T0_DQS_16" pad="C14"/> +<connect gate="B16" pin="IO_L4N_T0_16" pad="E14"/> +<connect gate="B16" pin="IO_L4P_T0_16" pad="E13"/> +<connect gate="B16" pin="IO_L5N_T0_16" pad="D16"/> +<connect gate="B16" pin="IO_L5P_T0_16" pad="E16"/> +<connect gate="B16" pin="IO_L6N_T0_VREF_16" pad="D15"/> +<connect gate="B16" pin="IO_L6P_T0_16" pad="D14"/> +<connect gate="B16" pin="IO_L7N_T1_16" pad="B16"/> +<connect gate="B16" pin="IO_L7P_T1_16" pad="B15"/> +<connect gate="B16" pin="IO_L8N_T1_16" pad="B13"/> +<connect gate="B16" pin="IO_L8P_T1_16" pad="C13"/> +<connect gate="B16" pin="IO_L9N_T1_DQS_16" pad="A16"/> +<connect gate="B16" pin="IO_L9P_T1_DQS_16" pad="A15"/> +<connect gate="B16" pin="VCCO_16@0" pad="A17"/> +<connect gate="B16" pin="VCCO_16@1" pad="B14"/> +<connect gate="B16" pin="VCCO_16@2" pad="C21"/> +<connect gate="B16" pin="VCCO_16@3" pad="D18"/> +<connect gate="B16" pin="VCCO_16@4" pad="E15"/> +<connect gate="B16" pin="VCCO_16@5" pad="F22"/> +<connect gate="B216" pin="MGTPRXN0_216" pad="C11"/> +<connect gate="B216" pin="MGTPRXN1_216" pad="A10"/> +<connect gate="B216" pin="MGTPRXN2_216" pad="C9"/> +<connect gate="B216" pin="MGTPRXN3_216" pad="A8"/> +<connect gate="B216" pin="MGTPRXP0_216" pad="D11"/> +<connect gate="B216" pin="MGTPRXP1_216" pad="B10"/> +<connect gate="B216" pin="MGTPRXP2_216" pad="D9"/> +<connect gate="B216" pin="MGTPRXP3_216" pad="B8"/> +<connect gate="B216" pin="MGTPTXN0_216" pad="C7"/> +<connect gate="B216" pin="MGTPTXN1_216" pad="A6"/> +<connect gate="B216" pin="MGTPTXN2_216" pad="C5"/> +<connect gate="B216" pin="MGTPTXN3_216" pad="A4"/> +<connect gate="B216" pin="MGTPTXP0_216" pad="D7"/> +<connect gate="B216" pin="MGTPTXP1_216" pad="B6"/> +<connect gate="B216" pin="MGTPTXP2_216" pad="D5"/> +<connect gate="B216" pin="MGTPTXP3_216" pad="B4"/> +<connect gate="B216" pin="MGTREFCLK0N_216" pad="E10"/> +<connect gate="B216" pin="MGTREFCLK0P_216" pad="F10"/> +<connect gate="B216" pin="MGTREFCLK1N_216" pad="E6"/> +<connect gate="B216" pin="MGTREFCLK1P_216" pad="F6"/> +<connect gate="B216" pin="MGTRREF_216" pad="F8"/> +<connect gate="B34" pin="IO_0_34" pad="T3"/> +<connect gate="B34" pin="IO_25_34" pad="U7"/> +<connect gate="B34" pin="IO_L10N_T1_34" pad="AB5"/> +<connect gate="B34" pin="IO_L10P_T1_34" pad="AA5"/> +<connect gate="B34" pin="IO_L11N_T1_SRCC_34" pad="AA4"/> +<connect gate="B34" pin="IO_L11P_T1_SRCC_34" pad="Y4"/> +<connect gate="B34" pin="IO_L12N_T1_MRCC_34" pad="W4"/> +<connect gate="B34" pin="IO_L12P_T1_MRCC_34" pad="V4"/> +<connect gate="B34" pin="IO_L13N_T2_MRCC_34" pad="T4"/> +<connect gate="B34" pin="IO_L13P_T2_MRCC_34" pad="R4"/> +<connect gate="B34" pin="IO_L14N_T2_SRCC_34" pad="U5"/> +<connect gate="B34" pin="IO_L14P_T2_SRCC_34" pad="T5"/> +<connect gate="B34" pin="IO_L15N_T2_DQS_34" pad="W5"/> +<connect gate="B34" pin="IO_L15P_T2_DQS_34" pad="W6"/> +<connect gate="B34" pin="IO_L16N_T2_34" pad="V5"/> +<connect gate="B34" pin="IO_L16P_T2_34" pad="U6"/> +<connect gate="B34" pin="IO_L17N_T2_34" pad="T6"/> +<connect gate="B34" pin="IO_L17P_T2_34" pad="R6"/> +<connect gate="B34" pin="IO_L18N_T2_34" pad="AA6"/> +<connect gate="B34" pin="IO_L18P_T2_34" pad="Y6"/> +<connect gate="B34" pin="IO_L19N_T3_VREF_34" pad="W7"/> +<connect gate="B34" pin="IO_L19P_T3_34" pad="V7"/> +<connect gate="B34" pin="IO_L1N_T0_34" pad="U1"/> +<connect gate="B34" pin="IO_L1P_T0_34" pad="T1"/> +<connect gate="B34" pin="IO_L20N_T3_34" pad="AB6"/> +<connect gate="B34" pin="IO_L20P_T3_34" pad="AB7"/> +<connect gate="B34" pin="IO_L21N_T3_DQS_34" pad="V8"/> +<connect gate="B34" pin="IO_L21P_T3_DQS_34" pad="V9"/> +<connect gate="B34" pin="IO_L22N_T3_34" pad="AB8"/> +<connect gate="B34" pin="IO_L22P_T3_34" pad="AA8"/> +<connect gate="B34" pin="IO_L23N_T3_34" pad="Y7"/> +<connect gate="B34" pin="IO_L23P_T3_34" pad="Y8"/> +<connect gate="B34" pin="IO_L24N_T3_34" pad="Y9"/> +<connect gate="B34" pin="IO_L24P_T3_34" pad="W9"/> +<connect gate="B34" pin="IO_L2N_T0_34" pad="V2"/> +<connect gate="B34" pin="IO_L2P_T0_34" pad="U2"/> +<connect gate="B34" pin="IO_L3N_T0_DQS_34" pad="R2"/> +<connect gate="B34" pin="IO_L3P_T0_DQS_34" pad="R3"/> +<connect gate="B34" pin="IO_L4N_T0_34" pad="Y2"/> +<connect gate="B34" pin="IO_L4P_T0_34" pad="W2"/> +<connect gate="B34" pin="IO_L5N_T0_34" pad="Y1"/> +<connect gate="B34" pin="IO_L5P_T0_34" pad="W1"/> +<connect gate="B34" pin="IO_L6N_T0_VREF_34" pad="V3"/> +<connect gate="B34" pin="IO_L6P_T0_34" pad="U3"/> +<connect gate="B34" pin="IO_L7N_T1_34" pad="AB1"/> +<connect gate="B34" pin="IO_L7P_T1_34" pad="AA1"/> +<connect gate="B34" pin="IO_L8N_T1_34" pad="AB2"/> +<connect gate="B34" pin="IO_L8P_T1_34" pad="AB3"/> +<connect gate="B34" pin="IO_L9N_T1_DQS_34" pad="AA3"/> +<connect gate="B34" pin="IO_L9P_T1_DQS_34" pad="Y3"/> +<connect gate="B34" pin="VCCO_34@0" pad="R5"/> +<connect gate="B34" pin="VCCO_34@1" pad="T2"/> +<connect gate="B34" pin="VCCO_34@2" pad="V6"/> +<connect gate="B34" pin="VCCO_34@3" pad="W3"/> +<connect gate="B34" pin="VCCO_34@4" pad="AA7"/> +<connect gate="B34" pin="VCCO_34@5" pad="AB4"/> +<connect gate="B35" pin="IO_0_35" pad="F4"/> +<connect gate="B35" pin="IO_25_35" pad="L6"/> +<connect gate="B35" pin="IO_L10N_T1_AD15N_35" pad="H5"/> +<connect gate="B35" pin="IO_L10P_T1_AD15P_35" pad="J5"/> +<connect gate="B35" pin="IO_L11N_T1_SRCC_35" pad="G3"/> +<connect gate="B35" pin="IO_L11P_T1_SRCC_35" pad="H3"/> +<connect gate="B35" pin="IO_L12N_T1_MRCC_35" pad="G4"/> +<connect gate="B35" pin="IO_L12P_T1_MRCC_35" pad="H4"/> +<connect gate="B35" pin="IO_L13N_T2_MRCC_35" pad="J4"/> +<connect gate="B35" pin="IO_L13P_T2_MRCC_35" pad="K4"/> +<connect gate="B35" pin="IO_L14N_T2_SRCC_35" pad="K3"/> +<connect gate="B35" pin="IO_L14P_T2_SRCC_35" pad="L3"/> +<connect gate="B35" pin="IO_L15N_T2_DQS_35" pad="L1"/> +<connect gate="B35" pin="IO_L15P_T2_DQS_35" pad="M1"/> +<connect gate="B35" pin="IO_L16N_T2_35" pad="M2"/> +<connect gate="B35" pin="IO_L16P_T2_35" pad="M3"/> +<connect gate="B35" pin="IO_L17N_T2_35" pad="J6"/> +<connect gate="B35" pin="IO_L17P_T2_35" pad="K6"/> +<connect gate="B35" pin="IO_L18N_T2_35" pad="L4"/> +<connect gate="B35" pin="IO_L18P_T2_35" pad="L5"/> +<connect gate="B35" pin="IO_L19N_T3_VREF_35" pad="N3"/> +<connect gate="B35" pin="IO_L19P_T3_35" pad="N4"/> +<connect gate="B35" pin="IO_L1N_T0_AD4N_35" pad="A1"/> +<connect gate="B35" pin="IO_L1P_T0_AD4P_35" pad="B1"/> +<connect gate="B35" pin="IO_L20N_T3_35" pad="P1"/> +<connect gate="B35" pin="IO_L20P_T3_35" pad="R1"/> +<connect gate="B35" pin="IO_L21N_T3_DQS_35" pad="P4"/> +<connect gate="B35" pin="IO_L21P_T3_DQS_35" pad="P5"/> +<connect gate="B35" pin="IO_L22N_T3_35" pad="N2"/> +<connect gate="B35" pin="IO_L22P_T3_35" pad="P2"/> +<connect gate="B35" pin="IO_L23N_T3_35" pad="M5"/> +<connect gate="B35" pin="IO_L23P_T3_35" pad="M6"/> +<connect gate="B35" pin="IO_L24N_T3_35" pad="N5"/> +<connect gate="B35" pin="IO_L24P_T3_35" pad="P6"/> +<connect gate="B35" pin="IO_L2N_T0_AD12N_35" pad="B2"/> +<connect gate="B35" pin="IO_L2P_T0_AD12P_35" pad="C2"/> +<connect gate="B35" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/> +<connect gate="B35" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/> +<connect gate="B35" pin="IO_L4N_T0_35" pad="D2"/> +<connect gate="B35" pin="IO_L4P_T0_35" pad="E2"/> +<connect gate="B35" pin="IO_L5N_T0_AD13N_35" pad="F1"/> +<connect gate="B35" pin="IO_L5P_T0_AD13P_35" pad="G1"/> +<connect gate="B35" pin="IO_L6N_T0_VREF_35" pad="E3"/> +<connect gate="B35" pin="IO_L6P_T0_35" pad="F3"/> +<connect gate="B35" pin="IO_L7N_T1_AD6N_35" pad="J1"/> +<connect gate="B35" pin="IO_L7P_T1_AD6P_35" pad="K1"/> +<connect gate="B35" pin="IO_L8N_T1_AD14N_35" pad="G2"/> +<connect gate="B35" pin="IO_L8P_T1_AD14P_35" pad="H2"/> +<connect gate="B35" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/> +<connect gate="B35" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/> +<connect gate="B35" pin="VCCO_35@0" pad="C1"/> +<connect gate="B35" pin="VCCO_35@1" pad="F2"/> +<connect gate="B35" pin="VCCO_35@2" pad="H6"/> +<connect gate="B35" pin="VCCO_35@3" pad="J3"/> +<connect gate="B35" pin="VCCO_35@4" pad="M4"/> +<connect gate="B35" pin="VCCO_35@5" pad="N1"/> +<connect gate="BGNDA" pin="GND@0" pad="A2"/> +<connect gate="BGNDA" pin="GND@1" pad="A3"/> +<connect gate="BGNDA" pin="GND@10" pad="B19"/> +<connect gate="BGNDA" pin="GND@11" pad="C3"/> +<connect gate="BGNDA" pin="GND@12" pad="C6"/> +<connect gate="BGNDA" pin="GND@13" pad="C10"/> +<connect gate="BGNDA" pin="GND@14" pad="C12"/> +<connect gate="BGNDA" pin="GND@15" pad="C16"/> +<connect gate="BGNDA" pin="GND@16" pad="D3"/> +<connect gate="BGNDA" pin="GND@17" pad="D4"/> +<connect gate="BGNDA" pin="GND@18" pad="D8"/> +<connect gate="BGNDA" pin="GND@19" pad="D12"/> +<connect gate="BGNDA" pin="GND@2" pad="A5"/> +<connect gate="BGNDA" pin="GND@20" pad="D13"/> +<connect gate="BGNDA" pin="GND@21" pad="E4"/> +<connect gate="BGNDA" pin="GND@22" pad="E5"/> +<connect gate="BGNDA" pin="GND@23" pad="E7"/> +<connect gate="BGNDA" pin="GND@24" pad="E9"/> +<connect gate="BGNDA" pin="GND@25" pad="E11"/> +<connect gate="BGNDA" pin="GND@26" pad="E20"/> +<connect gate="BGNDA" pin="GND@27" pad="F5"/> +<connect gate="BGNDA" pin="GND@28" pad="F11"/> +<connect gate="BGNDA" pin="GND@29" pad="F17"/> +<connect gate="BGNDA" pin="GND@3" pad="A7"/> +<connect gate="BGNDA" pin="GND@30" pad="G5"/> +<connect gate="BGNDA" pin="GND@31" pad="G6"/> +<connect gate="BGNDA" pin="GND@32" pad="G7"/> +<connect gate="BGNDA" pin="GND@33" pad="G8"/> +<connect gate="BGNDA" pin="GND@34" pad="G9"/> +<connect gate="BGNDA" pin="GND@35" pad="G10"/> +<connect gate="BGNDA" pin="GND@36" pad="G12"/> +<connect gate="BGNDA" pin="GND@37" pad="G14"/> +<connect gate="BGNDA" pin="GND@38" pad="H1"/> +<connect gate="BGNDA" pin="GND@39" pad="H7"/> +<connect gate="BGNDA" pin="GND@4" pad="A9"/> +<connect gate="BGNDA" pin="GND@40" pad="H9"/> +<connect gate="BGNDA" pin="GND@41" pad="H11"/> +<connect gate="BGNDA" pin="GND@42" pad="H21"/> +<connect gate="BGNDA" pin="GND@43" pad="J8"/> +<connect gate="BGNDA" pin="GND@5" pad="A11"/> +<connect gate="BGNDA" pin="GND@6" pad="A12"/> +<connect gate="BGNDA" pin="GND@7" pad="A22"/> +<connect gate="BGNDA" pin="GND@8" pad="B3"/> +<connect gate="BGNDA" pin="GND@9" pad="B12"/> +<connect gate="BGNDB" pin="GND@44" pad="J10"/> +<connect gate="BGNDB" pin="GND@45" pad="J12"/> +<connect gate="BGNDB" pin="GND@46" pad="J18"/> +<connect gate="BGNDB" pin="GND@47" pad="K5"/> +<connect gate="BGNDB" pin="GND@48" pad="K7"/> +<connect gate="BGNDB" pin="GND@49" pad="K11"/> +<connect gate="BGNDB" pin="GND@50" pad="K15"/> +<connect gate="BGNDB" pin="GND@51" pad="L2"/> +<connect gate="BGNDB" pin="GND@52" pad="L8"/> +<connect gate="BGNDB" pin="GND@53" pad="L22"/> +<connect gate="BGNDB" pin="GND@54" pad="M7"/> +<connect gate="BGNDB" pin="GND@55" pad="M11"/> +<connect gate="BGNDB" pin="GND@56" pad="M19"/> +<connect gate="BGNDB" pin="GND@57" pad="N6"/> +<connect gate="BGNDB" pin="GND@58" pad="N8"/> +<connect gate="BGNDB" pin="GND@59" pad="N16"/> +<connect gate="BGNDB" pin="GND@60" pad="P3"/> +<connect gate="BGNDB" pin="GND@61" pad="P7"/> +<connect gate="BGNDB" pin="GND@62" pad="P9"/> +<connect gate="BGNDB" pin="GND@63" pad="P11"/> +<connect gate="BGNDB" pin="GND@64" pad="P13"/> +<connect gate="BGNDB" pin="GND@65" pad="R8"/> +<connect gate="BGNDB" pin="GND@66" pad="R10"/> +<connect gate="BGNDB" pin="GND@67" pad="R12"/> +<connect gate="BGNDB" pin="GND@68" pad="R20"/> +<connect gate="BGNDB" pin="GND@69" pad="T7"/> +<connect gate="BGNDB" pin="GND@70" pad="T9"/> +<connect gate="BGNDB" pin="GND@71" pad="T11"/> +<connect gate="BGNDB" pin="GND@72" pad="T17"/> +<connect gate="BGNDB" pin="GND@73" pad="U4"/> +<connect gate="BGNDB" pin="GND@74" pad="U14"/> +<connect gate="BGNDB" pin="GND@75" pad="V1"/> +<connect gate="BGNDB" pin="GND@76" pad="V11"/> +<connect gate="BGNDB" pin="GND@77" pad="V21"/> +<connect gate="BGNDB" pin="GND@78" pad="W8"/> +<connect gate="BGNDB" pin="GND@79" pad="W18"/> +<connect gate="BGNDB" pin="GND@80" pad="Y5"/> +<connect gate="BGNDB" pin="GND@81" pad="Y15"/> +<connect gate="BGNDB" pin="GND@82" pad="AA2"/> +<connect gate="BGNDB" pin="GND@83" pad="AA12"/> +<connect gate="BGNDB" pin="GND@84" pad="AA22"/> +<connect gate="BGNDB" pin="GND@85" pad="AB9"/> +<connect gate="BGNDB" pin="GND@86" pad="AB19"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@0" pad="D6"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@1" pad="D10"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@2" pad="E8"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@3" pad="F7"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@4" pad="F9"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@0" pad="B5"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@1" pad="B7"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@2" pad="B9"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@3" pad="B11"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@4" pad="C4"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@5" pad="C8"/> +<connect gate="BTDIODE" pin="DXN_0" pad="N9"/> +<connect gate="BTDIODE" pin="DXP_0" pad="N10"/> +<connect gate="BVCCAUX" pin="VCCAUX@0" pad="H12"/> +<connect gate="BVCCAUX" pin="VCCAUX@1" pad="K12"/> +<connect gate="BVCCAUX" pin="VCCAUX@2" pad="M12"/> +<connect gate="BVCCAUX" pin="VCCAUX@3" pad="P12"/> +<connect gate="BVCCAUX" pin="VCCAUX@4" pad="R11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@0" pad="J11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@1" pad="L11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@2" pad="N11"/> +<connect gate="BVCCINT" pin="VCCINT@0" pad="H8"/> +<connect gate="BVCCINT" pin="VCCINT@1" pad="H10"/> +<connect gate="BVCCINT" pin="VCCINT@10" pad="R7"/> +<connect gate="BVCCINT" pin="VCCINT@11" pad="R9"/> +<connect gate="BVCCINT" pin="VCCINT@12" pad="T8"/> +<connect gate="BVCCINT" pin="VCCINT@13" pad="T10"/> +<connect gate="BVCCINT" pin="VCCINT@2" pad="J7"/> +<connect gate="BVCCINT" pin="VCCINT@3" pad="J9"/> +<connect gate="BVCCINT" pin="VCCINT@4" pad="K8"/> +<connect gate="BVCCINT" pin="VCCINT@5" pad="L7"/> +<connect gate="BVCCINT" pin="VCCINT@6" pad="M8"/> +<connect gate="BVCCINT" pin="VCCINT@7" pad="N7"/> +<connect gate="BVCCINT" pin="VCCINT@8" pad="P8"/> +<connect gate="BVCCINT" pin="VCCINT@9" pad="P10"/> +<connect gate="BXADC" pin="GNDADC_0" pad="K9"/> +<connect gate="BXADC" pin="VCCADC_0" pad="K10"/> +<connect gate="BXADC" pin="VN_0" pad="M9"/> +<connect gate="BXADC" pin="VP_0" pad="L10"/> +<connect gate="BXADC" pin="VREFN_0" pad="L9"/> +<connect gate="BXADC" pin="VREFP_0" pad="M10"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="altera-configdevices"> +<packages> +<package name="SO08"> +<description><b>Small Outline Package</b></description> +<wire x1="2.159" y1="1.9558" x2="-2.159" y2="1.9558" width="0.1524" layer="21"/> +<wire x1="2.159" y1="-1.9558" x2="2.54" y2="-1.5748" width="0.1524" layer="21" curve="90"/> +<wire x1="-2.54" y1="1.5748" x2="-2.159" y2="1.9558" width="0.1524" layer="21" curve="-90"/> +<wire x1="2.159" y1="1.9558" x2="2.54" y2="1.5748" width="0.1524" layer="21" curve="-90"/> +<wire x1="-2.54" y1="-1.5748" x2="-2.159" y2="-1.9558" width="0.1524" layer="21" curve="90"/> +<wire x1="-2.159" y1="-1.9558" x2="2.159" y2="-1.9558" width="0.1524" layer="21"/> +<wire x1="2.54" y1="-1.5748" x2="2.54" y2="1.5748" width="0.1524" layer="21"/> +<wire x1="-2.54" y1="1.5748" x2="-2.54" y2="-1.5748" width="0.1524" layer="21"/> +<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21" curve="-180"/> +<wire x1="-2.54" y1="-1.6002" x2="2.54" y2="-1.6002" width="0.0508" layer="21"/> +<smd name="1" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="8" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="2" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="3" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="7" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="6" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="4" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="5" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> 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layer="51"/> +<wire x1="-0.75" y1="-0.35" x2="-0.75" y2="0.35" width="0.1016" layer="51"/> +<wire x1="-0.45" y1="0.3" x2="-0.45" y2="-0.3" width="0.1016" layer="51"/> +<wire x1="0.45" y1="0.3" x2="0.45" y2="-0.3" width="0.1016" layer="51"/> +<wire x1="-0.2" y1="0.35" x2="0.2" y2="0.35" width="0.1016" layer="21"/> +<wire x1="-0.2" y1="-0.35" x2="0.2" y2="-0.35" width="0.1016" layer="21"/> +<smd name="C" x="-0.75" y="0" dx="0.8" dy="0.8" layer="1"/> +<smd name="A" x="0.75" y="0" dx="0.8" dy="0.8" layer="1"/> +<text x="-1" y="1" size="1.27" layer="25">>NAME</text> +<text x="-1" y="-2" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-0.4" y1="0.175" x2="0" y2="0.4" layer="51"/> +<rectangle x1="-0.25" y1="0.175" x2="0" y2="0.4" layer="21"/> +</package> +</packages> +<symbols> +<symbol name="LED"> +<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/> +<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/> +<wire x1="1.27" y1="-2.54" x2="0" y2="-2.54" width="0.254" layer="94"/> +<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/> +<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="0" y2="-2.54" width="0.1524" layer="94"/> +<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/> +<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/> +<text x="3.556" y="-4.572" size="1.778" layer="95" rot="R90">>NAME</text> +<text x="5.715" y="-4.572" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/> +<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/> +<polygon width="0.1524" layer="94"> +<vertex x="-3.429" y="-2.159"/> +<vertex x="-3.048" y="-1.27"/> +<vertex x="-2.54" y="-1.778"/> +</polygon> +<polygon width="0.1524" layer="94"> +<vertex x="-3.302" y="-3.302"/> +<vertex x="-2.921" y="-2.413"/> +<vertex x="-2.413" y="-2.921"/> +</polygon> +</symbol> +</symbols> +<devicesets> +<deviceset name="LED" prefix="LED" uservalue="yes"> +<description><b>LED</b><p> +<u>OSRAM</u>:<br> + +- <u>CHIPLED</u><br> +LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971 +LH N974, LH R974<br> +LS Q976, LO Q976, LY Q976<br> +LO Q996<br> + +- <u>Hyper CHIPLED</u><br> +LW Q18S<br> +LB Q993, LB Q99A, LB R99A<br> + +- <u>SideLED</u><br> +LS A670, LO A670, LY A670, LG A670, LP A670<br> +LB A673, LV A673, LT A673, LW A673<br> +LH A674<br> +LY A675<br> +LS A676, LA A676, LO A676, LY A676, LW A676<br> +LS A679, LY A679, LG A679<br> + +- <u>Hyper Micro SIDELED®</u><br> +LS Y876, LA Y876, LO Y876, LY Y876<br> +LT Y87S<br> + +- <u>SmartLED</u><br> +LW L88C, LW L88S<br> +LB L89C, LB L89S, LG L890<br> +LS L89K, LO L89K, LY L89K<br> +LS L896, LA L896, LO L896, LY L896<br> + +- <u>TOPLED</u><br> +LS T670, LO T670, LY T670, LG T670, LP T670<br> +LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br> +LG T671, LOG T671, LSG T671<br> +LB T673, LV T673, LT T673, LW T673<br> +LH T674<br> +LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br> +LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br> +LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br> +LW T67C<br> +LS T679, LY T679, LG T679<br> +LS T770, LO T770, LY T770, LG T770, LP T770<br> +LB T773, LV T773, LT T773, LW T773<br> +LH T774<br> +LS E675, LA E675, LY E675, LS T675<br> +LS T776, LA T776, LO T776, LY T776, LB T776<br> +LHGB T686<br> +LT T68C, LB T68C<br> + +- <u>Hyper Mini TOPLED®</u><br> +LB M676<br> + +- <u>Mini TOPLED Santana®</u><br> +LG M470<br> +LS M47K, LO M47K, LY M47K +<p> +Source: http://www.osram.convergy.de<p> + +<u>LUXEON:</u><br> +- <u>LUMILED®</u><br> +LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br> +LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br> +LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br> +LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br> +LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br> +LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br> +LXK2-PH12-R00, LXK2-PH12-S00<br> +LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00 +<p> +Source: www.luxeon.com<p> + +<u>KINGBRIGHT:</U><p> +KA-3528ASYC<br> +Source: www.kingbright.com</description> +<gates> +<gate name="G$1" symbol="LED" x="0" y="0"/> +</gates> +<devices> +<device name="SMT1206" package="1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LD260" package="LD260"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SQR2X5" package="LED2X5"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="3MM" package="LED3MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="5MM" package="LED5MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LSU260" package="LSU260"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LZR181" package="LZR181"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B152" package="Q62902-B152"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B153" package="Q62902-B153"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B155" package="Q62902-B155"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B156" package="Q62902-B156"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SFH480" package="SFH480"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SFH482" package="SFH482"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SQR5.7X3.2" package="U57X32"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="IRL80A" package="IRL80A"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-2" package="P-LCC-2"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="MINI-TOP" package="OSRAM-MINI-TOP-LED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SIDELED" package="OSRAM-SIDELED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMART-LED" package="SMART-LED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="B"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-2-BACK" package="P-LCC-2-TOPLED-RG"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="MICRO-SIDELED" package="MICRO-SIDELED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-4" package="P-LCC-4"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C@4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIP-LED0603" package="CHIP-LED0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIP-LED0805" package="CHIP-LED0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="TOPLED-SANTANA" package="MINI-TOPLED-SANTANA"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_0805" package="CHIPLED_0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_1206" package="CHIPLED_1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_0603" package="CHIPLED_0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED-0603-TTW" package="CHIPLED-0603-TTW"> +<connects> +<connect gate="G$1" pin="A" pad="A@1"/> +<connect gate="G$1" pin="C" pad="C@1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="" package="SMARTLED-TTW"> +<connects> +<connect gate="G$1" pin="A" pad="A@1"/> +<connect gate="G$1" pin="C" pad="C@1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-LUMILED+" package="LUMILED+"> +<connects> +<connect gate="G$1" pin="A" pad="2+"/> +<connect gate="G$1" pin="C" pad="4-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-LUMILED" package="LUMILED"> +<connects> +<connect gate="G$1" pin="A" pad="2+"/> +<connect gate="G$1" pin="C" pad="4-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="10MM" package="LED10MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="KA-3528ASYC" package="KA-3528ASYC"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML0805" package="SML0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML1206" package="SML1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML0603" package="SML0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="con-lstb"> +<description><b>Pin Headers</b><p> +Naming:<p> +MA = male<p> +# contacts - # rows<p> +W = angled<p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="MA08-2"> +<description><b>PIN HEADER</b></description> +<wire x1="-9.525" y1="2.54" x2="-8.255" y2="2.54" width="0.1524" layer="21"/> +<wire x1="-8.255" y1="2.54" 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pad="P$61"/> +<connect gate="G$1" pin="MAR2" pad="P$62"/> +<connect gate="G$1" pin="OCP_ADJ" pad="P$58"/> +<connect gate="G$1" pin="PGND" pad="P$1 P$2 P$3 P$4 P$27 P$28 P$29 P$30 P$31 P$32 P$33 P$64 P$65 P$66 P$67 P$68 P$69 P$70 P$71"/> +<connect gate="G$1" pin="POK" pad="P$54"/> +<connect gate="G$1" pin="PVIN" pad="P$34 P$35 P$36 P$37 P$38 P$39 P$40 P$41 P$42 P$43"/> +<connect gate="G$1" pin="SS" pad="P$59"/> +<connect gate="G$1" pin="S_DELAY" pad="P$60"/> +<connect gate="G$1" pin="S_IN" pad="P$49"/> +<connect gate="G$1" pin="S_OUT" pad="P$48"/> +<connect gate="G$1" pin="VFB" pad="P$56"/> +<connect gate="G$1" pin="VOUT" pad="P$5 P$6 P$7 P$8 P$9 P$10 P$11 P$12 P$13"/> +<connect gate="G$1" pin="VSENSE" pad="P$63"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="EN5364QI" constant="no"/> +<attribute name="OC_FARNELL" value="2081142" constant="no"/> +<attribute name="PACKAGE" value="QFN" constant="no"/> +<attribute name="SUPPLIER" value="ENPIRION" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LMZ13608"> +<description>LMZ13608 8-A SIMPLE SWITCHER +Power Module With 36-V Maximum Input Voltage + +http://www.ti.com/lit/ds/symlink/lmz13608.pdf</description> +<gates> +<gate name="G$1" symbol="LMZ22008" x="0" y="0"/> +</gates> +<devices> +<device name="" package="NDY"> +<connects> +<connect gate="G$1" pin="AGND@5" pad="P$5"/> +<connect gate="G$1" pin="AGND@6" pad="P$6"/> +<connect gate="G$1" pin="EN" pad="P$4"/> +<connect gate="G$1" pin="FB" pad="P$7"/> +<connect gate="G$1" pin="PGND" pad="P$8"/> +<connect gate="G$1" pin="SH" pad="P$10"/> +<connect gate="G$1" pin="SS/TRK" pad="P$9"/> +<connect gate="G$1" pin="SYNC" pad="P$3"/> +<connect gate="G$1" pin="VIN@1" pad="P$1"/> +<connect gate="G$1" pin="VIN@2" pad="P$2"/> +<connect gate="G$1" pin="VOUT@10" pad="P$11"/> +<connect gate="G$1" pin="VOUT@11" pad="P$12"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="LMZ13608TZ/NOPB" constant="no"/> +<attribute name="OC_FARNELL" value="2492265" constant="no"/> +<attribute name="PACKAGE" value="NDY (11)" constant="no"/> +<attribute name="SUPPLIER" value="Texas Instruments" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="rc-master"> +<description><b>R/C MASTER! - v1.07 (07/03/2007)</b><p> +<p>This library is a collection of SMD and through hole resistors and capacitors by various manufacturers. Some of these include types from Panasonic, Kemet, BC Components and others. Many of the packages were adapted from <b>rcl.lbr</b> and <b>cap-pan40.lbr</b> and have been renamed and grouped in a more logical form.</p><p>Silkscreen elements are a minimum of 8 mils in width with larger components using 10 mil widths. Most of the SMD components have text sizes of 0 .04" and thru-hole components are 0.05" in size. A text ratio of 14 is used in both cases. Where practical, the elements are aligned on a 12.5 mil or 6.25 mil grid depending on the pad size and spacing.</p> +<p><h4>All capacitors are grouped by the following naming conventions:</h4></p> +<table width="380" border="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><div align="center"><strong>Prefix</strong></div></td> + <td width="289" bgcolor="#33CCFF"><div align="center"><strong>Description</strong></div></td> + </tr> + <tr> + <td><div align="center">CBP_</div></td> + <td><div align="center">Bipolar Electrolytic Types</div></td> + </tr> + <tr> + <td><div align="center">CCA_</div></td> + <td><div align="center">Chip Cap Array Types</div></td> + </tr> + <tr> + <td><div align="center">CP_</div></td> + <td><div align="center">Polarized Electrolytic/Tantalum Types</div></td> + </tr> + <tr> + <td><div align="center">C_</div></td> + <td><div align="center">Non-Polarized Film / Chip Types</div></td> + </tr> + <tr> + <td><div align="center">FB_</div></td> + <td><div align="center">Simple Ferrite Bead Types</div></td> + </tr> + <tr> + <td><div align="center">L_</div></td> + <td><div align="center">Simple Chip Inductors</div></td> + </tr> + <tr> + <td><div align="center">R_</div></td> + <td><div align="center">Resistor Types</div></td> + </tr> +</table> +<p> +<p><author>THIS LIBRARY IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR IMPLIED.<br>Copyright (C) 2007, Bob Starr<br> http://www.bobstarr.net<br> +</author></description> +<packages> +<package name="CE-010X030"> +<description><b>POLCAP RADIAL</b><p> +1.0 mm lead spacing, 3 mm diameter, grid 0.0125 inch</description> +<wire x1="-2.2225" y1="0.9525" x2="-1.5875" y2="0.9525" width="0.254" layer="21"/> +<wire x1="-1.905" y1="0.635" x2="-1.905" y2="1.27" width="0.254" layer="21"/> +<wire x1="-0.3587" y1="0" x2="-0.7" y2="0" width="0.2032" layer="51"/> +<wire x1="0.2764" y1="0" x2="0.7" y2="0" width="0.2032" layer="51"/> +<wire x1="0.2" y1="0" x2="0.4" y2="0.6" width="0.254" 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+<technology name=""/> +</technologies> +</device> +<device name="SV-J" package="CSV-J"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SV-K" package="CSV-K"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="GC-SD-H" package="CGOLD-SD-H"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="GC-SD-V" package="CGOLD-SD-V"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="E-015X040" package="CE-015X040"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="E-020X060" package="CE-020X060"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="E-025X075" package="CE-025X075"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="E-025X085" package="CE-025X085"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="EH-035-080X115" package="CEH-035-080X115"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="EH-035-080X115/R" package="CEH-035-080X115/R"> +<connects> +<connect gate="G$1" pin="+" pad="+"/> +<connect gate="G$1" pin="-" pad="-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> </devicesets> </library> </libraries> @@ -25195,6 +41059,906 @@ Source: 008-0260-0_E.pdf</description> <part name="FID15" library="UsedComponents" deviceset="FIDUCIAL" device="1X2"/> <part name="D2" library="diode" deviceset="BAT54C" device=""/> <part name="L2" library="microbuilder" deviceset="INDUCTOR" device="_0805" value="10uH"/> +<part name="U7" library="Xilinx_XC7A200TFBG484" deviceset="XC7A200TFBG484" device=""/> +<part name="SUPPLY59" library="supply2" deviceset="GND" device=""/> +<part name="SUPPLY60" library="supply2" deviceset="GND" device=""/> +<part name="SUPPLY61" library="supply2" deviceset="GND" device=""/> +<part name="SUPPLY62" library="supply2" deviceset="GND" device=""/> +<part name="SUPPLY63" library="supply2" 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name="RATED_VOLTAGE" value="16V"/> +<attribute name="TOLERANCE" value="20%"/> +</part> +<part name="C176" library="resistor" deviceset="C-EU" device="C1210" value="47 uF"> +<attribute name="DIELECTRIC" value="X5R"/> +<attribute name="RATED_VOLTAGE" value="16V"/> +<attribute name="TOLERANCE" value="20%"/> +</part> +<part name="C177" library="resistor" deviceset="C-EU" device="C1210" value="47 uF"> +<attribute name="DIELECTRIC" value="X5R"/> +<attribute name="RATED_VOLTAGE" value="16V"/> +<attribute name="TOLERANCE" value="20%"/> +</part> +<part name="C178" library="resistor" deviceset="C-EU" device="C1210" value="47 uF"> +<attribute name="DIELECTRIC" value="X5R"/> +<attribute name="RATED_VOLTAGE" value="16V"/> +<attribute name="TOLERANCE" value="20%"/> +</part> </parts> <sheets> <sheet> @@ -28873,6 +45637,4838 @@ MKM by installing this jumper</text> </net> </nets> </sheet> +<sheet> +<description>Pavel 1-1</description> +<plain> +<text x="-129.54" y="160.02" size="1.778" layer="91">*) Configuration Interface</text> +<text x="-91.44" y="30.48" size="1.778" layer="91">M[2:0] == 3'b001 => Master SPI</text> +<text x="-139.7" y="81.28" size="1.778" layer="91">*) Since VCCO is 3.3V, CFGBVS must be tied High. + +*) Battery is not used + +*) PROG_B is dedicated input -- can be driven by STM32 directly + +*) INIT_B is bi-directional open-drain, must be driven with MOSFET to ground</text> +<text x="-35.56" y="50.8" size="1.778" layer="91">*) "Not DONE" LED, should be of red color</text> +</plain> +<instances> +<instance part="U7" gate="B0" x="-111.76" y="132.08"/> +<instance part="SUPPLY59" gate="GND" x="-101.6" y="106.68"/> +<instance part="R21" gate="G$1" x="-119.38" y="30.48" rot="R90"> +<attribute name="TOLERANCE" x="-119.38" y="30.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY150" gate="GND" x="-119.38" y="17.78"/> +<instance part="SUPPLY151" gate="GND" x="-99.06" y="17.78"/> +<instance part="FRAME8" gate="G$1" x="-149.86" y="-2.54"/> +<instance part="R23" gate="G$1" x="-99.06" y="30.48" rot="R90"> +<attribute name="TOLERANCE" x="-99.06" y="30.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R24" gate="G$1" x="-78.74" y="50.8" rot="R90"> +<attribute name="TOLERANCE" x="-78.74" y="50.8" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R25" gate="G$1" x="0" y="149.86" rot="R90"> +<attribute name="TOLERANCE" x="0" y="149.86" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R26" gate="G$1" x="-10.16" y="149.86" rot="R90"> +<attribute name="TOLERANCE" x="-10.16" y="149.86" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="Q6" gate="G$1" x="0" y="129.54" rot="MR0"/> +<instance part="SUPPLY161" gate="GND" x="-10.16" y="104.14"/> +<instance part="R29" gate="G$1" x="10.16" y="116.84" rot="R90"> +<attribute name="TOLERANCE" x="10.16" y="116.84" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY162" gate="GND" x="10.16" y="104.14"/> +<instance part="LED15" gate="G$1" x="-10.16" y="66.04"/> +<instance part="R33" gate="G$1" x="-10.16" y="76.2" rot="R90"> +<attribute name="TOLERANCE" x="-10.16" y="76.2" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R34" gate="G$1" x="2.54" y="58.42" rot="R180"> +<attribute name="TOLERANCE" x="2.54" y="58.42" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY59" gate="GND" pin="GND"/> +<wire x1="-101.6" y1="109.22" x2="-101.6" y2="149.86" width="0.1524" layer="91"/> +<pinref part="U7" gate="B0" pin="VCCBATT_0"/> +<wire x1="-101.6" y1="149.86" x2="-106.68" y2="149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R21" gate="G$1" pin="1"/> +<pinref part="SUPPLY150" gate="GND" pin="GND"/> +<wire x1="-119.38" y1="25.4" x2="-119.38" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="-99.06" y1="25.4" x2="-99.06" y2="20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY151" gate="GND" pin="GND"/> +<pinref part="R23" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="Q6" gate="G$1" pin="S"/> +<pinref part="SUPPLY161" gate="GND" pin="GND"/> +<wire x1="-5.08" y1="127" x2="-10.16" y2="127" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="127" x2="-10.16" y2="106.68" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R29" gate="G$1" pin="1"/> +<pinref part="SUPPLY162" gate="GND" pin="GND"/> +<wire x1="10.16" y1="111.76" x2="10.16" y2="106.68" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="VCCO_0@0"/> +<wire x1="-106.68" y1="147.32" x2="-96.52" y2="147.32" width="0.1524" layer="91"/> +<pinref part="U7" gate="B0" pin="VCCO_0@1"/> +<wire x1="-96.52" y1="147.32" x2="-76.2" y2="147.32" width="0.1524" layer="91"/> +<wire x1="-106.68" y1="144.78" x2="-96.52" y2="144.78" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="144.78" x2="-96.52" y2="147.32" width="0.1524" layer="91"/> +<junction x="-96.52" y="147.32"/> +<label x="-93.98" y="147.32" size="1.778" layer="95"/> +<pinref part="U7" gate="B0" pin="CFGBVS_0"/> +<wire x1="-106.68" y1="142.24" x2="-96.52" y2="142.24" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="142.24" x2="-96.52" y2="144.78" width="0.1524" layer="91"/> +<junction x="-96.52" y="144.78"/> +</segment> +<segment> +<pinref part="R25" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="160.02" x2="0" y2="160.02" width="0.1524" layer="91"/> +<wire x1="0" y1="154.94" x2="0" y2="160.02" width="0.1524" layer="91"/> +<junction x="0" y="160.02"/> +<pinref part="R26" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="154.94" x2="-10.16" y2="160.02" width="0.1524" layer="91"/> +<junction x="-10.16" y="160.02"/> +<label x="35.56" y="160.02" size="1.778" layer="95" xref="yes"/> +<wire x1="0" y1="160.02" x2="35.56" y2="160.02" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="160.02" x2="-35.56" y2="160.02" width="0.1524" layer="91"/> +<label x="-35.56" y="160.02" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-35.56" y1="83.82" x2="-10.16" y2="83.82" width="0.1524" layer="91"/> +<label x="-35.56" y="83.82" size="1.778" layer="95"/> +<pinref part="R33" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="83.82" x2="35.56" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="81.28" x2="-10.16" y2="83.82" width="0.1524" layer="91"/> +<junction x="-10.16" y="83.82"/> +</segment> +</net> +<net name="FPGA_PROM_SCLK" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="CCLK_0"/> +<wire x1="-106.68" y1="132.08" x2="-71.12" y2="132.08" width="0.1524" layer="91"/> +<label x="-93.98" y="132.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_M2" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="M2_0"/> +<wire x1="-106.68" y1="124.46" x2="-71.12" y2="124.46" width="0.1524" layer="91"/> +<label x="-93.98" y="124.46" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R21" gate="G$1" pin="2"/> +<wire x1="-119.38" y1="35.56" x2="-119.38" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="40.64" x2="-134.62" y2="40.64" width="0.1524" layer="91"/> +<label x="-132.08" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TCK" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="TCK_0"/> +<wire x1="-106.68" y1="121.92" x2="-71.12" y2="121.92" width="0.1524" layer="91"/> +<label x="-93.98" y="121.92" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TDI" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="TDI_0"/> +<wire x1="-106.68" y1="119.38" x2="-71.12" y2="119.38" width="0.1524" layer="91"/> +<label x="-93.98" y="119.38" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TDO" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="TDO_0"/> +<wire x1="-106.68" y1="116.84" x2="-71.12" y2="116.84" width="0.1524" layer="91"/> +<label x="-93.98" y="116.84" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TMS" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="TMS_0"/> +<wire x1="-106.68" y1="114.3" x2="-71.12" y2="114.3" width="0.1524" layer="91"/> +<label x="-93.98" y="114.3" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROGRAM_B" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="PROGRAM_B_0"/> +<wire x1="-106.68" y1="134.62" x2="-71.12" y2="134.62" width="0.1524" layer="91"/> +<label x="-93.98" y="134.62" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R25" gate="G$1" pin="1"/> +<wire x1="0" y1="144.78" x2="0" y2="139.7" width="0.1524" layer="91"/> +<wire x1="0" y1="139.7" x2="35.56" y2="139.7" width="0.1524" layer="91"/> +<label x="35.56" y="139.7" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_DONE_INT" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="DONE_0"/> +<wire x1="-106.68" y1="139.7" x2="-71.12" y2="139.7" width="0.1524" layer="91"/> +<label x="-93.98" y="139.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="LED15" gate="G$1" pin="C"/> +<wire x1="-10.16" y1="60.96" x2="-10.16" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="58.42" x2="-35.56" y2="58.42" width="0.1524" layer="91"/> +<pinref part="R34" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="58.42" x2="-2.54" y2="58.42" width="0.1524" layer="91"/> +<junction x="-10.16" y="58.42"/> +<label x="-35.56" y="58.42" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_M0" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="M0_0"/> +<wire x1="-106.68" y1="129.54" x2="-71.12" y2="129.54" width="0.1524" layer="91"/> +<label x="-93.98" y="129.54" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-93.98" y1="40.64" x2="-78.74" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="40.64" x2="-78.74" y2="45.72" width="0.1524" layer="91"/> +<label x="-91.44" y="40.64" size="1.778" layer="95"/> +<pinref part="R24" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_M1" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="M1_0"/> +<wire x1="-106.68" y1="127" x2="-71.12" y2="127" width="0.1524" layer="91"/> +<label x="-93.98" y="127" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-114.3" y1="40.64" x2="-99.06" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="40.64" x2="-99.06" y2="35.56" width="0.1524" layer="91"/> +<label x="-101.6" y="43.18" size="1.778" layer="95" rot="R180"/> +<pinref part="R23" gate="G$1" pin="2"/> +</segment> +</net> +<net name="VPGA_VCCO_3V3" class="0"> +<segment> +<wire x1="-78.74" y1="55.88" x2="-78.74" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="60.96" x2="-93.98" y2="60.96" width="0.1524" layer="91"/> +<label x="-96.52" y="60.96" size="1.778" layer="95"/> +<pinref part="R24" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_INIT_B_INT" class="0"> +<segment> +<pinref part="U7" gate="B0" pin="INIT_B_0"/> +<wire x1="-106.68" y1="137.16" x2="-71.12" y2="137.16" width="0.1524" layer="91"/> +<label x="-93.98" y="137.16" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R26" gate="G$1" pin="1"/> +<wire x1="-10.16" y1="144.78" x2="-10.16" y2="132.08" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="132.08" x2="-35.56" y2="132.08" width="0.1524" layer="91"/> +<pinref part="Q6" gate="G$1" pin="D"/> +<wire x1="-5.08" y1="132.08" x2="-10.16" y2="132.08" width="0.1524" layer="91"/> +<junction x="-10.16" y="132.08"/> +<label x="-35.56" y="132.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_INIT_B" class="0"> +<segment> +<label x="35.56" y="127" size="1.778" layer="95" xref="yes"/> +<pinref part="Q6" gate="G$1" pin="G"/> +<wire x1="5.08" y1="127" x2="10.16" y2="127" width="0.1524" layer="91"/> +<pinref part="R29" gate="G$1" pin="2"/> +<wire x1="10.16" y1="127" x2="10.16" y2="121.92" width="0.1524" layer="91"/> +<junction x="10.16" y="127"/> +<wire x1="10.16" y1="127" x2="35.56" y2="127" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$34" class="0"> +<segment> +<pinref part="R33" gate="G$1" pin="1"/> +<pinref part="LED15" gate="G$1" pin="A"/> +<wire x1="-10.16" y1="71.12" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_DONE" class="0"> +<segment> +<pinref part="R34" gate="G$1" pin="1"/> +<wire x1="7.62" y1="58.42" x2="35.56" y2="58.42" width="0.1524" layer="91"/> +<label x="35.56" y="58.42" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 1-2</description> +<plain> +<text x="22.86" y="78.74" size="1.778" layer="91">*) Temperature Sensor [NOT USED]</text> +<text x="-35.56" y="78.74" size="1.778" layer="91">*) XADC [NOT USED]</text> +<text x="-139.7" y="81.28" size="1.778" layer="91">*) Transceivers [NOT USED]</text> +</plain> +<instances> +<instance part="U7" gate="B216" x="-119.38" y="-12.7"/> +<instance part="U7" gate="BMGTAVCC" x="-119.38" y="60.96"/> +<instance part="U7" gate="BMGTAVTT" x="-119.38" y="35.56"/> +<instance part="U7" gate="BTDIODE" x="43.18" y="68.58"/> +<instance part="U7" gate="BXADC" x="-33.02" y="63.5"/> +<instance part="SUPPLY60" gate="GND" x="53.34" y="58.42"/> +<instance part="SUPPLY61" gate="GND" x="-22.86" y="48.26"/> +<instance part="SUPPLY62" gate="GND" x="-12.7" y="48.26"/> +<instance part="FRAME9" gate="G$1" x="-160.02" y="-81.28"/> +<instance part="C70" gate="G$1" x="-12.7" y="60.96"> +<attribute name="DIELECTRIC" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U7" gate="BXADC" pin="GNDADC_0"/> +<wire x1="-27.94" y1="55.88" x2="-22.86" y2="55.88" width="0.1524" layer="91"/> +<pinref part="SUPPLY61" gate="GND" pin="GND"/> +<wire x1="-22.86" y1="55.88" x2="-22.86" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U7" gate="BXADC" pin="VREFN_0"/> +<wire x1="-27.94" y1="58.42" x2="-22.86" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="58.42" x2="-22.86" y2="55.88" width="0.1524" layer="91"/> +<junction x="-22.86" y="55.88"/> +<pinref part="U7" gate="BXADC" pin="VREFP_0"/> +<wire x1="-27.94" y1="60.96" x2="-22.86" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="60.96" x2="-22.86" y2="58.42" width="0.1524" layer="91"/> +<junction x="-22.86" y="58.42"/> +</segment> +<segment> +<pinref part="SUPPLY62" gate="GND" pin="GND"/> +<wire x1="-12.7" y1="55.88" x2="-12.7" y2="50.8" width="0.1524" layer="91"/> +<pinref part="C70" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="U7" gate="BTDIODE" pin="DXN_0"/> +<wire x1="48.26" y1="66.04" x2="53.34" y2="66.04" width="0.1524" layer="91"/> +<pinref part="SUPPLY60" gate="GND" pin="GND"/> +<wire x1="53.34" y1="66.04" x2="53.34" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U7" gate="BTDIODE" pin="DXP_0"/> +<wire x1="48.26" y1="68.58" x2="53.34" y2="68.58" width="0.1524" layer="91"/> +<wire x1="53.34" y1="68.58" x2="53.34" y2="66.04" width="0.1524" layer="91"/> +<junction x="53.34" y="66.04"/> +</segment> +</net> +<net name="FPGA_VCCAUX_1V8" class="0"> +<segment> +<pinref part="U7" gate="BXADC" pin="VCCADC_0"/> +<wire x1="-27.94" y1="68.58" x2="-12.7" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="68.58" x2="-12.7" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="68.58" x2="-2.54" y2="68.58" width="0.1524" layer="91"/> +<junction x="-12.7" y="68.58"/> +<label x="-22.86" y="68.58" size="1.778" layer="95"/> +<pinref part="C70" gate="G$1" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 1-3</description> +<plain> +<text x="-20.32" y="50.8" size="1.778" layer="91">*) HOLD feature not used + +*) PROM is write-protected by default, to disable +write protection (such as during firmware update), +jumper must be inserted</text> +</plain> +<instances> +<instance part="IC3" gate="A" x="-50.8" y="36.83"/> +<instance part="SUPPLY147" gate="GND" x="-73.66" y="15.24"/> +<instance part="R9" gate="G$1" x="-73.66" y="53.34" rot="R90"> +<attribute name="TOLERANCE" x="-73.66" y="53.34" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="JP7" gate="A" x="-83.82" y="53.34"/> +<instance part="R20" gate="G$1" x="-83.82" y="27.94" rot="R90"> +<attribute name="TOLERANCE" x="-83.82" y="27.94" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY148" gate="GND" x="-83.82" y="15.24"/> +<instance part="SUPPLY149" gate="GND" x="0" y="15.24"/> +<instance part="FRAME10" gate="G$1" x="-129.54" y="-91.44"/> +<instance part="Q5" gate="G$1" x="-45.72" y="-33.02"/> +<instance part="C110" gate="G$1" x="-76.2" y="-35.56"> +<attribute name="DIELECTRIC" x="-76.2" y="-35.56" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-76.2" y="-35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-76.2" y="-35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY159" gate="GND" x="-60.96" y="-48.26"/> +<instance part="SUPPLY160" gate="GND" x="-76.2" y="-48.26"/> +<instance part="R28" gate="G$1" x="-45.72" y="-17.78" rot="R180"/> +<instance part="SV3" gate="1" x="99.06" y="12.7" rot="R180"/> +<instance part="SUPPLY163" gate="GND" x="86.36" y="-5.08"/> +<instance part="R35" gate="G$1" x="63.5" y="55.88" rot="R90"> +<attribute name="TOLERANCE" x="63.5" y="55.88" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R36" gate="G$1" x="73.66" y="55.88" rot="R90"> +<attribute name="TOLERANCE" x="73.66" y="55.88" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R37" gate="G$1" x="83.82" y="55.88" rot="R90"> +<attribute name="TOLERANCE" x="83.82" y="55.88" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY164" gate="GND" x="60.96" y="-5.08"/> +<instance part="C133" gate="G$1" x="60.96" y="10.16"> +<attribute name="DIELECTRIC" x="60.96" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="60.96" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C134" gate="G$1" x="0" y="30.48"> +<attribute name="DIELECTRIC" x="0" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="0" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="0" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY147" gate="GND" pin="GND"/> +<wire x1="-73.66" y1="17.78" x2="-73.66" y2="35.56" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="VSS"/> +<wire x1="-73.66" y1="35.56" x2="-68.58" y2="35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY148" gate="GND" pin="GND"/> +<pinref part="R20" gate="G$1" pin="1"/> +<wire x1="-83.82" y1="17.78" x2="-83.82" y2="22.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY149" gate="GND" pin="GND"/> +<wire x1="0" y1="17.78" x2="0" y2="25.4" width="0.1524" layer="91"/> +<pinref part="C134" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY159" gate="GND" pin="GND"/> +<wire x1="-60.96" y1="-45.72" x2="-60.96" y2="-38.1" width="0.1524" layer="91"/> +<pinref part="Q5" gate="G$1" pin="GND"/> +<wire x1="-60.96" y1="-38.1" x2="-58.42" y2="-38.1" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C110" gate="G$1" pin="2"/> +<pinref part="SUPPLY160" gate="GND" pin="GND"/> +<wire x1="-76.2" y1="-40.64" x2="-76.2" y2="-45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY163" gate="GND" pin="GND"/> +<wire x1="86.36" y1="-2.54" x2="86.36" y2="2.54" width="0.1524" layer="91"/> +<pinref part="SV3" gate="1" pin="8"/> +<wire x1="86.36" y1="2.54" x2="91.44" y2="2.54" width="0.1524" layer="91"/> +<pinref part="SV3" gate="1" pin="7"/> +<wire x1="91.44" y1="5.08" x2="86.36" y2="5.08" width="0.1524" layer="91"/> +<wire x1="86.36" y1="5.08" x2="86.36" y2="2.54" width="0.1524" layer="91"/> +<junction x="86.36" y="2.54"/> +<pinref part="SV3" gate="1" pin="6"/> +<wire x1="91.44" y1="7.62" x2="86.36" y2="7.62" width="0.1524" layer="91"/> +<wire x1="86.36" y1="7.62" x2="86.36" y2="5.08" width="0.1524" layer="91"/> +<junction x="86.36" y="5.08"/> +</segment> +<segment> +<pinref part="SUPPLY164" gate="GND" pin="GND"/> +<wire x1="60.96" y1="-2.54" x2="60.96" y2="5.08" width="0.1524" layer="91"/> +<pinref part="C133" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<pinref part="R9" gate="G$1" pin="2"/> +<wire x1="-73.66" y1="58.42" x2="-73.66" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="63.5" x2="-83.82" y2="63.5" width="0.1524" layer="91"/> +<label x="-96.52" y="63.5" size="1.778" layer="95"/> +<pinref part="IC3" gate="A" pin="VCC"/> +<wire x1="-83.82" y1="63.5" x2="-99.06" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-31.75" y1="43.18" x2="-25.4" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="43.18" x2="-25.4" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="63.5" x2="-73.66" y2="63.5" width="0.1524" layer="91"/> +<junction x="-73.66" y="63.5"/> +<pinref part="IC3" gate="A" pin="!HOLD!/DQ3"/> +<wire x1="-31.75" y1="40.64" x2="-25.4" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="40.64" x2="-25.4" y2="43.18" width="0.1524" layer="91"/> +<junction x="-25.4" y="43.18"/> +<pinref part="JP7" gate="A" pin="2"/> +<wire x1="-83.82" y1="60.96" x2="-83.82" y2="63.5" width="0.1524" layer="91"/> +<junction x="-83.82" y="63.5"/> +<wire x1="0" y1="40.64" x2="0" y2="33.02" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="40.64" x2="0" y2="40.64" width="0.1524" layer="91"/> +<junction x="-25.4" y="40.64"/> +<pinref part="C134" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="C110" gate="G$1" pin="1"/> +<wire x1="-76.2" y1="-33.02" x2="-76.2" y2="-27.94" width="0.1524" layer="91"/> +<pinref part="Q5" gate="G$1" pin="VCC"/> +<wire x1="-76.2" y1="-27.94" x2="-60.96" y2="-27.94" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="-27.94" x2="-58.42" y2="-27.94" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="-27.94" x2="-81.28" y2="-27.94" width="0.1524" layer="91"/> +<junction x="-76.2" y="-27.94"/> +<label x="-81.28" y="-27.94" size="1.778" layer="95"/> +<pinref part="R28" gate="G$1" pin="2"/> +<wire x1="-50.8" y1="-17.78" x2="-60.96" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="-17.78" x2="-60.96" y2="-27.94" width="0.1524" layer="91"/> +<junction x="-60.96" y="-27.94"/> +</segment> +<segment> +<pinref part="SV3" gate="1" pin="1"/> +<wire x1="91.44" y1="20.32" x2="60.96" y2="20.32" width="0.1524" layer="91"/> +<wire x1="60.96" y1="20.32" x2="55.88" y2="20.32" width="0.1524" layer="91"/> +<wire x1="60.96" y1="12.7" x2="60.96" y2="20.32" width="0.1524" layer="91"/> +<junction x="60.96" y="20.32"/> +<label x="55.88" y="20.32" size="1.778" layer="95"/> +<pinref part="C133" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="R35" gate="G$1" pin="2"/> +<wire x1="63.5" y1="60.96" x2="63.5" y2="66.04" width="0.1524" layer="91"/> +<wire x1="63.5" y1="66.04" x2="73.66" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R37" gate="G$1" pin="2"/> +<wire x1="73.66" y1="66.04" x2="83.82" y2="66.04" width="0.1524" layer="91"/> +<wire x1="83.82" y1="66.04" x2="83.82" y2="60.96" width="0.1524" layer="91"/> +<junction x="83.82" y="66.04"/> +<wire x1="83.82" y1="66.04" x2="109.22" y2="66.04" width="0.1524" layer="91"/> +<label x="86.36" y="66.04" size="1.778" layer="95"/> +<pinref part="R36" gate="G$1" pin="2"/> +<wire x1="73.66" y1="60.96" x2="73.66" y2="66.04" width="0.1524" layer="91"/> +<junction x="73.66" y="66.04"/> +</segment> +</net> +<net name="FPGA_PROM_SCLK" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="C"/> +<wire x1="-31.75" y1="38.1" x2="-10.16" y2="38.1" width="0.1524" layer="91"/> +<label x="-30.48" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_MOSI" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="DQ0"/> +<wire x1="-31.75" y1="35.56" x2="-10.16" y2="35.56" width="0.1524" layer="91"/> +<label x="-30.48" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_CS_N" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="!S"/> +<wire x1="-68.58" y1="43.18" x2="-73.66" y2="43.18" width="0.1524" layer="91"/> +<label x="-109.22" y="43.18" size="1.778" layer="95"/> +<pinref part="R9" gate="G$1" pin="1"/> +<wire x1="-73.66" y1="43.18" x2="-109.22" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="43.18" x2="-73.66" y2="48.26" width="0.1524" layer="91"/> +<junction x="-73.66" y="43.18"/> +</segment> +</net> +<net name="FPGA_PROM_MISO" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="DQ1"/> +<wire x1="-68.58" y1="40.64" x2="-109.22" y2="40.64" width="0.1524" layer="91"/> +<label x="-109.22" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_W_N" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="!W!/VPP/DQ2"/> +<wire x1="-68.58" y1="38.1" x2="-83.82" y2="38.1" width="0.1524" layer="91"/> +<label x="-109.22" y="38.1" size="1.778" layer="95"/> +<pinref part="R20" gate="G$1" pin="2"/> +<wire x1="-83.82" y1="38.1" x2="-109.22" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="33.02" x2="-83.82" y2="38.1" width="0.1524" layer="91"/> +<junction x="-83.82" y="38.1"/> +<pinref part="JP7" gate="A" pin="1"/> +<wire x1="-83.82" y1="45.72" x2="-83.82" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_GCLK" class="0"> +<segment> +<wire x1="-33.02" y1="-33.02" x2="-2.54" y2="-33.02" width="0.1524" layer="91"/> +<label x="-30.48" y="-33.02" size="1.778" layer="95"/> +<pinref part="Q5" gate="G$1" pin="FO"/> +</segment> +</net> +<net name="FPGA_JTAG_TCK" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="2"/> +<wire x1="91.44" y1="17.78" x2="71.12" y2="17.78" width="0.1524" layer="91"/> +<label x="71.12" y="17.78" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R37" gate="G$1" pin="1"/> +<wire x1="83.82" y1="50.8" x2="83.82" y2="45.72" width="0.1524" layer="91"/> +<wire x1="83.82" y1="45.72" x2="109.22" y2="45.72" width="0.1524" layer="91"/> +<label x="88.9" y="45.72" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TDI" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="4"/> +<wire x1="91.44" y1="12.7" x2="71.12" y2="12.7" width="0.1524" layer="91"/> +<label x="71.12" y="12.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R35" gate="G$1" pin="1"/> +<wire x1="63.5" y1="50.8" x2="63.5" y2="35.56" width="0.1524" layer="91"/> +<wire x1="63.5" y1="35.56" x2="109.22" y2="35.56" width="0.1524" layer="91"/> +<label x="88.9" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TDO" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="5"/> +<wire x1="91.44" y1="10.16" x2="71.12" y2="10.16" width="0.1524" layer="91"/> +<label x="71.12" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TMS" class="0"> +<segment> +<pinref part="SV3" gate="1" pin="3"/> +<wire x1="91.44" y1="15.24" x2="71.12" y2="15.24" width="0.1524" layer="91"/> +<label x="71.12" y="15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R36" gate="G$1" pin="1"/> +<wire x1="73.66" y1="50.8" x2="73.66" y2="40.64" width="0.1524" layer="91"/> +<wire x1="73.66" y1="40.64" x2="109.22" y2="40.64" width="0.1524" layer="91"/> +<label x="88.9" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$33" class="0"> +<segment> +<pinref part="Q5" gate="G$1" pin="OE"/> +<wire x1="-33.02" y1="-27.94" x2="-30.48" y2="-27.94" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-27.94" x2="-30.48" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R28" gate="G$1" pin="1"/> +<wire x1="-30.48" y1="-17.78" x2="-40.64" y2="-17.78" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 2-1</description> +<plain> +<text x="-119.38" y="83.82" size="1.778" layer="91">*) Middle Right Bank</text> +<text x="-35.56" y="86.36" size="1.778" layer="91">*) Upper Left Bank</text> +<text x="-96.52" y="66.04" size="1.778" layer="91">*) Completely unused banks +still must be powered</text> +<text x="-7.62" y="68.58" size="1.778" layer="91">*) Completely unused banks +still must be powered</text> +</plain> +<instances> +<instance part="U7" gate="B15" x="-109.22" y="5.08"/> +<instance part="U7" gate="B35" x="-20.32" y="7.62"/> +<instance part="FRAME13" gate="G$1" x="-147.32" y="-81.28"/> +</instances> +<busses> +</busses> +<nets> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<wire x1="-104.14" y1="73.66" x2="-99.06" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="73.66" x2="-99.06" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="71.12" x2="-99.06" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="68.58" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="66.04" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<junction x="-99.06" y="66.04"/> +<wire x1="-104.14" y1="68.58" x2="-99.06" y2="68.58" width="0.1524" layer="91"/> +<junction x="-99.06" y="68.58"/> +<wire x1="-104.14" y1="71.12" x2="-99.06" y2="71.12" width="0.1524" layer="91"/> +<junction x="-99.06" y="71.12"/> +<junction x="-99.06" y="73.66"/> +<wire x1="-99.06" y1="73.66" x2="-73.66" y2="73.66" width="0.1524" layer="91"/> +<label x="-96.52" y="73.66" size="1.778" layer="95"/> +<pinref part="U7" gate="B15" pin="VCCO_15@5"/> +<wire x1="-104.14" y1="60.96" x2="-99.06" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="60.96" x2="-99.06" y2="63.5" width="0.1524" layer="91"/> +<pinref part="U7" gate="B15" pin="VCCO_15@4"/> +<wire x1="-99.06" y1="63.5" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="63.5" x2="-99.06" y2="63.5" width="0.1524" layer="91"/> +<junction x="-99.06" y="63.5"/> +<pinref part="U7" gate="B15" pin="VCCO_15@0"/> +<pinref part="U7" gate="B15" pin="VCCO_15@1"/> +<pinref part="U7" gate="B15" pin="VCCO_15@2"/> +<pinref part="U7" gate="B15" pin="VCCO_15@3"/> +</segment> +<segment> +<wire x1="-15.24" y1="76.2" x2="-10.16" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="76.2" x2="-10.16" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="73.66" x2="-10.16" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="71.12" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="68.58" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<junction x="-10.16" y="68.58"/> +<wire x1="-15.24" y1="71.12" x2="-10.16" y2="71.12" width="0.1524" layer="91"/> +<junction x="-10.16" y="71.12"/> +<wire x1="-15.24" y1="73.66" x2="-10.16" y2="73.66" width="0.1524" layer="91"/> +<junction x="-10.16" y="73.66"/> +<junction x="-10.16" y="76.2"/> +<wire x1="-10.16" y1="76.2" x2="15.24" y2="76.2" width="0.1524" layer="91"/> +<label x="-7.62" y="76.2" size="1.778" layer="95"/> +<wire x1="-15.24" y1="63.5" x2="-10.16" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="63.5" x2="-10.16" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="66.04" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="66.04" x2="-10.16" y2="66.04" width="0.1524" layer="91"/> +<junction x="-10.16" y="66.04"/> +<pinref part="U7" gate="B35" pin="VCCO_35@0"/> +<pinref part="U7" gate="B35" pin="VCCO_35@1"/> +<pinref part="U7" gate="B35" pin="VCCO_35@2"/> +<pinref part="U7" gate="B35" pin="VCCO_35@3"/> +<pinref part="U7" gate="B35" pin="VCCO_35@4"/> +<pinref part="U7" gate="B35" pin="VCCO_35@5"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 2-2</description> +<plain> +<text x="30.48" y="63.5" size="1.778" layer="91">*) Bottom Bank</text> +<text x="-106.68" y="73.66" size="1.778" layer="91">*) Lower Left Bank</text> +<text x="81.28" y="38.1" size="1.778" layer="91"><-- FMC_A[...] signals can be swapped</text> +<text x="81.28" y="-30.48" size="1.778" layer="91"><-- FMC_CLK signal _MUST_ go +into either W11 or V13 (i.e. into +one of the two positive (master) +sides of the two available +MRCC differential pairs)</text> +<text x="-53.34" y="45.72" size="1.778" layer="91"><-- FMC_D[...] signals can be swapped</text> +<text x="-38.1" y="-35.56" size="1.778" layer="91"><-- FMC_* control signals can be swapped</text> +</plain> +<instances> +<instance part="U7" gate="B13" x="43.18" y="2.54"/> +<instance part="U7" gate="B34" x="-91.44" y="-7.62"/> +<instance part="FRAME12" gate="G$1" x="-124.46" y="-93.98"/> +</instances> +<busses> +<bus name="FPGA_FMC_A[0..25]"> +<segment> +<wire x1="78.74" y1="43.18" x2="93.98" y2="43.18" width="0.762" layer="92"/> +<wire x1="78.74" y1="43.18" x2="78.74" y2="-27.94" width="0.762" layer="92"/> +<label x="78.74" y="43.18" size="1.778" layer="95"/> +</segment> +</bus> +<bus name="FPGA_FMC_D[0..31]"> +<segment> +<wire x1="-55.88" y1="-33.02" x2="-55.88" y2="50.8" width="0.762" layer="92"/> +<wire x1="-55.88" y1="50.8" x2="-40.64" y2="50.8" width="0.762" layer="92"/> +<label x="-55.88" y="50.8" size="1.778" layer="95"/> +</segment> +</bus> +</busses> +<nets> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="VCCO_34@5"/> +<wire x1="-86.36" y1="48.26" x2="-81.28" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="48.26" x2="-81.28" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U7" gate="B34" pin="VCCO_34@0"/> +<wire x1="-81.28" y1="50.8" x2="-81.28" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="53.34" x2="-81.28" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="55.88" x2="-81.28" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="58.42" x2="-81.28" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="60.96" x2="-86.36" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U7" gate="B34" pin="VCCO_34@1"/> +<wire x1="-86.36" y1="58.42" x2="-81.28" y2="58.42" width="0.1524" layer="91"/> +<junction x="-81.28" y="58.42"/> +<pinref part="U7" gate="B34" pin="VCCO_34@2"/> +<wire x1="-86.36" y1="55.88" x2="-81.28" y2="55.88" width="0.1524" layer="91"/> +<junction x="-81.28" y="55.88"/> +<pinref part="U7" gate="B34" pin="VCCO_34@3"/> +<wire x1="-86.36" y1="53.34" x2="-81.28" y2="53.34" width="0.1524" layer="91"/> +<junction x="-81.28" y="53.34"/> +<pinref part="U7" gate="B34" pin="VCCO_34@4"/> +<wire x1="-86.36" y1="50.8" x2="-81.28" y2="50.8" width="0.1524" layer="91"/> +<junction x="-81.28" y="50.8"/> +<junction x="-81.28" y="60.96"/> +<wire x1="-81.28" y1="60.96" x2="-55.88" y2="60.96" width="0.1524" layer="91"/> +<label x="-78.74" y="60.96" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="48.26" y1="50.8" x2="53.34" y2="50.8" width="0.1524" layer="91"/> +<label x="53.34" y="50.8" size="1.778" layer="95"/> +<pinref part="U7" gate="B13" pin="VCCO_13@0"/> +<pinref part="U7" gate="B13" pin="VCCO_13@1"/> +<wire x1="53.34" y1="50.8" x2="78.74" y2="50.8" width="0.1524" layer="91"/> +<wire x1="48.26" y1="48.26" x2="53.34" y2="48.26" width="0.1524" layer="91"/> +<wire x1="53.34" y1="48.26" x2="53.34" y2="50.8" width="0.1524" layer="91"/> +<junction x="53.34" y="50.8"/> +<pinref part="U7" gate="B13" pin="VCCO_13@2"/> +<wire x1="48.26" y1="45.72" x2="53.34" y2="45.72" width="0.1524" layer="91"/> +<wire x1="53.34" y1="45.72" x2="53.34" y2="48.26" width="0.1524" layer="91"/> +<junction x="53.34" y="48.26"/> +<pinref part="U7" gate="B13" pin="VCCO_13@3"/> +<wire x1="48.26" y1="43.18" x2="53.34" y2="43.18" width="0.1524" layer="91"/> +<wire x1="53.34" y1="43.18" x2="53.34" y2="45.72" width="0.1524" layer="91"/> +<junction x="53.34" y="45.72"/> +<pinref part="U7" gate="B13" pin="VCCO_13@4"/> +<wire x1="48.26" y1="40.64" x2="53.34" y2="40.64" width="0.1524" layer="91"/> +<wire x1="53.34" y1="40.64" x2="53.34" y2="43.18" width="0.1524" layer="91"/> +<junction x="53.34" y="43.18"/> +</segment> +</net> +<net name="FPGA_FMC_A0" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_0_13"/> +<wire x1="48.26" y1="38.1" x2="78.74" y2="38.1" width="0.1524" layer="91"/> +<label x="53.34" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A1" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L1P_T0_13"/> +<wire x1="48.26" y1="35.56" x2="78.74" y2="35.56" width="0.1524" layer="91"/> +<label x="53.34" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A2" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L1N_T0_13"/> +<wire x1="48.26" y1="33.02" x2="78.74" y2="33.02" width="0.1524" layer="91"/> +<label x="53.34" y="33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A3" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L2P_T0_13"/> +<wire x1="48.26" y1="30.48" x2="78.74" y2="30.48" width="0.1524" layer="91"/> +<label x="53.34" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A4" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L2N_T0_13"/> +<wire x1="48.26" y1="27.94" x2="78.74" y2="27.94" width="0.1524" layer="91"/> +<label x="53.34" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A5" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L3P_T0_DQS_13"/> +<wire x1="48.26" y1="25.4" x2="78.74" y2="25.4" width="0.1524" layer="91"/> +<label x="53.34" y="25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A6" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L3N_T0_DQS_13"/> +<wire x1="48.26" y1="22.86" x2="78.74" y2="22.86" width="0.1524" layer="91"/> +<label x="53.34" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A7" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L4P_T0_13"/> +<wire x1="48.26" y1="20.32" x2="78.74" y2="20.32" width="0.1524" layer="91"/> +<label x="53.34" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A8" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L4N_T0_13"/> +<wire x1="48.26" y1="17.78" x2="78.74" y2="17.78" width="0.1524" layer="91"/> +<label x="53.34" y="17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A9" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L5P_T0_13"/> +<wire x1="48.26" y1="15.24" x2="78.74" y2="15.24" width="0.1524" layer="91"/> +<label x="53.34" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A10" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L5N_T0_13"/> +<wire x1="48.26" y1="12.7" x2="78.74" y2="12.7" width="0.1524" layer="91"/> +<label x="53.34" y="12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A11" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L6P_T0_13"/> +<wire x1="48.26" y1="10.16" x2="78.74" y2="10.16" width="0.1524" layer="91"/> +<label x="53.34" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A12" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L6N_T0_VREF_13"/> +<wire x1="48.26" y1="7.62" x2="78.74" y2="7.62" width="0.1524" layer="91"/> +<label x="53.34" y="7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A13" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L7P_T1_13"/> +<wire x1="48.26" y1="5.08" x2="78.74" y2="5.08" width="0.1524" layer="91"/> +<label x="53.34" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A14" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L7N_T1_13"/> +<wire x1="48.26" y1="2.54" x2="78.74" y2="2.54" width="0.1524" layer="91"/> +<label x="53.34" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A15" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L8P_T1_13"/> +<wire x1="48.26" y1="0" x2="78.74" y2="0" width="0.1524" layer="91"/> +<label x="53.34" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A16" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L8N_T1_13"/> +<wire x1="48.26" y1="-2.54" x2="78.74" y2="-2.54" width="0.1524" layer="91"/> +<label x="53.34" y="-2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A17" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L9P_T1_DQS_13"/> +<wire x1="48.26" y1="-5.08" x2="78.74" y2="-5.08" width="0.1524" layer="91"/> +<label x="53.34" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A18" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L9N_T1_DQS_13"/> +<wire x1="48.26" y1="-7.62" x2="78.74" y2="-7.62" width="0.1524" layer="91"/> +<label x="53.34" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A19" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L10P_T1_13"/> +<wire x1="48.26" y1="-10.16" x2="78.74" y2="-10.16" width="0.1524" layer="91"/> +<label x="53.34" y="-10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A20" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L10N_T1_13"/> +<wire x1="48.26" y1="-12.7" x2="78.74" y2="-12.7" width="0.1524" layer="91"/> +<label x="53.34" y="-12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A21" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L11P_T1_SRCC_13"/> +<wire x1="48.26" y1="-15.24" x2="78.74" y2="-15.24" width="0.1524" layer="91"/> +<label x="53.34" y="-15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A22" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L11N_T1_SRCC_13"/> +<wire x1="48.26" y1="-17.78" x2="78.74" y2="-17.78" width="0.1524" layer="91"/> +<label x="53.34" y="-17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A25" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L13N_T2_MRCC_13"/> +<wire x1="48.26" y1="-27.94" x2="78.74" y2="-27.94" width="0.1524" layer="91"/> +<label x="53.34" y="-27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A23" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L12N_T1_MRCC_13"/> +<wire x1="48.26" y1="-22.86" x2="78.74" y2="-22.86" width="0.1524" layer="91"/> +<label x="53.34" y="-22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_A24" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L13P_T2_MRCC_13"/> +<wire x1="48.26" y1="-25.4" x2="78.74" y2="-25.4" width="0.1524" layer="91"/> +<label x="53.34" y="-25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_CLK" class="0"> +<segment> +<pinref part="U7" gate="B13" pin="IO_L12P_T1_MRCC_13"/> +<wire x1="48.26" y1="-20.32" x2="73.66" y2="-20.32" width="0.1524" layer="91"/> +<label x="53.34" y="-20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D0" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_0_34"/> +<wire x1="-86.36" y1="45.72" x2="-55.88" y2="45.72" width="0.1524" layer="91"/> +<label x="-81.28" y="45.72" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D1" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L1P_T0_34"/> +<wire x1="-86.36" y1="43.18" x2="-55.88" y2="43.18" width="0.1524" layer="91"/> +<label x="-81.28" y="43.18" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D2" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L1N_T0_34"/> +<wire x1="-86.36" y1="40.64" x2="-55.88" y2="40.64" width="0.1524" layer="91"/> +<label x="-81.28" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D3" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L2P_T0_34"/> +<wire x1="-86.36" y1="38.1" x2="-55.88" y2="38.1" width="0.1524" layer="91"/> +<label x="-81.28" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D4" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L2N_T0_34"/> +<wire x1="-86.36" y1="35.56" x2="-55.88" y2="35.56" width="0.1524" layer="91"/> +<label x="-81.28" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D5" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L3P_T0_DQS_34"/> +<wire x1="-86.36" y1="33.02" x2="-55.88" y2="33.02" width="0.1524" layer="91"/> +<label x="-81.28" y="33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D6" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L3N_T0_DQS_34"/> +<wire x1="-86.36" y1="30.48" x2="-55.88" y2="30.48" width="0.1524" layer="91"/> +<label x="-81.28" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D7" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L4P_T0_34"/> +<wire x1="-86.36" y1="27.94" x2="-55.88" y2="27.94" width="0.1524" layer="91"/> +<label x="-81.28" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D8" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L4N_T0_34"/> +<wire x1="-86.36" y1="25.4" x2="-55.88" y2="25.4" width="0.1524" layer="91"/> +<label x="-81.28" y="25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D9" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L5P_T0_34"/> +<wire x1="-86.36" y1="22.86" x2="-55.88" y2="22.86" width="0.1524" layer="91"/> +<label x="-81.28" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D10" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L5N_T0_34"/> +<wire x1="-86.36" y1="20.32" x2="-55.88" y2="20.32" width="0.1524" layer="91"/> +<label x="-81.28" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D11" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L6P_T0_34"/> +<wire x1="-86.36" y1="17.78" x2="-55.88" y2="17.78" width="0.1524" layer="91"/> +<label x="-81.28" y="17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D12" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L6N_T0_VREF_34"/> +<wire x1="-86.36" y1="15.24" x2="-55.88" y2="15.24" width="0.1524" layer="91"/> +<label x="-81.28" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D13" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L7P_T1_34"/> +<wire x1="-86.36" y1="12.7" x2="-55.88" y2="12.7" width="0.1524" layer="91"/> +<label x="-81.28" y="12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D14" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L7N_T1_34"/> +<wire x1="-86.36" y1="10.16" x2="-55.88" y2="10.16" width="0.1524" layer="91"/> +<label x="-81.28" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D15" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L8P_T1_34"/> +<wire x1="-86.36" y1="7.62" x2="-55.88" y2="7.62" width="0.1524" layer="91"/> +<label x="-81.28" y="7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D16" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L8N_T1_34"/> +<wire x1="-86.36" y1="5.08" x2="-55.88" y2="5.08" width="0.1524" layer="91"/> +<label x="-81.28" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D17" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L9P_T1_DQS_34"/> +<wire x1="-86.36" y1="2.54" x2="-55.88" y2="2.54" width="0.1524" layer="91"/> +<label x="-81.28" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D18" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L9N_T1_DQS_34"/> +<wire x1="-86.36" y1="0" x2="-55.88" y2="0" width="0.1524" layer="91"/> +<label x="-81.28" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D19" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L10P_T1_34"/> +<wire x1="-86.36" y1="-2.54" x2="-55.88" y2="-2.54" width="0.1524" layer="91"/> +<label x="-81.28" y="-2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D20" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L10N_T1_34"/> +<wire x1="-86.36" y1="-5.08" x2="-55.88" y2="-5.08" width="0.1524" layer="91"/> +<label x="-81.28" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D21" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L11P_T1_SRCC_34"/> +<wire x1="-86.36" y1="-7.62" x2="-55.88" y2="-7.62" width="0.1524" layer="91"/> +<label x="-81.28" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D22" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L11N_T1_SRCC_34"/> +<wire x1="-86.36" y1="-10.16" x2="-55.88" y2="-10.16" width="0.1524" layer="91"/> +<label x="-81.28" y="-10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D23" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L12P_T1_MRCC_34"/> +<wire x1="-86.36" y1="-12.7" x2="-55.88" y2="-12.7" width="0.1524" layer="91"/> +<label x="-81.28" y="-12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D24" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L12N_T1_MRCC_34"/> +<wire x1="-86.36" y1="-15.24" x2="-55.88" y2="-15.24" width="0.1524" layer="91"/> +<label x="-81.28" y="-15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D25" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L13P_T2_MRCC_34"/> +<wire x1="-86.36" y1="-17.78" x2="-55.88" y2="-17.78" width="0.1524" layer="91"/> +<label x="-81.28" y="-17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D26" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L13N_T2_MRCC_34"/> +<wire x1="-86.36" y1="-20.32" x2="-55.88" y2="-20.32" width="0.1524" layer="91"/> +<label x="-81.28" y="-20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D27" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L14P_T2_SRCC_34"/> +<wire x1="-86.36" y1="-22.86" x2="-55.88" y2="-22.86" width="0.1524" layer="91"/> +<label x="-81.28" y="-22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D28" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L14N_T2_SRCC_34"/> +<wire x1="-86.36" y1="-25.4" x2="-55.88" y2="-25.4" width="0.1524" layer="91"/> +<label x="-81.28" y="-25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D29" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L15P_T2_DQS_34"/> +<wire x1="-86.36" y1="-27.94" x2="-55.88" y2="-27.94" width="0.1524" layer="91"/> +<label x="-81.28" y="-27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D30" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L15N_T2_DQS_34"/> +<wire x1="-86.36" y1="-30.48" x2="-55.88" y2="-30.48" width="0.1524" layer="91"/> +<label x="-81.28" y="-30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_D31" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L16P_T2_34"/> +<wire x1="-86.36" y1="-33.02" x2="-55.88" y2="-33.02" width="0.1524" layer="91"/> +<label x="-81.28" y="-33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_FMC_NE1" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L16N_T2_34"/> +<wire x1="-86.36" y1="-35.56" x2="-60.96" y2="-35.56" width="0.1524" layer="91"/> +<label x="-60.96" y="-35.56" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_FMC_NL" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L17P_T2_34"/> +<wire x1="-86.36" y1="-38.1" x2="-60.96" y2="-38.1" width="0.1524" layer="91"/> +<label x="-60.96" y="-38.1" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_FMC_NOE" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L17N_T2_34"/> +<wire x1="-86.36" y1="-40.64" x2="-60.96" y2="-40.64" width="0.1524" layer="91"/> +<label x="-60.96" y="-40.64" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_FMC_NWAIT" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L18P_T2_34"/> +<wire x1="-86.36" y1="-43.18" x2="-60.96" y2="-43.18" width="0.1524" layer="91"/> +<label x="-60.96" y="-43.18" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_FMC_NWE" class="0"> +<segment> +<pinref part="U7" gate="B34" pin="IO_L18N_T2_34"/> +<wire x1="-86.36" y1="-45.72" x2="-60.96" y2="-45.72" width="0.1524" layer="91"/> +<label x="-60.96" y="-45.72" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 2-3</description> +<plain> +<text x="-27.94" y="83.82" size="1.778" layer="91">*) FPGA Power Subsystem -- AUX and I/O</text> +<text x="58.42" y="58.42" size="1.778" layer="91">*) VCCAUX = 0.75V x (1 + 205 / 147) = 1.796V + +*) VCCO = 0.75V x (1 + 205 / 59) = 3.356 + +*) Minimal load current is 2 mA: +1.8V / 470 Ohm = ~4mA +3.3V / 470 Ohm = ~7mA + +*) Light-load mode is enabled +</text> +</plain> +<instances> +<instance part="FRAME11" gate="G$1" x="-139.7" y="-83.82"/> +<instance part="SUPPLY165" gate="GND" x="-73.66" y="15.24"/> +<instance part="SUPPLY166" gate="GND" x="-63.5" y="15.24"/> +<instance part="SUPPLY167" gate="GND" x="-93.98" y="15.24"/> +<instance part="C87" gate="G$1" x="-119.38" y="55.88"> +<attribute name="DIELECTRIC" x="-119.38" y="55.88" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-119.38" y="55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-119.38" y="55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY168" gate="GND" x="-119.38" y="43.18"/> +<instance part="R38" gate="G$1" x="-104.14" y="25.4" rot="R90"> +<attribute name="TOLERANCE" x="-104.14" y="25.4" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY169" gate="GND" x="-104.14" y="15.24"/> +<instance part="R39" gate="G$1" x="-106.68" y="55.88" rot="R90"> +<attribute name="TOLERANCE" x="-106.68" y="55.88" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R40" gate="G$1" x="-38.1" y="58.42" rot="R90"> +<attribute name="TOLERANCE" x="-38.1" y="58.42" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R41" gate="G$1" x="-38.1" y="43.18" rot="R90"> +<attribute name="TOLERANCE" x="-38.1" y="43.18" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="U$5" gate="G$1" x="-68.58" y="48.26"/> +<instance part="SUPPLY170" gate="GND" x="-38.1" y="33.02"/> +<instance part="SUPPLY171" gate="GND" x="-20.32" y="33.02"/> +<instance part="R42" gate="G$1" x="-7.62" y="45.72" rot="R90"> +<attribute name="TOLERANCE" x="-7.62" y="45.72" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY172" gate="GND" x="-7.62" y="33.02"/> +<instance part="R43" gate="G$1" x="0" y="66.04"/> +<instance part="SUPPLY173" gate="GND" x="-73.66" y="-66.04"/> +<instance part="SUPPLY174" gate="GND" x="-63.5" y="-66.04"/> +<instance part="SUPPLY175" gate="GND" x="-93.98" y="-66.04"/> +<instance part="C91" gate="G$1" x="-119.38" y="-25.4"> +<attribute name="DIELECTRIC" x="-119.38" y="-25.4" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-119.38" y="-25.4" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-119.38" y="-25.4" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY176" gate="GND" x="-119.38" y="-38.1"/> +<instance part="R44" gate="G$1" x="-104.14" y="-55.88" rot="R90"> +<attribute name="TOLERANCE" x="-104.14" y="-55.88" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY177" gate="GND" x="-104.14" y="-66.04"/> +<instance part="R45" gate="G$1" x="-106.68" y="-25.4" rot="R90"> +<attribute name="TOLERANCE" x="-106.68" y="-25.4" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R46" gate="G$1" x="-38.1" y="-22.86" rot="R90"> +<attribute name="TOLERANCE" x="-38.1" y="-22.86" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R47" gate="G$1" x="-38.1" y="-38.1" rot="R90"> +<attribute name="TOLERANCE" x="-38.1" y="-38.1" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="U$6" gate="G$1" x="-68.58" y="-33.02"/> +<instance part="SUPPLY178" gate="GND" x="-38.1" y="-48.26"/> +<instance part="SUPPLY179" gate="GND" x="-20.32" y="-48.26"/> +<instance part="R48" gate="G$1" x="-7.62" y="-35.56" rot="R90"> +<attribute name="TOLERANCE" x="-7.62" y="-35.56" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY180" gate="GND" x="-7.62" y="-48.26"/> +<instance part="R49" gate="G$1" x="0" y="-15.24"/> +<instance part="C115" gate="G$1" x="-93.98" y="25.4"> +<attribute name="RATED_VOLTAGE" x="-93.98" y="25.4" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-93.98" y="25.4" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-93.98" y="25.4" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C116" gate="G$1" x="-93.98" y="-55.88"> +<attribute name="RATED_VOLTAGE" x="-93.98" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-93.98" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-93.98" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C131" gate="G$1" x="-30.48" y="-20.32"> +<attribute name="DIELECTRIC" x="-30.48" y="-20.32" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="-20.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="-20.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C132" gate="G$1" x="-30.48" y="60.96"> +<attribute name="DIELECTRIC" x="-30.48" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C174" gate="G$1" x="-20.32" y="48.26"> +<attribute name="DIELECTRIC" x="-20.32" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-20.32" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-20.32" y="48.26" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C175" gate="G$1" x="-20.32" y="-33.02"> +<attribute name="DIELECTRIC" x="-20.32" y="-33.02" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-20.32" y="-33.02" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-20.32" y="-33.02" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY165" gate="GND" pin="GND"/> +<wire x1="-73.66" y1="17.78" x2="-73.66" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="AGND"/> +</segment> +<segment> +<pinref part="SUPPLY166" gate="GND" pin="GND"/> +<wire x1="-63.5" y1="17.78" x2="-63.5" y2="20.32" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="PGND"/> +</segment> +<segment> +<pinref part="SUPPLY167" gate="GND" pin="GND"/> +<wire x1="-93.98" y1="20.32" x2="-93.98" y2="17.78" width="0.1524" layer="91"/> +<pinref part="C115" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="C87" gate="G$1" pin="2"/> +<pinref part="SUPPLY168" gate="GND" pin="GND"/> +<wire x1="-119.38" y1="50.8" x2="-119.38" y2="45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY169" gate="GND" pin="GND"/> +<pinref part="R38" gate="G$1" pin="1"/> +<wire x1="-104.14" y1="17.78" x2="-104.14" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY170" gate="GND" pin="GND"/> +<pinref part="R41" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="35.56" x2="-38.1" y2="38.1" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY171" gate="GND" pin="GND"/> +<wire x1="-20.32" y1="35.56" x2="-20.32" y2="43.18" width="0.1524" layer="91"/> +<pinref part="C174" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY172" gate="GND" pin="GND"/> +<pinref part="R42" gate="G$1" pin="1"/> +<wire x1="-7.62" y1="35.56" x2="-7.62" y2="40.64" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY173" gate="GND" pin="GND"/> +<wire x1="-73.66" y1="-63.5" x2="-73.66" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="AGND"/> +</segment> +<segment> +<pinref part="SUPPLY174" gate="GND" pin="GND"/> +<wire x1="-63.5" y1="-63.5" x2="-63.5" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="PGND"/> +</segment> +<segment> +<pinref part="SUPPLY175" gate="GND" pin="GND"/> +<wire x1="-93.98" y1="-60.96" x2="-93.98" y2="-63.5" width="0.1524" layer="91"/> +<pinref part="C116" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="C91" gate="G$1" pin="2"/> +<pinref part="SUPPLY176" gate="GND" pin="GND"/> +<wire x1="-119.38" y1="-30.48" x2="-119.38" y2="-35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY177" gate="GND" pin="GND"/> +<pinref part="R44" gate="G$1" pin="1"/> +<wire x1="-104.14" y1="-63.5" x2="-104.14" y2="-60.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY178" gate="GND" pin="GND"/> +<pinref part="R47" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-45.72" x2="-38.1" y2="-43.18" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY179" gate="GND" pin="GND"/> +<wire x1="-20.32" y1="-45.72" x2="-20.32" y2="-38.1" width="0.1524" layer="91"/> +<pinref part="C175" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY180" gate="GND" pin="GND"/> +<pinref part="R48" gate="G$1" pin="1"/> +<wire x1="-7.62" y1="-45.72" x2="-7.62" y2="-40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_VCCAUX_1V8" class="0"> +<segment> +<pinref part="R43" gate="G$1" pin="2"/> +<wire x1="5.08" y1="66.04" x2="30.48" y2="66.04" width="0.1524" layer="91"/> +<label x="7.62" y="66.04" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<pinref part="R49" gate="G$1" pin="2"/> +<wire x1="5.08" y1="-15.24" x2="30.48" y2="-15.24" width="0.1524" layer="91"/> +<label x="7.62" y="-15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$35" class="0"> +<segment> +<wire x1="-93.98" y1="27.94" x2="-93.98" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="30.48" x2="-88.9" y2="30.48" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="SS"/> +<pinref part="C115" gate="G$1" pin="1"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<wire x1="-88.9" y1="66.04" x2="-93.98" y2="66.04" width="0.1524" layer="91"/> +<label x="-124.46" y="66.04" size="1.778" layer="95"/> +<wire x1="-93.98" y1="66.04" x2="-106.68" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-106.68" y1="66.04" x2="-119.38" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="66.04" x2="-124.46" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="60.96" x2="-93.98" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="60.96" x2="-93.98" y2="66.04" width="0.1524" layer="91"/> +<junction x="-93.98" y="66.04"/> +<pinref part="C87" gate="G$1" pin="1"/> +<wire x1="-119.38" y1="58.42" x2="-119.38" y2="66.04" width="0.1524" layer="91"/> +<junction x="-119.38" y="66.04"/> +<pinref part="R39" gate="G$1" pin="2"/> +<wire x1="-106.68" y1="60.96" x2="-106.68" y2="66.04" width="0.1524" layer="91"/> +<junction x="-106.68" y="66.04"/> +<pinref part="U$5" gate="G$1" pin="PVIN"/> +<pinref part="U$5" gate="G$1" pin="AVIN"/> +</segment> +<segment> +<wire x1="-88.9" y1="-15.24" x2="-93.98" y2="-15.24" width="0.1524" layer="91"/> +<label x="-124.46" y="-15.24" size="1.778" layer="95"/> +<wire x1="-93.98" y1="-15.24" x2="-106.68" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-106.68" y1="-15.24" x2="-119.38" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="-15.24" x2="-124.46" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="-20.32" x2="-93.98" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-20.32" x2="-93.98" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-93.98" y="-15.24"/> +<pinref part="C91" gate="G$1" pin="1"/> +<wire x1="-119.38" y1="-22.86" x2="-119.38" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-119.38" y="-15.24"/> +<pinref part="R45" gate="G$1" pin="2"/> +<wire x1="-106.68" y1="-20.32" x2="-106.68" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-106.68" y="-15.24"/> +<pinref part="U$6" gate="G$1" pin="PVIN"/> +<pinref part="U$6" gate="G$1" pin="AVIN"/> +</segment> +</net> +<net name="PWR_ENA_VCCAUX" class="0"> +<segment> +<wire x1="-88.9" y1="55.88" x2="-99.06" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="55.88" x2="-99.06" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="76.2" x2="-124.46" y2="76.2" width="0.1524" layer="91"/> +<label x="-124.46" y="76.2" size="1.778" layer="95"/> +<pinref part="U$5" gate="G$1" pin="ENABLE"/> +</segment> +</net> +<net name="N$36" class="0"> +<segment> +<pinref part="R38" gate="G$1" pin="2"/> +<wire x1="-104.14" y1="30.48" x2="-104.14" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="40.64" x2="-88.9" y2="40.64" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="RLLM"/> +</segment> +</net> +<net name="N$37" class="0"> +<segment> +<wire x1="-88.9" y1="45.72" x2="-106.68" y2="45.72" width="0.1524" layer="91"/> +<pinref part="R39" gate="G$1" pin="1"/> +<wire x1="-106.68" y1="45.72" x2="-106.68" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="LLM/SYNC"/> +</segment> +</net> +<net name="N$38" class="0"> +<segment> +<pinref part="U$5" gate="G$1" pin="VOUT"/> +<wire x1="-48.26" y1="66.04" x2="-38.1" y2="66.04" width="0.1524" layer="91"/> +<pinref part="R40" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="66.04" x2="-38.1" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="63.5" x2="-30.48" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="66.04" x2="-38.1" y2="66.04" width="0.1524" layer="91"/> +<junction x="-38.1" y="66.04"/> +<wire x1="-20.32" y1="50.8" x2="-20.32" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="66.04" x2="-30.48" y2="66.04" width="0.1524" layer="91"/> +<junction x="-30.48" y="66.04"/> +<pinref part="R42" gate="G$1" pin="2"/> +<wire x1="-7.62" y1="50.8" x2="-7.62" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="66.04" x2="-20.32" y2="66.04" width="0.1524" layer="91"/> +<junction x="-20.32" y="66.04"/> +<pinref part="R43" gate="G$1" pin="1"/> +<wire x1="-5.08" y1="66.04" x2="-7.62" y2="66.04" width="0.1524" layer="91"/> +<junction x="-7.62" y="66.04"/> +<pinref part="C132" gate="G$1" pin="1"/> +<pinref part="C174" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$39" class="0"> +<segment> +<pinref part="R40" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="53.34" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U$5" gate="G$1" pin="VFB"/> +<wire x1="-38.1" y1="50.8" x2="-48.26" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="55.88" x2="-30.48" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="50.8" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> +<junction x="-38.1" y="50.8"/> +<pinref part="R41" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="48.26" x2="-38.1" y2="50.8" width="0.1524" layer="91"/> +<pinref part="C132" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$40" class="0"> +<segment> +<wire x1="-93.98" y1="-53.34" x2="-93.98" y2="-50.8" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-50.8" x2="-88.9" y2="-50.8" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="SS"/> +<pinref part="C116" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$41" class="0"> +<segment> +<pinref part="R44" gate="G$1" pin="2"/> +<wire x1="-104.14" y1="-50.8" x2="-104.14" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-40.64" x2="-88.9" y2="-40.64" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="RLLM"/> +</segment> +</net> +<net name="N$42" class="0"> +<segment> +<wire x1="-88.9" y1="-35.56" x2="-106.68" y2="-35.56" width="0.1524" layer="91"/> +<pinref part="R45" gate="G$1" pin="1"/> +<wire x1="-106.68" y1="-35.56" x2="-106.68" y2="-30.48" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="LLM/SYNC"/> +</segment> +</net> +<net name="N$43" class="0"> +<segment> +<pinref part="U$6" gate="G$1" pin="VOUT"/> +<wire x1="-48.26" y1="-15.24" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="R46" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="-15.24" x2="-38.1" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-17.78" x2="-30.48" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-15.24" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-38.1" y="-15.24"/> +<wire x1="-20.32" y1="-30.48" x2="-20.32" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-15.24" x2="-30.48" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-30.48" y="-15.24"/> +<pinref part="R48" gate="G$1" pin="2"/> +<wire x1="-7.62" y1="-30.48" x2="-7.62" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="-15.24" x2="-20.32" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-20.32" y="-15.24"/> +<pinref part="R49" gate="G$1" pin="1"/> +<wire x1="-5.08" y1="-15.24" x2="-7.62" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-7.62" y="-15.24"/> +<pinref part="C131" gate="G$1" pin="1"/> +<pinref part="C175" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$44" class="0"> +<segment> +<pinref part="R46" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-27.94" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> +<pinref part="U$6" gate="G$1" pin="VFB"/> +<wire x1="-38.1" y1="-30.48" x2="-48.26" y2="-30.48" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-25.4" x2="-30.48" y2="-30.48" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-30.48" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> +<junction x="-38.1" y="-30.48"/> +<pinref part="R47" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="-33.02" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> +<pinref part="C131" gate="G$1" pin="2"/> +</segment> +</net> +<net name="PWR_ENA_VCCO" class="0"> +<segment> +<wire x1="-88.9" y1="-25.4" x2="-99.06" y2="-25.4" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-25.4" x2="-99.06" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-5.08" x2="-124.46" y2="-5.08" width="0.1524" layer="91"/> +<label x="-124.46" y="-5.08" size="1.778" layer="95"/> +<pinref part="U$6" gate="G$1" pin="ENABLE"/> +</segment> +</net> +<net name="POK_VCCAUX" class="0"> +<segment> +<pinref part="U$5" gate="G$1" pin="POK"/> +<wire x1="-48.26" y1="30.48" x2="-45.72" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="30.48" x2="-45.72" y2="45.72" width="0.1524" layer="91"/> +<label x="-45.72" y="33.02" size="1.778" layer="95" rot="R90"/> +</segment> +</net> +<net name="POK_VCCO" class="0"> +<segment> +<pinref part="U$6" gate="G$1" pin="POK"/> +<wire x1="-48.26" y1="-50.8" x2="-45.72" y2="-50.8" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="-50.8" x2="-45.72" y2="-35.56" width="0.1524" layer="91"/> +<label x="-45.72" y="-48.26" size="1.778" layer="95" rot="R90"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 3-1</description> +<plain> +<text x="-81.28" y="96.52" size="1.778" layer="91">*) Upper Right Bank</text> +<text x="-55.88" y="5.08" size="1.778" layer="91">*) FPGA_GCLK signal _MUST_ go into either D17 or C18 +(i.e. into one of the two positive (master) sides +of the two available MRCC differential pairs)</text> +<text x="-55.88" y="0" size="1.778" layer="91">*) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped</text> +<text x="83.82" y="99.06" size="1.778" layer="91">*) Signals, that are allowed to be swapped, can be be swapped +with each other and/or moved to different pins within their bank.</text> +</plain> +<instances> +<instance part="U7" gate="B16" x="-63.5" y="20.32"/> +<instance part="FRAME14" gate="G$1" x="-99.06" y="-68.58"/> +<instance part="SV1" gate="G$1" x="116.84" y="73.66" rot="R180"/> +<instance part="SUPPLY153" gate="GND" x="76.2" y="55.88"/> +<instance part="SUPPLY154" gate="GND" x="106.68" y="55.88"/> +<instance part="SUPPLY155" gate="GND" x="127" y="55.88"/> +<instance part="SV2" gate="G$1" x="116.84" y="30.48" rot="R180"/> +<instance part="SUPPLY156" gate="GND" x="76.2" y="12.7"/> +<instance part="SUPPLY157" gate="GND" x="106.68" y="12.7"/> +<instance part="SUPPLY158" gate="GND" x="127" y="12.7"/> +<instance part="C135" gate="G$1" x="76.2" y="71.12"> +<attribute name="DIELECTRIC" x="76.2" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="76.2" y="71.12" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="76.2" y="71.12" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C136" gate="G$1" x="76.2" y="27.94"> +<attribute name="DIELECTRIC" x="76.2" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="76.2" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="76.2" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY153" gate="GND" pin="GND"/> +<wire x1="76.2" y1="58.42" x2="76.2" y2="66.04" width="0.1524" layer="91"/> +<pinref part="C135" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY154" gate="GND" pin="GND"/> +<wire x1="106.68" y1="58.42" x2="106.68" y2="68.58" width="0.1524" layer="91"/> +<pinref part="SV1" gate="G$1" pin="11"/> +<wire x1="106.68" y1="68.58" x2="109.22" y2="68.58" width="0.1524" layer="91"/> +<pinref part="SV1" gate="G$1" pin="5"/> +<wire x1="109.22" y1="76.2" x2="106.68" y2="76.2" width="0.1524" layer="91"/> +<wire x1="106.68" y1="76.2" x2="106.68" y2="68.58" width="0.1524" layer="91"/> +<junction x="106.68" y="68.58"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="12"/> +<wire x1="124.46" y1="68.58" x2="127" y2="68.58" width="0.1524" layer="91"/> +<pinref part="SUPPLY155" gate="GND" pin="GND"/> +<wire x1="127" y1="68.58" x2="127" y2="58.42" width="0.1524" layer="91"/> +<pinref part="SV1" gate="G$1" pin="6"/> +<wire x1="124.46" y1="76.2" x2="127" y2="76.2" width="0.1524" layer="91"/> +<wire x1="127" y1="76.2" x2="127" y2="68.58" width="0.1524" layer="91"/> +<junction x="127" y="68.58"/> +</segment> +<segment> +<pinref part="SUPPLY156" gate="GND" pin="GND"/> +<wire x1="76.2" y1="15.24" x2="76.2" y2="22.86" width="0.1524" layer="91"/> +<pinref part="C136" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY157" gate="GND" pin="GND"/> +<wire x1="106.68" y1="15.24" x2="106.68" y2="25.4" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="11"/> +<wire x1="106.68" y1="25.4" x2="109.22" y2="25.4" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="5"/> +<wire x1="109.22" y1="33.02" x2="106.68" y2="33.02" width="0.1524" layer="91"/> +<wire x1="106.68" y1="33.02" x2="106.68" y2="25.4" width="0.1524" layer="91"/> +<junction x="106.68" y="25.4"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="12"/> +<wire x1="124.46" y1="25.4" x2="127" y2="25.4" width="0.1524" layer="91"/> +<pinref part="SUPPLY158" gate="GND" pin="GND"/> +<wire x1="127" y1="25.4" x2="127" y2="15.24" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="6"/> +<wire x1="124.46" y1="33.02" x2="127" y2="33.02" width="0.1524" layer="91"/> +<wire x1="127" y1="33.02" x2="127" y2="25.4" width="0.1524" layer="91"/> +<junction x="127" y="25.4"/> +</segment> +</net> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<wire x1="-58.42" y1="88.9" x2="-53.34" y2="88.9" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="88.9" x2="-53.34" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="86.36" x2="-53.34" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="83.82" x2="-53.34" y2="81.28" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="81.28" x2="-53.34" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="78.74" x2="-58.42" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-58.42" y1="81.28" x2="-53.34" y2="81.28" width="0.1524" layer="91"/> +<junction x="-53.34" y="81.28"/> +<wire x1="-58.42" y1="83.82" x2="-53.34" y2="83.82" width="0.1524" layer="91"/> +<junction x="-53.34" y="83.82"/> +<wire x1="-58.42" y1="86.36" x2="-53.34" y2="86.36" width="0.1524" layer="91"/> +<junction x="-53.34" y="86.36"/> +<junction x="-53.34" y="88.9"/> +<wire x1="-53.34" y1="88.9" x2="-27.94" y2="88.9" width="0.1524" layer="91"/> +<label x="-50.8" y="88.9" size="1.778" layer="95"/> +<pinref part="U7" gate="B16" pin="VCCO_16@5"/> +<wire x1="-58.42" y1="76.2" x2="-53.34" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="76.2" x2="-53.34" y2="78.74" width="0.1524" layer="91"/> +<junction x="-53.34" y="78.74"/> +<pinref part="U7" gate="B16" pin="VCCO_16@4"/> +<pinref part="U7" gate="B16" pin="VCCO_16@3"/> +<pinref part="U7" gate="B16" pin="VCCO_16@2"/> +<pinref part="U7" gate="B16" pin="VCCO_16@1"/> +<pinref part="U7" gate="B16" pin="VCCO_16@0"/> +</segment> +<segment> +<label x="71.12" y="86.36" size="1.778" layer="95"/> +<wire x1="106.68" y1="86.36" x2="76.2" y2="86.36" width="0.1524" layer="91"/> +<wire x1="76.2" y1="86.36" x2="71.12" y2="86.36" width="0.1524" layer="91"/> +<wire x1="76.2" y1="73.66" x2="76.2" y2="86.36" width="0.1524" layer="91"/> +<junction x="76.2" y="86.36"/> +<pinref part="SV1" gate="G$1" pin="3"/> +<wire x1="109.22" y1="78.74" x2="106.68" y2="78.74" width="0.1524" layer="91"/> +<wire x1="106.68" y1="78.74" x2="106.68" y2="81.28" width="0.1524" layer="91"/> +<junction x="106.68" y="86.36"/> +<pinref part="SV1" gate="G$1" pin="2"/> +<wire x1="106.68" y1="81.28" x2="106.68" y2="86.36" width="0.1524" layer="91"/> +<wire x1="124.46" y1="81.28" x2="127" y2="81.28" width="0.1524" layer="91"/> +<wire x1="127" y1="81.28" x2="127" y2="86.36" width="0.1524" layer="91"/> +<wire x1="127" y1="86.36" x2="106.68" y2="86.36" width="0.1524" layer="91"/> +<pinref part="SV1" gate="G$1" pin="4"/> +<wire x1="124.46" y1="78.74" x2="127" y2="78.74" width="0.1524" layer="91"/> +<wire x1="127" y1="78.74" x2="127" y2="81.28" width="0.1524" layer="91"/> +<junction x="127" y="81.28"/> +<pinref part="SV1" gate="G$1" pin="1"/> +<wire x1="109.22" y1="81.28" x2="106.68" y2="81.28" width="0.1524" layer="91"/> +<junction x="106.68" y="81.28"/> +<pinref part="C135" gate="G$1" pin="1"/> +</segment> +<segment> +<label x="71.12" y="43.18" size="1.778" layer="95"/> +<wire x1="106.68" y1="43.18" x2="76.2" y2="43.18" width="0.1524" layer="91"/> +<wire x1="76.2" y1="43.18" x2="71.12" y2="43.18" width="0.1524" layer="91"/> +<wire x1="76.2" y1="30.48" x2="76.2" y2="43.18" width="0.1524" layer="91"/> +<junction x="76.2" y="43.18"/> +<pinref part="SV2" gate="G$1" pin="3"/> +<wire x1="109.22" y1="35.56" x2="106.68" y2="35.56" width="0.1524" layer="91"/> +<wire x1="106.68" y1="35.56" x2="106.68" y2="38.1" width="0.1524" layer="91"/> +<junction x="106.68" y="43.18"/> +<pinref part="SV2" gate="G$1" pin="2"/> +<wire x1="106.68" y1="38.1" x2="106.68" y2="43.18" width="0.1524" layer="91"/> +<wire x1="124.46" y1="38.1" x2="127" y2="38.1" width="0.1524" layer="91"/> +<wire x1="127" y1="38.1" x2="127" y2="43.18" width="0.1524" layer="91"/> +<wire x1="127" y1="43.18" x2="106.68" y2="43.18" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="4"/> +<wire x1="124.46" y1="35.56" x2="127" y2="35.56" width="0.1524" layer="91"/> +<wire x1="127" y1="35.56" x2="127" y2="38.1" width="0.1524" layer="91"/> +<junction x="127" y="38.1"/> +<pinref part="SV2" gate="G$1" pin="1"/> +<wire x1="109.22" y1="38.1" x2="106.68" y2="38.1" width="0.1524" layer="91"/> +<junction x="106.68" y="38.1"/> +<pinref part="C136" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_GPIO_TAMPER_0" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_0_16"/> +<wire x1="-58.42" y1="73.66" x2="-27.94" y2="73.66" width="0.1524" layer="91"/> +<label x="-27.94" y="73.66" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_TAMPER_1" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L1P_T0_16"/> +<wire x1="-58.42" y1="71.12" x2="-27.94" y2="71.12" width="0.1524" layer="91"/> +<label x="-27.94" y="71.12" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_0" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L1N_T0_16"/> +<wire x1="-58.42" y1="68.58" x2="-27.94" y2="68.58" width="0.1524" layer="91"/> +<label x="-27.94" y="68.58" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_1" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L2P_T0_16"/> +<wire x1="-58.42" y1="66.04" x2="-27.94" y2="66.04" width="0.1524" layer="91"/> +<label x="-27.94" y="66.04" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_2" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L2N_T0_16"/> +<wire x1="-58.42" y1="63.5" x2="-27.94" y2="63.5" width="0.1524" layer="91"/> +<label x="-27.94" y="63.5" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_3" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L3P_T0_DQS_16"/> +<wire x1="-58.42" y1="60.96" x2="-27.94" y2="60.96" width="0.1524" layer="91"/> +<label x="-27.94" y="60.96" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_A_0" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L3N_T0_DQS_16"/> +<wire x1="-58.42" y1="58.42" x2="-27.94" y2="58.42" width="0.1524" layer="91"/> +<label x="-53.34" y="58.42" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="7"/> +<wire x1="109.22" y1="73.66" x2="86.36" y2="73.66" width="0.1524" layer="91"/> +<label x="86.36" y="73.66" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_1" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L4P_T0_16"/> +<wire x1="-58.42" y1="55.88" x2="-27.94" y2="55.88" width="0.1524" layer="91"/> +<label x="-53.34" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="8"/> +<wire x1="124.46" y1="73.66" x2="147.32" y2="73.66" width="0.1524" layer="91"/> +<label x="129.54" y="73.66" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_2" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L4N_T0_16"/> +<wire x1="-58.42" y1="53.34" x2="-27.94" y2="53.34" width="0.1524" layer="91"/> +<label x="-53.34" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="9"/> +<wire x1="109.22" y1="71.12" x2="86.36" y2="71.12" width="0.1524" layer="91"/> +<label x="86.36" y="71.12" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_3" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L5P_T0_16"/> +<wire x1="-58.42" y1="50.8" x2="-27.94" y2="50.8" width="0.1524" layer="91"/> +<label x="-53.34" y="50.8" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="10"/> +<wire x1="124.46" y1="71.12" x2="147.32" y2="71.12" width="0.1524" layer="91"/> +<label x="129.54" y="71.12" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_4" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L5N_T0_16"/> +<wire x1="-58.42" y1="48.26" x2="-27.94" y2="48.26" width="0.1524" layer="91"/> +<label x="-53.34" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="13"/> +<wire x1="109.22" y1="66.04" x2="86.36" y2="66.04" width="0.1524" layer="91"/> +<label x="86.36" y="66.04" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_5" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L6P_T0_16"/> +<wire x1="-58.42" y1="45.72" x2="-27.94" y2="45.72" width="0.1524" layer="91"/> +<label x="-53.34" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="14"/> +<wire x1="124.46" y1="66.04" x2="147.32" y2="66.04" width="0.1524" layer="91"/> +<label x="129.54" y="66.04" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_6" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L6N_T0_VREF_16"/> +<wire x1="-58.42" y1="43.18" x2="-27.94" y2="43.18" width="0.1524" layer="91"/> +<label x="-53.34" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="15"/> +<wire x1="109.22" y1="63.5" x2="86.36" y2="63.5" width="0.1524" layer="91"/> +<label x="86.36" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_7" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L7P_T1_16"/> +<wire x1="-58.42" y1="40.64" x2="-27.94" y2="40.64" width="0.1524" layer="91"/> +<label x="-53.34" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="G$1" pin="16"/> +<wire x1="124.46" y1="63.5" x2="147.32" y2="63.5" width="0.1524" layer="91"/> +<label x="129.54" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_0" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L7N_T1_16"/> +<wire x1="-58.42" y1="38.1" x2="-27.94" y2="38.1" width="0.1524" layer="91"/> +<label x="-53.34" y="38.1" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="7"/> +<wire x1="109.22" y1="30.48" x2="86.36" y2="30.48" width="0.1524" layer="91"/> +<label x="86.36" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_1" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L8P_T1_16"/> +<wire x1="-58.42" y1="35.56" x2="-27.94" y2="35.56" width="0.1524" layer="91"/> +<label x="-53.34" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="8"/> +<wire x1="124.46" y1="30.48" x2="147.32" y2="30.48" width="0.1524" layer="91"/> +<label x="129.54" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_2" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L8N_T1_16"/> +<wire x1="-58.42" y1="33.02" x2="-27.94" y2="33.02" width="0.1524" layer="91"/> +<label x="-53.34" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="9"/> +<wire x1="109.22" y1="27.94" x2="86.36" y2="27.94" width="0.1524" layer="91"/> +<label x="86.36" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_3" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L9P_T1_DQS_16"/> +<wire x1="-58.42" y1="30.48" x2="-27.94" y2="30.48" width="0.1524" layer="91"/> +<label x="-53.34" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="10"/> +<wire x1="124.46" y1="27.94" x2="147.32" y2="27.94" width="0.1524" layer="91"/> +<label x="129.54" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_4" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L9N_T1_DQS_16"/> +<wire x1="-58.42" y1="27.94" x2="-27.94" y2="27.94" width="0.1524" layer="91"/> +<label x="-53.34" y="27.94" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="13"/> +<wire x1="109.22" y1="22.86" x2="86.36" y2="22.86" width="0.1524" layer="91"/> +<label x="86.36" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_5" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L10P_T1_16"/> +<wire x1="-58.42" y1="25.4" x2="-27.94" y2="25.4" width="0.1524" layer="91"/> +<label x="-53.34" y="25.4" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="14"/> +<wire x1="124.46" y1="22.86" x2="147.32" y2="22.86" width="0.1524" layer="91"/> +<label x="129.54" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_6" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L10N_T1_16"/> +<wire x1="-58.42" y1="22.86" x2="-27.94" y2="22.86" width="0.1524" layer="91"/> +<label x="-53.34" y="22.86" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="15"/> +<wire x1="109.22" y1="20.32" x2="86.36" y2="20.32" width="0.1524" layer="91"/> +<label x="86.36" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_7" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L11P_T1_SRCC_16"/> +<wire x1="-58.42" y1="20.32" x2="-27.94" y2="20.32" width="0.1524" layer="91"/> +<label x="-53.34" y="20.32" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="16"/> +<wire x1="124.46" y1="20.32" x2="147.32" y2="20.32" width="0.1524" layer="91"/> +<label x="129.54" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GCLK" class="0"> +<segment> +<pinref part="U7" gate="B16" pin="IO_L12P_T1_MRCC_16"/> +<wire x1="-58.42" y1="15.24" x2="-27.94" y2="15.24" width="0.1524" layer="91"/> +<label x="-53.34" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 3-2</description> +<plain> +<text x="-129.54" y="78.74" size="1.778" layer="91">*) Lower Right Bank</text> +<text x="-88.9" y="-17.78" size="1.778" layer="91">DIGITIZED_NOISE signal should go into +either W19 or Y18 (i.e. into one of the two +positive (master) sides of the two available +MRCC differential pairs)</text> +<text x="30.48" y="81.28" size="1.778" layer="91">*) Signals, that are allowed to be swapped, can be be swapped +with each other and/or moved to different pins within their bank.</text> +<text x="-76.2" y="22.86" size="1.778" layer="91"><-- FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped</text> +<text x="-91.44" y="60.96" size="1.778" layer="91"><-- Disable pull-ups on all pins during configuration</text> +</plain> +<instances> +<instance part="U7" gate="B14" x="-114.3" y="0"/> +<instance part="FRAME15" gate="G$1" x="-152.4" y="-86.36"/> +<instance part="R27" gate="G$1" x="-96.52" y="60.96" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="60.96" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="FPGA_VCCO_3V3" class="0"> +<segment> +<wire x1="-109.22" y1="68.58" x2="-104.14" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="68.58" x2="-104.14" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="66.04" x2="-104.14" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="63.5" x2="-104.14" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="60.96" x2="-104.14" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="58.42" x2="-109.22" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-109.22" y1="60.96" x2="-104.14" y2="60.96" width="0.1524" layer="91"/> +<junction x="-104.14" y="60.96"/> +<wire x1="-109.22" y1="63.5" x2="-104.14" y2="63.5" width="0.1524" layer="91"/> +<junction x="-104.14" y="63.5"/> +<wire x1="-109.22" y1="66.04" x2="-104.14" y2="66.04" width="0.1524" layer="91"/> +<junction x="-104.14" y="66.04"/> +<junction x="-104.14" y="68.58"/> +<wire x1="-104.14" y1="68.58" x2="-96.52" y2="68.58" width="0.1524" layer="91"/> +<label x="-101.6" y="68.58" size="1.778" layer="95"/> +<wire x1="-96.52" y1="68.58" x2="-78.74" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="55.88" x2="-104.14" y2="58.42" width="0.1524" layer="91"/> +<junction x="-104.14" y="58.42"/> +<pinref part="U7" gate="B14" pin="VCCO_14@5"/> +<wire x1="-109.22" y1="55.88" x2="-104.14" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U7" gate="B14" pin="VCCO_14@4"/> +<pinref part="U7" gate="B14" pin="VCCO_14@3"/> +<pinref part="U7" gate="B14" pin="VCCO_14@2"/> +<pinref part="U7" gate="B14" pin="VCCO_14@1"/> +<pinref part="U7" gate="B14" pin="VCCO_14@0"/> +<pinref part="R27" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="66.04" x2="-96.52" y2="68.58" width="0.1524" layer="91"/> +<junction x="-96.52" y="68.58"/> +</segment> +</net> +<net name="FPGA_PROM_MOSI" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L1P_T0_D00_MOSI_14"/> +<wire x1="-109.22" y1="50.8" x2="-68.58" y2="50.8" width="0.1524" layer="91"/> +<label x="-91.44" y="50.8" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_MISO" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L1N_T0_D01_DIN_14"/> +<wire x1="-109.22" y1="48.26" x2="-68.58" y2="48.26" width="0.1524" layer="91"/> +<label x="-91.44" y="48.26" size="1.778" layer="95"/> +</segment> +</net> +<net name="DIGITIZED_NOISE" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L12P_T1_MRCC_14"/> +<wire x1="-109.22" y1="-5.08" x2="-78.74" y2="-5.08" width="0.1524" layer="91"/> +<label x="-78.74" y="-5.08" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_2" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L7N_T1_D10_14"/> +<wire x1="-109.22" y1="17.78" x2="-78.74" y2="17.78" width="0.1524" layer="91"/> +<label x="-104.14" y="17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_3" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L8P_T1_D11_14"/> +<wire x1="-109.22" y1="15.24" x2="-78.74" y2="15.24" width="0.1524" layer="91"/> +<label x="-104.14" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_CS_B" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L6P_T0_FCS_B_14"/> +<wire x1="-109.22" y1="25.4" x2="-78.74" y2="25.4" width="0.1524" layer="91"/> +<label x="-104.14" y="25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_0" class="0"> +<segment> +<pinref part="U7" gate="B14" pin="IO_L6N_T0_D08_VREF_14"/> +<wire x1="-109.22" y1="22.86" x2="-78.74" y2="22.86" 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- CORE & BRAM</text> +<text x="-106.68" y="76.2" size="1.778" layer="91">*) Ground Pins</text> +</plain> +<instances> +<instance part="U7" gate="BGNDA" x="-116.84" y="5.08"/> +<instance part="U7" gate="BGNDB" x="-71.12" y="5.08"/> +<instance part="U7" gate="BVCCAUX" x="60.96" y="55.88"/> +<instance part="U7" gate="BVCCBRAM" x="-15.24" y="58.42"/> +<instance part="U7" gate="BVCCINT" x="-15.24" y="22.86" rot="MR180"/> +<instance part="SUPPLY63" gate="GND" x="-106.68" y="-58.42"/> +<instance part="SUPPLY64" gate="GND" x="-60.96" y="-55.88"/> +<instance part="FRAME16" gate="G$1" x="-147.32" y="-81.28"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U7" gate="BGNDA" pin="GND@43"/> +<wire x1="-111.76" y1="-50.8" x2="-106.68" y2="-50.8" width="0.1524" layer="91"/> +<pinref part="SUPPLY63" gate="GND" pin="GND"/> +<wire x1="-106.68" y1="-50.8" x2="-106.68" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="U7" gate="BGNDA" pin="GND@42"/> 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layer="91"/> +<junction x="-5.08" y="38.1"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@10"/> +<wire x1="-10.16" y1="33.02" x2="-5.08" y2="33.02" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="33.02" x2="-5.08" y2="35.56" width="0.1524" layer="91"/> +<junction x="-5.08" y="35.56"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@9"/> +<wire x1="-10.16" y1="30.48" x2="-5.08" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="30.48" x2="-5.08" y2="33.02" width="0.1524" layer="91"/> +<junction x="-5.08" y="33.02"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@8"/> +<wire x1="-10.16" y1="27.94" x2="-5.08" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="27.94" x2="-5.08" y2="30.48" width="0.1524" layer="91"/> +<junction x="-5.08" y="30.48"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@7"/> +<wire x1="-10.16" y1="25.4" x2="-5.08" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="25.4" x2="-5.08" y2="27.94" width="0.1524" layer="91"/> +<junction x="-5.08" y="27.94"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@0"/> +<wire x1="-10.16" y1="7.62" x2="-5.08" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="7.62" x2="-5.08" y2="10.16" width="0.1524" layer="91"/> +<junction x="-5.08" y="25.4"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@6"/> +<wire x1="-5.08" y1="10.16" x2="-5.08" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="12.7" x2="-5.08" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="15.24" x2="-5.08" y2="17.78" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="17.78" x2="-5.08" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="20.32" x2="-5.08" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="22.86" x2="-5.08" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="22.86" x2="-5.08" y2="22.86" width="0.1524" layer="91"/> +<junction x="-5.08" y="22.86"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@5"/> +<wire x1="-10.16" y1="20.32" x2="-5.08" y2="20.32" width="0.1524" layer="91"/> +<junction x="-5.08" y="20.32"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@4"/> +<wire x1="-10.16" y1="17.78" x2="-5.08" y2="17.78" width="0.1524" layer="91"/> +<junction x="-5.08" y="17.78"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@3"/> +<wire x1="-10.16" y1="15.24" x2="-5.08" y2="15.24" width="0.1524" layer="91"/> +<junction x="-5.08" y="15.24"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@2"/> +<wire x1="-10.16" y1="12.7" x2="-5.08" y2="12.7" width="0.1524" layer="91"/> +<junction x="-5.08" y="12.7"/> +<pinref part="U7" gate="BVCCINT" pin="VCCINT@1"/> +<wire x1="-10.16" y1="10.16" x2="-5.08" y2="10.16" width="0.1524" layer="91"/> +<junction x="-5.08" y="10.16"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 4-1</description> +<plain> +<text x="66.04" y="58.42" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA package +<-- Place large 47 uF and 330 uF caps not far from the BGA package + +<-- Distribute smaller caps evenly under the BGA package +<-- Distribute larger caps evenly around the BGA package</text> +<text x="-40.64" y="86.36" size="1.778" layer="91">*) Decoupling capacitors for VCCINT and VCCBRAM</text> +<text x="55.88" y="-22.86" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA package +<-- Place large 47 uF caps not far from the BGA package + +<-- Try to place smaller caps next to FPGA balls</text> +<text x="-40.64" y="2.54" size="1.778" layer="91">*) Decoupling capacitors for VCCAUX</text> +</plain> +<instances> +<instance part="C65" gate="G$1" x="-78.74" y="73.66"> +<attribute name="DIELECTRIC" x="-78.74" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY65" gate="GND" x="-78.74" y="63.5"/> +<instance part="SUPPLY66" gate="GND" x="-66.04" y="63.5"/> +<instance part="SUPPLY67" gate="GND" x="-17.78" y="40.64"/> +<instance part="SUPPLY68" gate="GND" x="-5.08" y="40.64"/> +<instance part="SUPPLY69" gate="GND" x="7.62" y="40.64"/> +<instance part="SUPPLY70" gate="GND" x="20.32" y="40.64"/> +<instance part="SUPPLY71" gate="GND" x="33.02" y="40.64"/> +<instance part="SUPPLY72" gate="GND" x="45.72" y="40.64"/> +<instance part="C66" gate="G$1" x="-17.78" y="73.66"> +<attribute name="DIELECTRIC" x="-17.78" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-17.78" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-17.78" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY73" gate="GND" x="-17.78" y="63.5"/> +<instance part="SUPPLY74" gate="GND" x="-5.08" y="63.5"/> +<instance part="SUPPLY75" gate="GND" x="7.62" y="63.5"/> +<instance part="SUPPLY76" gate="GND" x="20.32" y="63.5"/> +<instance part="SUPPLY77" gate="GND" x="33.02" y="63.5"/> +<instance part="SUPPLY78" gate="GND" x="45.72" y="63.5"/> +<instance part="SUPPLY79" gate="GND" x="-48.26" y="63.5"/> +<instance part="SUPPLY80" gate="GND" x="-35.56" y="63.5"/> +<instance part="SUPPLY81" gate="GND" x="-40.64" y="40.64"/> +<instance part="SUPPLY82" gate="GND" x="-53.34" y="40.64"/> +<instance part="SUPPLY83" gate="GND" x="-66.04" y="40.64"/> +<instance part="SUPPLY84" gate="GND" x="-78.74" y="40.64"/> +<instance part="SUPPLY85" gate="GND" x="-40.64" y="17.78"/> +<instance part="SUPPLY86" gate="GND" x="-53.34" y="17.78"/> +<instance part="SUPPLY87" gate="GND" x="-66.04" y="17.78"/> +<instance part="C67" gate="G$1" x="-78.74" y="27.94"> +<attribute name="DIELECTRIC" x="-78.74" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY88" gate="GND" x="-78.74" y="17.78"/> +<instance part="SUPPLY89" gate="GND" x="10.16" y="17.78"/> +<instance part="SUPPLY90" gate="GND" x="-2.54" y="17.78"/> +<instance part="SUPPLY91" gate="GND" x="-15.24" y="17.78"/> +<instance part="SUPPLY92" gate="GND" x="-27.94" y="17.78"/> +<instance part="SUPPLY93" gate="GND" x="60.96" y="17.78"/> +<instance part="SUPPLY94" gate="GND" x="48.26" y="17.78"/> +<instance part="SUPPLY95" gate="GND" x="35.56" y="17.78"/> +<instance part="SUPPLY96" gate="GND" x="22.86" y="17.78"/> +<instance part="SUPPLY97" gate="GND" x="73.66" y="17.78"/> +<instance part="SUPPLY98" gate="GND" x="-71.12" y="-22.86"/> +<instance part="SUPPLY99" gate="GND" x="-53.34" y="-22.86"/> +<instance part="SUPPLY100" gate="GND" x="-40.64" y="-22.86"/> +<instance part="SUPPLY101" gate="GND" x="-27.94" y="-22.86"/> +<instance part="SUPPLY102" gate="GND" x="-10.16" y="-22.86"/> +<instance part="SUPPLY103" gate="GND" x="2.54" y="-22.86"/> +<instance part="SUPPLY104" gate="GND" x="15.24" y="-22.86"/> +<instance part="SUPPLY105" gate="GND" x="27.94" y="-22.86"/> +<instance part="SUPPLY106" gate="GND" x="40.64" y="-22.86"/> +<instance part="FRAME18" gate="G$1" x="-116.84" y="-78.74"/> +<instance part="C68" gate="G$1" x="-48.26" y="73.66"> +<attribute name="DIELECTRIC" x="-48.26" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-48.26" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-48.26" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C69" gate="G$1" x="-66.04" y="73.66"> +<attribute name="DIELECTRIC" x="-66.04" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C71" gate="G$1" x="-78.74" y="50.8"> +<attribute name="DIELECTRIC" x="-78.74" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C72" gate="G$1" x="-66.04" y="50.8"> +<attribute name="DIELECTRIC" x="-66.04" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C73" gate="G$1" x="-53.34" y="50.8"> +<attribute name="DIELECTRIC" x="-53.34" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-53.34" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-53.34" y="50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C74" gate="G$1" x="-40.64" y="50.8"> +<attribute name="DIELECTRIC" x="-40.64" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-40.64" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-40.64" y="50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C75" gate="G$1" x="-66.04" y="27.94"> +<attribute name="DIELECTRIC" x="-66.04" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C76" gate="G$1" x="-53.34" y="27.94"> +<attribute name="DIELECTRIC" x="-53.34" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-53.34" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-53.34" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C77" gate="G$1" x="-40.64" y="27.94"> +<attribute name="DIELECTRIC" x="-40.64" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-40.64" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-40.64" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C78" gate="G$1" x="-27.94" y="27.94"> +<attribute name="DIELECTRIC" x="-27.94" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-27.94" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-27.94" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C79" gate="G$1" x="-15.24" y="27.94"> +<attribute name="DIELECTRIC" x="-15.24" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-15.24" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-15.24" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C80" gate="G$1" x="-2.54" y="27.94"> +<attribute name="DIELECTRIC" x="-2.54" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-2.54" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-2.54" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C81" gate="G$1" x="10.16" y="27.94"> +<attribute name="DIELECTRIC" x="10.16" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="10.16" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="10.16" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C82" gate="G$1" x="22.86" y="27.94"> +<attribute name="DIELECTRIC" x="22.86" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="22.86" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="22.86" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C83" gate="G$1" x="35.56" y="27.94"> +<attribute name="DIELECTRIC" x="35.56" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="35.56" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="35.56" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C84" gate="G$1" x="48.26" y="27.94"> +<attribute name="DIELECTRIC" x="48.26" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="48.26" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C85" gate="G$1" x="60.96" y="27.94"> +<attribute name="DIELECTRIC" x="60.96" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="60.96" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="60.96" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C88" gate="G$1" x="-10.16" y="-12.7"> +<attribute name="DIELECTRIC" x="-10.16" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-10.16" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-10.16" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C89" gate="G$1" x="2.54" y="-12.7"> +<attribute name="DIELECTRIC" x="2.54" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="2.54" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="2.54" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C90" gate="G$1" x="15.24" y="-12.7"> +<attribute name="DIELECTRIC" x="15.24" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="15.24" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="15.24" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C92" gate="G$1" x="27.94" y="-12.7"> +<attribute name="DIELECTRIC" x="27.94" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="27.94" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="27.94" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C93" gate="G$1" x="40.64" y="-12.7"> +<attribute name="DIELECTRIC" x="40.64" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="40.64" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="40.64" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C130" gate="G$1" x="73.66" y="27.94"> +<attribute name="DIELECTRIC" x="73.66" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="73.66" y="27.94" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="73.66" y="27.94" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C142" gate="G$1" x="-5.08" y="73.66"> +<attribute name="DIELECTRIC" x="-5.08" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-5.08" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-5.08" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C143" gate="G$1" x="7.62" y="73.66"> +<attribute name="DIELECTRIC" x="7.62" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="7.62" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="7.62" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C144" gate="G$1" x="20.32" y="73.66"> +<attribute name="DIELECTRIC" x="20.32" y="73.66" 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gate="G$1" x="-35.56" y="73.66"> +<attribute name="DIELECTRIC" x="-35.56" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-35.56" y="73.66" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-35.56" y="73.66" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C169" gate="G$1" x="-71.12" y="-12.7"> +<attribute name="DIELECTRIC" x="-71.12" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-71.12" y="-12.7" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-71.12" y="-12.7" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY65" gate="GND" pin="GND"/> +<pinref part="C65" gate="G$1" pin="-"/> +<wire x1="-78.74" y1="66.04" x2="-78.74" y2="68.58" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY66" gate="GND" pin="GND"/> +<wire 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part="C155" gate="G$1" pin="1"/> +<pinref part="C169" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_VCCINT_1V0" class="0"> +<segment> +<wire x1="-66.04" y1="78.74" x2="-66.04" y2="76.2" width="0.1524" layer="91"/> +<pinref part="C65" gate="G$1" pin="+"/> +<wire x1="-78.74" y1="76.2" x2="-78.74" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="78.74" x2="-66.04" y2="78.74" width="0.1524" layer="91"/> +<junction x="-78.74" y="78.74"/> +<wire x1="-78.74" y1="78.74" x2="-104.14" y2="78.74" width="0.1524" layer="91"/> +<label x="-101.6" y="78.74" size="1.778" layer="95"/> +<wire x1="-48.26" y1="76.2" x2="-48.26" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="78.74" x2="-66.04" y2="78.74" width="0.1524" layer="91"/> +<junction x="-66.04" y="78.74"/> +<wire x1="-35.56" y1="76.2" x2="-35.56" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="78.74" x2="-48.26" y2="78.74" width="0.1524" layer="91"/> +<junction x="-48.26" y="78.74"/> +<wire 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x="48.26" y="33.02"/> +<wire x1="60.96" y1="33.02" x2="48.26" y2="33.02" width="0.1524" layer="91"/> +<wire x1="60.96" y1="30.48" x2="60.96" y2="33.02" width="0.1524" layer="91"/> +<junction x="60.96" y="33.02"/> +<wire x1="-40.64" y1="30.48" x2="-40.64" y2="33.02" width="0.1524" layer="91"/> +<junction x="-40.64" y="33.02"/> +<wire x1="-27.94" y1="30.48" x2="-27.94" y2="33.02" width="0.1524" layer="91"/> +<junction x="-27.94" y="33.02"/> +<wire x1="-15.24" y1="30.48" x2="-15.24" y2="33.02" width="0.1524" layer="91"/> +<junction x="-15.24" y="33.02"/> +<wire x1="-2.54" y1="30.48" x2="-2.54" y2="33.02" width="0.1524" layer="91"/> +<junction x="-2.54" y="33.02"/> +<wire x1="10.16" y1="30.48" x2="10.16" y2="33.02" width="0.1524" layer="91"/> +<junction x="10.16" y="33.02"/> +<wire x1="22.86" y1="30.48" x2="22.86" y2="33.02" width="0.1524" layer="91"/> +<junction x="22.86" y="33.02"/> +<wire x1="35.56" y1="30.48" x2="35.56" y2="33.02" width="0.1524" layer="91"/> +<junction x="35.56" y="33.02"/> +<pinref part="C68" gate="G$1" pin="1"/> +<pinref part="C69" gate="G$1" pin="+"/> +<pinref part="C71" gate="G$1" pin="1"/> +<pinref part="C72" gate="G$1" pin="1"/> +<pinref part="C73" gate="G$1" pin="1"/> +<pinref part="C74" gate="G$1" pin="1"/> +<pinref part="C75" gate="G$1" pin="1"/> +<pinref part="C76" gate="G$1" pin="1"/> +<pinref part="C77" gate="G$1" pin="1"/> +<pinref part="C78" gate="G$1" pin="1"/> +<pinref part="C79" gate="G$1" pin="1"/> +<pinref part="C80" gate="G$1" pin="1"/> +<pinref part="C81" gate="G$1" pin="1"/> +<pinref part="C82" gate="G$1" pin="1"/> +<pinref part="C83" gate="G$1" pin="1"/> +<pinref part="C84" gate="G$1" pin="1"/> +<pinref part="C85" gate="G$1" pin="1"/> +<pinref part="C130" gate="G$1" pin="1"/> +<pinref part="C142" gate="G$1" pin="1"/> +<pinref part="C143" gate="G$1" pin="1"/> +<pinref part="C144" gate="G$1" pin="1"/> +<pinref part="C145" gate="G$1" pin="1"/> +<pinref part="C146" gate="G$1" pin="1"/> +<pinref part="C147" gate="G$1" pin="1"/> +<pinref part="C148" gate="G$1" pin="1"/> +<pinref part="C149" gate="G$1" pin="1"/> +<pinref part="C150" gate="G$1" pin="1"/> +<pinref part="C151" gate="G$1" pin="1"/> +<pinref part="C152" gate="G$1" pin="1"/> +<pinref part="C168" gate="G$1" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 4-2</description> +<plain> +<text x="0" y="78.74" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA package +<-- Place large 47 uF caps not far from the BGA package + +<-- Place one of four 47 uF caps on every side of the BGA package +<-- Distribute six sets of caps among six FPGA I/O banks</text> +<text x="-104.14" y="101.6" size="1.778" layer="91">*) Decoupling capacitors for VCCO</text> +</plain> +<instances> +<instance part="SUPPLY107" gate="GND" x="-142.24" y="78.74"/> +<instance part="SUPPLY108" gate="GND" x="-129.54" y="78.74"/> +<instance part="SUPPLY109" gate="GND" x="-116.84" y="78.74"/> +<instance part="SUPPLY110" gate="GND" x="-104.14" y="78.74"/> +<instance part="SUPPLY111" gate="GND" x="-81.28" y="78.74"/> +<instance part="SUPPLY112" gate="GND" x="-68.58" y="78.74"/> +<instance part="SUPPLY113" gate="GND" x="-50.8" y="78.74"/> +<instance part="SUPPLY114" gate="GND" x="-38.1" y="78.74"/> +<instance part="SUPPLY115" gate="GND" x="-25.4" y="78.74"/> +<instance part="SUPPLY116" gate="GND" x="-12.7" y="78.74"/> +<instance part="SUPPLY117" gate="GND" x="-81.28" y="55.88"/> +<instance part="SUPPLY118" gate="GND" x="-68.58" y="55.88"/> +<instance part="SUPPLY119" gate="GND" x="-50.8" y="55.88"/> +<instance part="SUPPLY120" gate="GND" x="-38.1" y="55.88"/> +<instance part="SUPPLY121" gate="GND" x="-25.4" y="55.88"/> +<instance part="SUPPLY122" gate="GND" x="-12.7" y="55.88"/> +<instance part="SUPPLY123" gate="GND" x="-81.28" y="33.02"/> +<instance part="SUPPLY124" gate="GND" x="-68.58" y="33.02"/> +<instance part="SUPPLY125" gate="GND" x="-50.8" y="33.02"/> +<instance part="SUPPLY126" gate="GND" x="-38.1" y="33.02"/> +<instance part="SUPPLY127" gate="GND" x="-25.4" y="33.02"/> +<instance part="SUPPLY128" gate="GND" x="-12.7" y="33.02"/> +<instance part="SUPPLY129" gate="GND" x="-81.28" y="10.16"/> +<instance part="SUPPLY130" gate="GND" x="-68.58" y="10.16"/> +<instance part="SUPPLY131" gate="GND" x="-50.8" y="10.16"/> +<instance part="SUPPLY132" gate="GND" x="-38.1" y="10.16"/> +<instance part="SUPPLY133" gate="GND" x="-25.4" y="10.16"/> +<instance part="SUPPLY134" gate="GND" x="-12.7" y="10.16"/> +<instance part="SUPPLY135" gate="GND" x="-81.28" y="-12.7"/> +<instance part="SUPPLY136" gate="GND" x="-68.58" y="-12.7"/> +<instance part="SUPPLY137" gate="GND" x="-50.8" y="-12.7"/> +<instance part="SUPPLY138" gate="GND" x="-38.1" y="-12.7"/> +<instance part="SUPPLY139" gate="GND" x="-25.4" y="-12.7"/> +<instance part="SUPPLY140" gate="GND" x="-12.7" y="-12.7"/> +<instance part="SUPPLY141" gate="GND" x="-81.28" y="-35.56"/> +<instance part="SUPPLY142" gate="GND" x="-68.58" y="-35.56"/> +<instance part="SUPPLY143" gate="GND" x="-50.8" y="-35.56"/> +<instance part="SUPPLY144" gate="GND" x="-38.1" y="-35.56"/> +<instance part="SUPPLY145" gate="GND" x="-25.4" y="-35.56"/> +<instance part="SUPPLY146" gate="GND" x="-12.7" y="-35.56"/> +<instance part="FRAME17" gate="G$1" x="-177.8" y="-63.5"/> +<instance part="C97" gate="G$1" x="-50.8" y="88.9"> +<attribute name="DIELECTRIC" x="-50.8" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-50.8" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-50.8" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C98" gate="G$1" x="-38.1" y="88.9"> +<attribute name="DIELECTRIC" x="-38.1" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-38.1" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-38.1" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C100" gate="G$1" x="-25.4" y="88.9"> +<attribute name="DIELECTRIC" x="-25.4" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-25.4" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-25.4" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C101" gate="G$1" x="-12.7" y="88.9"> +<attribute name="DIELECTRIC" x="-12.7" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-12.7" y="88.9" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-12.7" y="88.9" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C102" gate="G$1" x="-50.8" y="66.04"> +<attribute name="DIELECTRIC" x="-50.8" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-50.8" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-50.8" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C105" gate="G$1" x="-38.1" y="66.04"> +<attribute name="DIELECTRIC" x="-38.1" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-38.1" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-38.1" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C106" gate="G$1" x="-25.4" y="66.04"> +<attribute name="DIELECTRIC" x="-25.4" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-25.4" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-25.4" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C107" gate="G$1" x="-12.7" y="66.04"> +<attribute name="DIELECTRIC" x="-12.7" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-12.7" y="66.04" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-12.7" y="66.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C108" gate="G$1" x="-50.8" y="43.18"> +<attribute name="DIELECTRIC" x="-50.8" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-50.8" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-50.8" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C109" gate="G$1" x="-38.1" y="43.18"> +<attribute name="DIELECTRIC" x="-38.1" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-38.1" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-38.1" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C113" gate="G$1" x="-25.4" y="43.18"> +<attribute name="DIELECTRIC" x="-25.4" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-25.4" y="43.18" size="1.778" layer="96" display="off"/> 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part="SUPPLY137" gate="GND" pin="GND"/> +<wire x1="-50.8" y1="-10.16" x2="-50.8" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="C122" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY138" gate="GND" pin="GND"/> +<wire x1="-38.1" y1="-7.62" x2="-38.1" y2="-10.16" width="0.1524" layer="91"/> +<pinref part="C123" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY139" gate="GND" pin="GND"/> +<wire x1="-25.4" y1="-10.16" x2="-25.4" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="C124" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY140" gate="GND" pin="GND"/> +<wire x1="-12.7" y1="-7.62" x2="-12.7" y2="-10.16" width="0.1524" layer="91"/> +<pinref part="C125" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY141" gate="GND" pin="GND"/> +<wire x1="-81.28" y1="-33.02" x2="-81.28" y2="-30.48" width="0.1524" layer="91"/> +<pinref part="C167" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY142" gate="GND" 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y1="-22.86" x2="-81.28" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="-22.86" x2="-12.7" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="-20.32" x2="-25.4" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="-20.32" x2="-38.1" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="-20.32" x2="-50.8" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="-20.32" x2="-68.58" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-68.58" y1="-20.32" x2="-81.28" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-68.58" y1="-22.86" x2="-68.58" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-68.58" y="-20.32"/> +<wire x1="-50.8" y1="-22.86" x2="-50.8" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-50.8" y="-20.32"/> +<wire x1="-38.1" y1="-22.86" x2="-38.1" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-38.1" y="-20.32"/> +<wire x1="-25.4" y1="-22.86" x2="-25.4" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-25.4" y="-20.32"/> +<wire x1="-81.28" y1="-20.32" x2="-91.44" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-81.28" y="-20.32"/> +<wire x1="-91.44" y1="-20.32" x2="-91.44" y2="2.54" width="0.1524" layer="91"/> +<junction x="-91.44" y="2.54"/> +<pinref part="C97" gate="G$1" pin="1"/> +<pinref part="C98" gate="G$1" pin="1"/> +<pinref part="C100" gate="G$1" pin="1"/> +<pinref part="C101" gate="G$1" pin="1"/> +<pinref part="C102" gate="G$1" pin="1"/> +<pinref part="C105" gate="G$1" pin="1"/> +<pinref part="C106" gate="G$1" pin="1"/> +<pinref part="C107" gate="G$1" pin="1"/> +<pinref part="C108" gate="G$1" pin="1"/> +<pinref part="C109" gate="G$1" pin="1"/> +<pinref part="C113" gate="G$1" pin="1"/> +<pinref part="C117" gate="G$1" pin="1"/> +<pinref part="C118" gate="G$1" pin="1"/> +<pinref part="C119" gate="G$1" pin="1"/> +<pinref part="C120" gate="G$1" pin="1"/> +<pinref part="C121" gate="G$1" pin="1"/> +<pinref part="C122" gate="G$1" pin="1"/> +<pinref part="C123" gate="G$1" pin="1"/> +<pinref part="C124" gate="G$1" pin="1"/> +<pinref part="C125" gate="G$1" pin="1"/> +<pinref part="C126" gate="G$1" pin="1"/> +<pinref part="C127" gate="G$1" pin="1"/> +<pinref part="C128" gate="G$1" pin="1"/> +<pinref part="C129" gate="G$1" pin="1"/> +<pinref part="C156" gate="G$1" pin="1"/> +<pinref part="C157" gate="G$1" pin="1"/> +<pinref part="C158" gate="G$1" pin="1"/> +<pinref part="C159" gate="G$1" pin="1"/> +<pinref part="C160" gate="G$1" pin="1"/> +<pinref part="C161" gate="G$1" pin="1"/> +<pinref part="C162" gate="G$1" pin="1"/> +<pinref part="C163" gate="G$1" pin="1"/> +<pinref part="C164" gate="G$1" pin="1"/> +<pinref part="C165" gate="G$1" pin="1"/> +<pinref part="C166" gate="G$1" pin="1"/> +<pinref part="C167" gate="G$1" pin="1"/> +<pinref part="C170" gate="G$1" pin="1"/> +<pinref part="C171" gate="G$1" pin="1"/> +<pinref part="C172" gate="G$1" pin="1"/> +<pinref part="C173" gate="G$1" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 4-3</description> +<plain> +<text x="-22.86" y="68.58" size="1.778" layer="91">*) FPGA Power Subsystem -- CORE</text> +<text x="68.58" y="33.02" size="1.778" layer="91">*) VCCINT = 0.6V x (1 + 150 / 226) = 0.998V + +*) OCP_ADJ is not used (default over-current threshold) + +*) MARx are not used (output at nominal 100%) + +*) S_IN/S_OUT are not used (single regulator mode) + +*) S_DELAY is not used (single regulator mode) + +*) M/S is not used (parallel operation not needed) + +*) EA_OUT is not used (default control loop) + +*) Minimal load current is 0A, but we still place +load of 100 Ohms just in case (gives 10 mA)</text> +</plain> +<instances> +<instance part="FRAME19" gate="G$1" x="-121.92" y="-96.52"/> +<instance part="SUPPLY181" gate="GND" x="-25.4" y="-71.12"/> +<instance part="SUPPLY182" gate="GND" x="-12.7" y="-71.12"/> +<instance part="C94" gate="G$1" x="-45.72" y="-60.96"> +<attribute name="RATED_VOLTAGE" x="-45.72" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-45.72" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-45.72" y="-60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY183" gate="GND" x="-45.72" y="-71.12"/> +<instance part="R50" gate="G$1" x="-60.96" y="2.54" rot="R90"> +<attribute name="TOLERANCE" x="-60.96" y="2.54" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C95" gate="G$1" x="-86.36" y="5.08"> +<attribute name="DIELECTRIC" x="-86.36" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-86.36" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-86.36" y="5.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C96" gate="G$1" x="-76.2" y="5.08"> +<attribute name="DIELECTRIC" x="-76.2" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-76.2" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-76.2" y="5.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY184" gate="GND" x="-86.36" y="-7.62"/> +<instance part="SUPPLY185" gate="GND" x="-76.2" y="-7.62"/> +<instance part="R51" gate="G$1" x="17.78" y="2.54" rot="R90"> +<attribute name="TOLERANCE" x="17.78" y="2.54" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R52" gate="G$1" x="17.78" y="-12.7" rot="R90"> +<attribute name="TOLERANCE" x="17.78" y="-12.7" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C99" gate="G$1" x="25.4" y="5.08"> +<attribute name="DIELECTRIC" x="25.4" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="25.4" y="5.08" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="25.4" y="5.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U$7" gate="G$1" x="-20.32" y="-22.86"/> +<instance part="SUPPLY189" gate="GND" x="17.78" y="-22.86"/> +<instance part="SUPPLY190" gate="GND" x="35.56" y="-22.86"/> +<instance part="SUPPLY191" gate="GND" x="48.26" y="-22.86"/> +<instance part="R53" gate="G$1" x="68.58" y="10.16"/> +<instance part="R54" gate="G$1" x="60.96" y="-10.16" rot="R90"> +<attribute name="TOLERANCE" x="60.96" y="-10.16" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY192" gate="GND" x="60.96" y="-22.86"/> +<instance part="R67" gate="G$1" x="7.62" y="-12.7" rot="R90"/> +<instance part="C176" gate="G$1" x="35.56" y="-7.62"> +<attribute name="DIELECTRIC" x="35.56" y="-7.62" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="35.56" y="-7.62" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="35.56" y="-7.62" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C177" gate="G$1" x="48.26" y="-7.62"> +<attribute name="DIELECTRIC" x="48.26" y="-7.62" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="-7.62" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="48.26" y="-7.62" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY181" gate="GND" pin="GND"/> +<wire x1="-25.4" y1="-66.04" x2="-25.4" y2="-68.58" width="0.1524" layer="91"/> +<pinref part="U$7" gate="G$1" pin="AGND"/> +</segment> +<segment> +<pinref part="SUPPLY182" gate="GND" pin="GND"/> +<wire x1="-12.7" y1="-66.04" x2="-12.7" y2="-68.58" width="0.1524" layer="91"/> +<pinref part="U$7" gate="G$1" pin="PGND"/> +</segment> +<segment> +<pinref part="SUPPLY183" gate="GND" pin="GND"/> +<pinref part="C94" gate="G$1" pin="2"/> +<wire x1="-45.72" y1="-68.58" x2="-45.72" y2="-66.04" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C95" gate="G$1" pin="2"/> +<wire x1="-86.36" y1="0" x2="-86.36" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="SUPPLY184" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="C96" gate="G$1" pin="2"/> +<wire x1="-76.2" y1="0" x2="-76.2" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="SUPPLY185" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="R52" gate="G$1" pin="1"/> +<wire x1="17.78" y1="-17.78" x2="17.78" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY189" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="SUPPLY190" gate="GND" pin="GND"/> +<wire x1="35.56" y1="-20.32" x2="35.56" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="C176" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY191" gate="GND" pin="GND"/> +<wire x1="48.26" y1="-20.32" x2="48.26" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="C177" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY192" gate="GND" pin="GND"/> +<pinref part="R54" gate="G$1" pin="1"/> +<wire x1="60.96" y1="-20.32" x2="60.96" y2="-15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_VCCINT_1V0" class="0"> +<segment> +<wire x1="73.66" y1="10.16" x2="99.06" y2="10.16" width="0.1524" layer="91"/> +<label x="76.2" y="10.16" size="1.778" layer="95"/> +<pinref part="R53" gate="G$1" pin="2"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<wire x1="-45.72" y1="5.08" x2="-45.72" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="10.16" x2="-40.64" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="5.08" x2="-45.72" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="10.16" x2="-60.96" y2="10.16" width="0.1524" layer="91"/> +<junction x="-45.72" y="10.16"/> +<label x="-91.44" y="10.16" size="1.778" layer="95"/> +<pinref part="C95" gate="G$1" pin="1"/> +<wire x1="-60.96" y1="10.16" x2="-76.2" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="10.16" x2="-86.36" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="10.16" x2="-91.44" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="7.62" x2="-86.36" y2="10.16" width="0.1524" layer="91"/> +<junction x="-86.36" y="10.16"/> +<pinref part="C96" gate="G$1" pin="1"/> +<wire x1="-76.2" y1="7.62" x2="-76.2" y2="10.16" width="0.1524" layer="91"/> +<junction x="-76.2" y="10.16"/> +<pinref part="R50" gate="G$1" pin="2"/> +<wire x1="-60.96" y1="7.62" x2="-60.96" y2="10.16" width="0.1524" layer="91"/> +<junction x="-60.96" y="10.16"/> +<pinref part="U$7" gate="G$1" pin="PVIN"/> +<pinref part="U$7" gate="G$1" pin="AVIN"/> +</segment> +</net> +<net name="POK_VCCINT" class="0"> +<segment> +<wire x1="5.08" y1="-55.88" x2="5.08" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="2.54" y1="-55.88" x2="5.08" y2="-55.88" width="0.1524" layer="91"/> +<label x="5.08" y="-53.34" size="1.778" layer="95" rot="R90"/> +<pinref part="U$7" gate="G$1" pin="POK"/> +</segment> +</net> +<net name="N$45" class="0"> +<segment> +<wire x1="-40.64" y1="-55.88" x2="-45.72" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C94" gate="G$1" pin="1"/> +<wire x1="-45.72" y1="-55.88" x2="-45.72" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="U$7" gate="G$1" pin="SS"/> +</segment> +</net> +<net name="N$46" class="0"> +<segment> +<pinref part="R50" gate="G$1" pin="1"/> +<wire x1="-40.64" y1="-5.08" x2="-60.96" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="-5.08" x2="-60.96" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="U$7" gate="G$1" pin="EN_PB"/> +</segment> +</net> +<net name="PWR_ENA_VCCINT" class="0"> +<segment> +<wire x1="-40.64" y1="0" x2="-50.8" y2="0" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="0" x2="-50.8" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="20.32" x2="-91.44" y2="20.32" width="0.1524" layer="91"/> +<label x="-91.44" y="20.32" size="1.778" layer="95"/> +<pinref part="U$7" gate="G$1" pin="ENABLE"/> +</segment> +</net> +<net name="N$47" class="0"> +<segment> +<pinref part="U$7" gate="G$1" pin="VSENSE"/> +<wire x1="2.54" y1="-20.32" x2="7.62" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-20.32" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R67" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$48" class="0"> +<segment> +<wire x1="7.62" y1="-7.62" x2="7.62" y2="10.16" width="0.1524" layer="91"/> +<pinref part="U$7" gate="G$1" pin="VOUT"/> +<wire x1="7.62" y1="10.16" x2="2.54" y2="10.16" width="0.1524" layer="91"/> +<junction x="7.62" y="10.16"/> +<wire x1="7.62" y1="10.16" x2="17.78" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R51" gate="G$1" pin="2"/> +<wire x1="17.78" y1="7.62" x2="17.78" y2="10.16" width="0.1524" layer="91"/> +<wire x1="17.78" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<junction x="17.78" y="10.16"/> +<pinref part="C99" gate="G$1" pin="1"/> +<wire x1="25.4" y1="10.16" x2="25.4" y2="7.62" width="0.1524" layer="91"/> +<wire x1="35.56" y1="-5.08" x2="35.56" y2="10.16" width="0.1524" layer="91"/> +<wire x1="35.56" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/> +<junction x="25.4" y="10.16"/> +<wire x1="48.26" y1="-5.08" x2="48.26" y2="10.16" width="0.1524" layer="91"/> +<wire x1="48.26" y1="10.16" x2="35.56" y2="10.16" width="0.1524" layer="91"/> +<junction x="35.56" y="10.16"/> +<pinref part="R54" gate="G$1" pin="2"/> +<wire x1="60.96" y1="-5.08" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<wire x1="60.96" y1="10.16" x2="48.26" y2="10.16" width="0.1524" layer="91"/> +<junction x="48.26" y="10.16"/> +<pinref part="R53" gate="G$1" pin="1"/> +<wire x1="63.5" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<junction x="60.96" y="10.16"/> +<pinref part="R67" gate="G$1" pin="2"/> +<pinref part="C176" gate="G$1" pin="1"/> +<pinref part="C177" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$49" class="0"> +<segment> +<pinref part="U$7" gate="G$1" pin="VFB"/> +<wire x1="2.54" y1="-5.08" x2="17.78" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="R51" gate="G$1" pin="1"/> +<wire x1="17.78" y1="-5.08" x2="17.78" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="R52" gate="G$1" pin="2"/> +<wire x1="17.78" y1="-5.08" x2="17.78" y2="-7.62" width="0.1524" layer="91"/> +<junction x="17.78" y="-5.08"/> +<wire x1="17.78" y1="-5.08" x2="25.4" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="C99" gate="G$1" pin="2"/> +<wire x1="25.4" y1="-5.08" x2="25.4" y2="0" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 5-1</description> +<plain> +</plain> +<instances> +<instance part="LED11" gate="G$1" x="-81.28" y="22.86"/> +<instance part="LED12" gate="G$1" x="-60.96" y="22.86"/> +<instance part="R22" gate="G$1" x="-81.28" y="35.56" rot="R90"> +<attribute name="TOLERANCE" x="-81.28" y="35.56" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY152" gate="GND" x="-81.28" y="10.16"/> +<instance part="FRAME20" gate="G$1" x="-127" y="-101.6"/> +<instance part="LED13" gate="G$1" x="-40.64" y="22.86"/> +<instance part="LED14" gate="G$1" x="-20.32" y="22.86"/> +<instance part="R30" gate="G$1" x="-60.96" y="35.56" rot="R90"> +<attribute name="TOLERANCE" x="-60.96" y="35.56" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R31" gate="G$1" x="-40.64" y="35.56" rot="R90"> +<attribute name="TOLERANCE" x="-40.64" y="35.56" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R32" gate="G$1" x="-20.32" y="35.56" rot="R90"> +<attribute name="TOLERANCE" x="-20.32" y="35.56" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY186" gate="GND" x="-60.96" y="10.16"/> +<instance part="SUPPLY187" gate="GND" x="-40.64" y="10.16"/> +<instance part="SUPPLY188" gate="GND" x="-20.32" y="10.16"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY152" gate="GND" pin="GND"/> +<pinref part="LED11" gate="G$1" pin="C"/> +<wire x1="-81.28" y1="12.7" x2="-81.28" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY186" gate="GND" pin="GND"/> +<pinref part="LED12" gate="G$1" pin="C"/> +<wire x1="-60.96" y1="12.7" x2="-60.96" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY187" gate="GND" pin="GND"/> +<pinref part="LED13" gate="G$1" pin="C"/> +<wire x1="-40.64" y1="12.7" x2="-40.64" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY188" gate="GND" pin="GND"/> +<pinref part="LED14" gate="G$1" pin="C"/> +<wire x1="-20.32" y1="12.7" x2="-20.32" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_2" class="0"> +<segment> +<pinref part="R31" gate="G$1" pin="2"/> +<wire x1="-40.64" y1="40.64" x2="-40.64" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="55.88" x2="-106.68" y2="55.88" width="0.1524" layer="91"/> +<label x="-106.68" y="55.88" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_3" class="0"> +<segment> +<pinref part="R32" gate="G$1" pin="2"/> +<wire x1="-20.32" y1="40.64" x2="-20.32" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="60.96" x2="-106.68" y2="60.96" width="0.1524" layer="91"/> +<label x="-106.68" y="60.96" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_0" class="0"> +<segment> +<pinref part="R22" gate="G$1" pin="2"/> +<wire x1="-81.28" y1="40.64" x2="-81.28" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="45.72" x2="-106.68" y2="45.72" width="0.1524" layer="91"/> +<label x="-106.68" y="45.72" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_1" class="0"> +<segment> +<pinref part="R30" gate="G$1" pin="2"/> +<wire x1="-60.96" y1="40.64" x2="-60.96" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="50.8" x2="-106.68" y2="50.8" width="0.1524" layer="91"/> +<label x="-106.68" y="50.8" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$27" class="0"> +<segment> +<pinref part="LED11" gate="G$1" pin="A"/> +<pinref part="R22" gate="G$1" pin="1"/> +<wire x1="-81.28" y1="25.4" x2="-81.28" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$28" class="0"> +<segment> +<pinref part="LED12" gate="G$1" pin="A"/> +<wire x1="-60.96" y1="25.4" x2="-60.96" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R30" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$29" class="0"> +<segment> +<pinref part="LED13" gate="G$1" pin="A"/> +<wire x1="-40.64" y1="25.4" x2="-40.64" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R31" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$30" class="0"> +<segment> +<pinref part="LED14" gate="G$1" pin="A"/> +<wire x1="-20.32" y1="25.4" x2="-20.32" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R32" gate="G$1" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 5-2</description> +<plain> +<text x="58.42" y="63.5" size="1.778" layer="91">*) Recommended power-up sequence: + +1) VCCINT + +2) VCCAUX + +3) VCCO + +RC network values are preliminary, +should be tweaked after experiments +</text> +<text x="-55.88" y="55.88" size="1.778" layer="91">---></text> +<text x="63.5" y="55.88" size="1.778" layer="91">---></text> +<text x="-137.16" y="-17.78" size="1.778" layer="91">---></text> +<text x="-22.86" y="-17.78" size="1.778" layer="91">---></text> +<text x="12.7" y="-35.56" size="1.778" layer="91">*) "Power OK" LED, should be of green color</text> +</plain> +<instances> +<instance part="FRAME21" gate="G$1" x="-152.4" y="-78.74"/> +<instance part="R55" gate="G$1" x="-106.68" y="55.88"> +<attribute name="TOLERANCE" x="-106.68" y="55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D3" gate="G$1" x="-106.68" y="66.04" rot="MR0"/> +<instance part="SUPPLY193" gate="GND" x="-96.52" y="35.56"/> +<instance part="R56" gate="G$1" x="-12.7" y="66.04" rot="R90"> +<attribute name="TOLERANCE" x="-12.7" y="66.04" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R57" gate="G$1" x="7.62" y="55.88"> +<attribute name="TOLERANCE" x="7.62" y="55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D4" gate="G$1" x="7.62" y="66.04" rot="MR0"/> +<instance part="SUPPLY194" gate="GND" x="17.78" y="35.56"/> +<instance part="R58" gate="G$1" x="-96.52" y="-7.62" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="-7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R59" gate="G$1" x="-76.2" y="-17.78"> +<attribute name="TOLERANCE" x="-76.2" y="-17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D5" gate="G$1" x="-76.2" y="-7.62" rot="MR0"/> +<instance part="SUPPLY195" gate="GND" x="-66.04" y="-38.1"/> +<instance part="R60" gate="G$1" x="20.32" y="2.54" rot="R90"> +<attribute name="TOLERANCE" x="20.32" y="2.54" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="Q3" gate="G$1" x="40.64" y="-15.24"/> +<instance part="SUPPLY196" gate="GND" x="50.8" y="-25.4"/> +<instance part="LED16" gate="G$1" x="50.8" y="-2.54" rot="MR0"/> +<instance part="R61" gate="G$1" x="50.8" y="10.16" rot="MR90"> +<attribute name="TOLERANCE" x="50.8" y="10.16" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +<instance part="C137" gate="G$1" x="-96.52" y="48.26"> +<attribute name="DIELECTRIC" x="-96.52" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-96.52" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-96.52" y="48.26" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C138" gate="G$1" x="-66.04" y="-25.4"> +<attribute name="DIELECTRIC" x="-66.04" y="-25.4" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="-25.4" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="-25.4" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C139" gate="G$1" x="17.78" y="48.26"> +<attribute name="DIELECTRIC" x="17.78" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="17.78" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="48.26" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY193" gate="GND" pin="GND"/> +<wire x1="-96.52" y1="38.1" x2="-96.52" y2="43.18" width="0.1524" layer="91"/> +<pinref part="C137" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY194" gate="GND" pin="GND"/> +<wire x1="17.78" y1="38.1" x2="17.78" y2="43.18" width="0.1524" layer="91"/> +<pinref part="C139" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY195" gate="GND" pin="GND"/> +<wire x1="-66.04" y1="-35.56" x2="-66.04" y2="-30.48" width="0.1524" layer="91"/> +<pinref part="C138" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="Q3" gate="G$1" pin="S"/> +<wire x1="45.72" y1="-17.78" x2="50.8" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="SUPPLY196" gate="GND" pin="GND"/> +<wire x1="50.8" y1="-17.78" x2="50.8" y2="-22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<pinref part="R55" gate="G$1" pin="1"/> +<wire x1="-111.76" y1="55.88" x2="-116.84" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-116.84" y1="55.88" x2="-116.84" y2="66.04" width="0.1524" layer="91"/> +<pinref part="D3" gate="G$1" pin="C"/> +<wire x1="-116.84" y1="66.04" x2="-109.22" y2="66.04" width="0.1524" layer="91"/> +<junction x="-116.84" y="55.88"/> +<wire x1="-116.84" y1="55.88" x2="-137.16" y2="55.88" width="0.1524" layer="91"/> +<label x="-137.16" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-33.02" y1="76.2" x2="-12.7" y2="76.2" width="0.1524" layer="91"/> +<pinref part="R56" gate="G$1" pin="2"/> +<wire x1="-12.7" y1="71.12" x2="-12.7" y2="76.2" width="0.1524" layer="91"/> +<label x="-33.02" y="76.2" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-116.84" y1="2.54" x2="-96.52" y2="2.54" width="0.1524" layer="91"/> +<pinref part="R58" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="-2.54" x2="-96.52" y2="2.54" width="0.1524" layer="91"/> +<label x="-116.84" y="2.54" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="0" y1="20.32" x2="20.32" y2="20.32" width="0.1524" layer="91"/> +<pinref part="R60" gate="G$1" pin="2"/> +<wire x1="20.32" y1="7.62" x2="20.32" y2="20.32" width="0.1524" layer="91"/> +<label x="0" y="20.32" size="1.778" layer="95"/> +<pinref part="R61" gate="G$1" pin="2"/> +<wire x1="50.8" y1="15.24" x2="50.8" y2="20.32" width="0.1524" layer="91"/> +<wire x1="50.8" y1="20.32" x2="20.32" y2="20.32" width="0.1524" layer="91"/> +<junction x="20.32" y="20.32"/> +</segment> +</net> +<net name="PWR_ENA_VCCAUX" class="0"> +<segment> +<wire x1="12.7" y1="55.88" x2="17.78" y2="55.88" width="0.1524" layer="91"/> +<label x="20.32" y="55.88" size="1.778" layer="95"/> +<pinref part="R57" gate="G$1" pin="2"/> +<wire x1="17.78" y1="55.88" x2="43.18" y2="55.88" width="0.1524" layer="91"/> +<wire x1="17.78" y1="50.8" x2="17.78" y2="55.88" width="0.1524" layer="91"/> +<junction x="17.78" y="55.88"/> +<pinref part="D4" gate="G$1" pin="A"/> +<wire x1="17.78" y1="66.04" x2="10.16" y2="66.04" width="0.1524" layer="91"/> +<wire x1="17.78" y1="66.04" x2="17.78" y2="55.88" width="0.1524" layer="91"/> +<pinref part="C139" gate="G$1" pin="1"/> +</segment> +</net> +<net name="POK_VCCINT" class="0"> +<segment> +<wire x1="-33.02" y1="55.88" x2="-12.7" y2="55.88" width="0.1524" layer="91"/> +<pinref part="R56" gate="G$1" pin="1"/> +<wire x1="-12.7" y1="55.88" x2="-12.7" y2="60.96" width="0.1524" layer="91"/> +<label x="-33.02" y="55.88" size="1.778" layer="95"/> +<pinref part="R57" gate="G$1" pin="1"/> +<wire x1="2.54" y1="55.88" x2="-2.54" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="55.88" x2="-2.54" y2="66.04" width="0.1524" layer="91"/> +<pinref part="D4" gate="G$1" pin="C"/> +<wire x1="-2.54" y1="66.04" x2="5.08" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="55.88" x2="-2.54" y2="55.88" width="0.1524" layer="91"/> +<junction x="-12.7" y="55.88"/> +<junction x="-2.54" y="55.88"/> +</segment> +</net> +<net name="PWR_ENA_VCCO" class="0"> +<segment> +<wire x1="-66.04" y1="-17.78" x2="-40.64" y2="-17.78" width="0.1524" layer="91"/> +<label x="-63.5" y="-17.78" size="1.778" layer="95"/> +<pinref part="D5" gate="G$1" pin="A"/> +<wire x1="-66.04" y1="-7.62" x2="-73.66" y2="-7.62" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="-17.78" x2="-66.04" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="R59" gate="G$1" pin="2"/> +<wire x1="-71.12" y1="-17.78" x2="-66.04" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-66.04" y="-17.78"/> +<wire x1="-66.04" y1="-22.86" x2="-66.04" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="C138" gate="G$1" pin="1"/> +</segment> +</net> +<net name="PWR_ENA_VCCINT" class="0"> +<segment> +<pinref part="D3" gate="G$1" pin="A"/> +<wire x1="-104.14" y1="66.04" x2="-96.52" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="66.04" x2="-96.52" y2="55.88" width="0.1524" layer="91"/> +<pinref part="R55" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="55.88" x2="-101.6" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="50.8" x2="-96.52" y2="55.88" width="0.1524" layer="91"/> +<junction x="-96.52" y="55.88"/> +<wire x1="-96.52" y1="55.88" x2="-71.12" y2="55.88" width="0.1524" layer="91"/> +<label x="-93.98" y="55.88" size="1.778" layer="95"/> +<pinref part="C137" gate="G$1" pin="1"/> +</segment> +</net> +<net name="POK_VCCAUX" class="0"> +<segment> +<wire x1="-116.84" y1="-17.78" x2="-96.52" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R58" gate="G$1" pin="1"/> +<wire x1="-96.52" y1="-17.78" x2="-96.52" y2="-12.7" width="0.1524" layer="91"/> +<label x="-116.84" y="-17.78" size="1.778" layer="95"/> +<pinref part="R59" gate="G$1" pin="1"/> +<wire x1="-81.28" y1="-17.78" x2="-86.36" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-17.78" x2="-86.36" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="D5" gate="G$1" pin="C"/> +<wire x1="-86.36" y1="-7.62" x2="-78.74" y2="-7.62" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-17.78" x2="-86.36" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-96.52" y="-17.78"/> +<junction x="-86.36" y="-17.78"/> +</segment> +</net> +<net name="POK_VCCO" class="0"> +<segment> +<wire x1="0" y1="-17.78" x2="20.32" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="R60" gate="G$1" pin="1"/> +<wire x1="20.32" y1="-17.78" x2="20.32" y2="-2.54" width="0.1524" layer="91"/> +<label x="0" y="-17.78" size="1.778" layer="95"/> +<pinref part="Q3" gate="G$1" pin="G"/> +<wire x1="20.32" y1="-17.78" x2="35.56" y2="-17.78" width="0.1524" layer="91"/> +<junction x="20.32" y="-17.78"/> +</segment> +</net> +<net name="N$50" class="0"> +<segment> +<pinref part="Q3" gate="G$1" pin="D"/> +<wire x1="45.72" y1="-12.7" x2="50.8" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="LED16" gate="G$1" pin="C"/> +<wire x1="50.8" y1="-12.7" x2="50.8" y2="-7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$51" class="0"> +<segment> +<pinref part="R61" gate="G$1" pin="1"/> +<pinref part="LED16" gate="G$1" pin="A"/> +<wire x1="50.8" y1="5.08" x2="50.8" y2="0" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Pavel 5-3</description> +<plain> +<text x="10.16" y="-73.66" size="1.778" layer="91">*) Intermediate Regulator: 18V -> 5V</text> +<text x="109.22" y="-81.28" size="1.778" layer="91">*) VCC_5V0 = 0.8V x (1 + 6.3/1.21) = 4.965V + +*) Current sharing not used + +*) SYNC is not used</text> +</plain> +<instances> +<instance part="FRAME22" gate="G$1" x="-88.9" y="-238.76"/> +<instance part="U$8" gate="G$1" x="60.96" y="-119.38"/> +<instance part="SUPPLY197" gate="GND" x="43.18" y="-162.56"/> +<instance part="SUPPLY198" gate="GND" x="58.42" y="-162.56"/> +<instance part="SUPPLY199" gate="GND" x="63.5" y="-162.56"/> +<instance part="C103" gate="G$1" x="17.78" y="-149.86"> +<attribute name="DIELECTRIC" x="17.78" y="-149.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="17.78" y="-149.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="-149.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY200" gate="GND" x="17.78" y="-162.56"/> +<instance part="SUPPLY201" gate="GND" x="7.62" y="-162.56"/> +<instance part="R62" gate="G$1" x="10.16" y="-119.38"> +<attribute name="TOLERANCE" x="10.16" y="-119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R63" gate="G$1" x="-2.54" y="-127" rot="R90"> +<attribute name="TOLERANCE" x="-2.54" y="-127" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R64" gate="G$1" x="-2.54" y="-111.76" rot="R90"> +<attribute name="TOLERANCE" x="-2.54" y="-111.76" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C104" gate="G$1" x="-53.34" y="-119.38"> +<attribute name="DIELECTRIC" x="-53.34" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-53.34" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-53.34" y="-119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY202" gate="GND" x="-2.54" y="-137.16"/> +<instance part="SUPPLY203" gate="GND" x="-17.78" y="-137.16"/> +<instance part="SUPPLY204" gate="GND" x="-33.02" y="-137.16"/> +<instance part="SUPPLY205" gate="GND" x="-43.18" y="-137.16"/> +<instance part="SUPPLY206" gate="GND" x="-53.34" y="-137.16"/> +<instance part="R65" gate="G$1" x="88.9" y="-116.84" rot="R90"> +<attribute name="TOLERANCE" x="88.9" y="-116.84" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R66" gate="G$1" x="88.9" y="-132.08" rot="R90"> +<attribute name="TOLERANCE" x="88.9" y="-132.08" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY207" gate="GND" x="88.9" y="-142.24"/> +<instance part="C111" gate="G$1" x="129.54" y="-114.3" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="129.54" y="-114.3" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="RATED_VOLTAGE" x="129.54" y="-114.3" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="132.715" y="-113.665" size="1.778" layer="95"/> +<attribute name="VALUE" x="132.08" y="-118.11" size="1.778" layer="96"/> +</instance> +<instance part="C114" gate="G$1" x="99.06" y="-111.76"> +<attribute name="RATED_VOLTAGE" x="99.06" y="-111.76" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="99.06" y="-111.76" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="99.06" y="-111.76" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C112" gate="G$1" x="144.78" y="-114.3" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="144.78" y="-114.3" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="RATED_VOLTAGE" x="144.78" y="-114.3" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="147.955" y="-113.665" size="1.778" layer="95"/> +<attribute name="VALUE" x="147.32" y="-118.11" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY208" gate="GND" x="99.06" y="-124.46"/> +<instance part="SUPPLY209" gate="GND" x="114.3" y="-124.46"/> +<instance part="SUPPLY210" gate="GND" x="129.54" y="-124.46"/> +<instance part="SUPPLY211" gate="GND" x="144.78" y="-124.46"/> +<instance part="C86" gate="G$1" x="-17.78" y="-119.38"> +<attribute name="RATED_VOLTAGE" x="-17.78" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-17.78" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-17.78" y="-119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R68" gate="G$1" x="7.62" y="-147.32" rot="R90"/> +<instance part="C140" gate="G$1" x="-43.18" y="-119.38"> +<attribute name="DIELECTRIC" x="-43.18" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-43.18" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-43.18" y="-119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C141" gate="G$1" x="-33.02" y="-119.38"> +<attribute name="DIELECTRIC" x="-33.02" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-33.02" y="-119.38" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-33.02" y="-119.38" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C178" gate="G$1" x="114.3" y="-111.76"> +<attribute name="DIELECTRIC" x="114.3" y="-111.76" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="114.3" y="-111.76" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="114.3" y="-111.76" size="1.778" layer="96" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY197" gate="GND" pin="GND"/> +<pinref part="U$8" gate="G$1" pin="PGND"/> +<wire x1="43.18" y1="-160.02" x2="43.18" y2="-149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY198" gate="GND" pin="GND"/> +<pinref part="U$8" gate="G$1" pin="AGND@5"/> +<wire x1="58.42" y1="-160.02" x2="58.42" y2="-149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY199" gate="GND" pin="GND"/> +<pinref part="U$8" gate="G$1" pin="AGND@6"/> +<wire x1="63.5" y1="-160.02" x2="63.5" y2="-149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY200" gate="GND" pin="GND"/> +<pinref part="C103" gate="G$1" pin="2"/> +<wire x1="17.78" y1="-160.02" x2="17.78" y2="-154.94" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY201" gate="GND" pin="GND"/> +<wire x1="7.62" y1="-160.02" x2="7.62" y2="-152.4" width="0.1524" layer="91"/> +<pinref part="R68" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="R63" gate="G$1" pin="1"/> +<pinref part="SUPPLY202" gate="GND" pin="GND"/> +<wire x1="-2.54" y1="-134.62" x2="-2.54" y2="-132.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY206" gate="GND" pin="GND"/> +<pinref part="C104" gate="G$1" pin="2"/> +<wire x1="-53.34" y1="-134.62" x2="-53.34" y2="-124.46" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY205" gate="GND" pin="GND"/> +<wire x1="-43.18" y1="-134.62" x2="-43.18" y2="-124.46" width="0.1524" layer="91"/> +<pinref part="C140" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY204" gate="GND" pin="GND"/> +<wire x1="-33.02" y1="-134.62" x2="-33.02" y2="-124.46" width="0.1524" layer="91"/> +<pinref part="C141" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY203" gate="GND" pin="GND"/> +<wire x1="-17.78" y1="-134.62" x2="-17.78" y2="-124.46" width="0.1524" layer="91"/> +<pinref part="C86" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="R66" gate="G$1" pin="1"/> +<pinref part="SUPPLY207" gate="GND" pin="GND"/> +<wire x1="88.9" y1="-137.16" x2="88.9" y2="-139.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY208" gate="GND" pin="GND"/> +<pinref part="C114" gate="G$1" pin="2"/> +<wire x1="99.06" y1="-121.92" x2="99.06" y2="-116.84" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY209" gate="GND" pin="GND"/> +<wire x1="114.3" y1="-121.92" x2="114.3" y2="-116.84" width="0.1524" layer="91"/> +<pinref part="C178" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY210" gate="GND" pin="GND"/> +<pinref part="C111" gate="G$1" pin="-"/> +<wire x1="129.54" y1="-121.92" x2="129.54" y2="-116.84" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY211" gate="GND" pin="GND"/> +<pinref part="C112" gate="G$1" pin="-"/> +<wire x1="144.78" y1="-121.92" x2="144.78" y2="-116.84" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<pinref part="U$8" gate="G$1" pin="VOUT@11"/> +<pinref part="U$8" gate="G$1" pin="VOUT@10"/> +<wire x1="88.9" y1="-104.14" x2="83.82" y2="-104.14" width="0.1524" layer="91"/> +<pinref part="R65" gate="G$1" pin="2"/> +<wire x1="88.9" y1="-111.76" x2="88.9" y2="-109.22" width="0.1524" layer="91"/> +<junction x="88.9" y="-104.14"/> +<wire x1="88.9" y1="-109.22" x2="88.9" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-109.22" x2="88.9" y2="-109.22" width="0.1524" layer="91"/> +<junction x="88.9" y="-109.22"/> +<pinref part="C114" gate="G$1" pin="1"/> +<wire x1="99.06" y1="-109.22" x2="99.06" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-104.14" x2="88.9" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="114.3" y1="-109.22" x2="114.3" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="114.3" y1="-104.14" x2="99.06" y2="-104.14" width="0.1524" layer="91"/> +<junction x="99.06" y="-104.14"/> +<pinref part="C111" gate="G$1" pin="+"/> +<wire x1="129.54" y1="-111.76" x2="129.54" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="129.54" y1="-104.14" x2="114.3" y2="-104.14" width="0.1524" layer="91"/> +<junction x="114.3" y="-104.14"/> +<pinref part="C112" gate="G$1" pin="+"/> +<wire x1="144.78" y1="-111.76" x2="144.78" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="144.78" y1="-104.14" x2="129.54" y2="-104.14" width="0.1524" layer="91"/> +<junction x="129.54" y="-104.14"/> +<wire x1="144.78" y1="-104.14" x2="149.86" y2="-104.14" width="0.1524" layer="91"/> +<junction x="144.78" y="-104.14"/> +<label x="139.7" y="-104.14" size="1.778" layer="95"/> +<pinref part="C178" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$52" class="0"> +<segment> +<pinref part="C103" gate="G$1" pin="1"/> +<wire x1="17.78" y1="-147.32" x2="17.78" y2="-139.7" width="0.1524" layer="91"/> +<pinref part="U$8" gate="G$1" pin="SS/TRK"/> +<wire x1="17.78" y1="-139.7" x2="22.86" y2="-139.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$53" class="0"> +<segment> +<wire x1="7.62" y1="-142.24" x2="7.62" y2="-129.54" width="0.1524" layer="91"/> +<pinref part="U$8" gate="G$1" pin="SYNC"/> +<wire x1="7.62" y1="-129.54" x2="22.86" y2="-129.54" width="0.1524" layer="91"/> +<pinref part="R68" gate="G$1" pin="2"/> +</segment> +</net> +<net name="PWR_18V" class="0"> +<segment> +<pinref part="U$8" gate="G$1" pin="VIN@2"/> +<wire x1="22.86" y1="-109.22" x2="17.78" y2="-109.22" width="0.1524" layer="91"/> +<wire x1="17.78" y1="-109.22" x2="17.78" y2="-104.14" width="0.1524" layer="91"/> +<pinref part="U$8" gate="G$1" pin="VIN@1"/> +<wire x1="17.78" y1="-104.14" x2="22.86" y2="-104.14" width="0.1524" layer="91"/> +<pinref part="R64" gate="G$1" pin="2"/> +<wire x1="-2.54" y1="-106.68" x2="-2.54" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="-104.14" x2="17.78" y2="-104.14" width="0.1524" layer="91"/> +<junction x="17.78" y="-104.14"/> +<pinref part="C104" gate="G$1" pin="1"/> +<wire x1="-53.34" y1="-116.84" x2="-53.34" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="-104.14" x2="-43.18" y2="-104.14" width="0.1524" layer="91"/> +<junction x="-2.54" y="-104.14"/> +<wire x1="-43.18" y1="-104.14" x2="-33.02" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="-104.14" x2="-17.78" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="-104.14" x2="-2.54" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="-116.84" x2="-43.18" y2="-104.14" width="0.1524" layer="91"/> +<junction x="-43.18" y="-104.14"/> +<wire x1="-17.78" y1="-116.84" x2="-17.78" y2="-104.14" width="0.1524" layer="91"/> +<junction x="-17.78" y="-104.14"/> +<wire x1="-53.34" y1="-104.14" x2="-58.42" y2="-104.14" width="0.1524" layer="91"/> +<junction x="-53.34" y="-104.14"/> +<label x="-58.42" y="-104.14" size="1.778" layer="95" rot="R180" xref="yes"/> +<pinref part="C86" gate="G$1" pin="1"/> +<pinref part="C140" gate="G$1" pin="1"/> +<pinref part="C141" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="-116.84" x2="-33.02" y2="-104.14" width="0.1524" layer="91"/> +<junction x="-33.02" y="-104.14"/> +</segment> +</net> +<net name="N$54" class="0"> +<segment> +<pinref part="R62" gate="G$1" pin="1"/> +<wire x1="5.08" y1="-119.38" x2="-2.54" y2="-119.38" width="0.1524" layer="91"/> +<pinref part="R64" gate="G$1" pin="1"/> +<wire x1="-2.54" y1="-119.38" x2="-2.54" y2="-116.84" width="0.1524" layer="91"/> +<pinref part="R63" gate="G$1" pin="2"/> +<wire x1="-2.54" y1="-121.92" x2="-2.54" y2="-119.38" width="0.1524" layer="91"/> +<junction x="-2.54" y="-119.38"/> +</segment> +</net> +<net name="N$55" class="0"> +<segment> +<pinref part="R62" gate="G$1" pin="2"/> +<pinref part="U$8" gate="G$1" pin="EN"/> +<wire x1="15.24" y1="-119.38" x2="22.86" y2="-119.38" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$56" class="0"> +<segment> +<pinref part="U$8" gate="G$1" pin="FB"/> +<wire x1="83.82" y1="-124.46" x2="88.9" y2="-124.46" width="0.1524" layer="91"/> +<pinref part="R65" gate="G$1" pin="1"/> +<wire x1="88.9" y1="-124.46" x2="88.9" y2="-121.92" width="0.1524" layer="91"/> +<pinref part="R66" gate="G$1" pin="2"/> +<wire x1="88.9" y1="-127" x2="88.9" y2="-124.46" width="0.1524" layer="91"/> +<junction x="88.9" y="-124.46"/> +</segment> +</net> +</nets> +</sheet> </sheets> <errors> <approved hash="102,4,226.06,222.25,VCC,3V3,,,,"/> |