diff options
| author | Fredrik Thulin <fredrik@thulin.net> | 2015-12-28 15:43:59 +0100 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2015-12-28 15:43:59 +0100 |
| commit | bcf07042a3d20c7b2fc044772126c9e9e8408070 (patch) | |
| tree | 06c59117075f0b89c3b05bd3e95e92b63a042f60 /eagle/alpha/rev02 | |
| parent | 5bda0b6805ad66f8b258bc738dd717fd7946bee2 (diff) | |
add SPI mux for FPGA cfg memory, and some other minor things.
Diffstat (limited to 'eagle/alpha/rev02')
| -rw-r--r-- | eagle/alpha/rev02/rev02.brd | 380 | ||||
| -rw-r--r-- | eagle/alpha/rev02/rev02.sch | 2655 |
2 files changed, 1734 insertions, 1301 deletions
diff --git a/eagle/alpha/rev02/rev02.brd b/eagle/alpha/rev02/rev02.brd index f7c471e..6a56d57 100644 --- a/eagle/alpha/rev02/rev02.brd +++ b/eagle/alpha/rev02/rev02.brd @@ -5087,6 +5087,97 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </package> </packages> </library> +<library name="74xx-eu"> +<description><b>TTL Devices, 74xx Series with European Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 +<li>http://icmaster.com/ViewCompare.asp +</ul> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="SO20W"> +<description><b>Wide Small Outline package</b> 300 mil</description> +<wire x1="6.1214" y1="3.7338" x2="-6.1214" y2="3.7338" width="0.1524" layer="51"/> +<wire x1="6.1214" y1="-3.7338" x2="6.5024" y2="-3.3528" width="0.1524" layer="21" curve="90"/> +<wire x1="-6.5024" y1="3.3528" x2="-6.1214" y2="3.7338" width="0.1524" layer="21" curve="-90"/> +<wire x1="6.1214" y1="3.7338" x2="6.5024" y2="3.3528" width="0.1524" layer="21" curve="-90"/> +<wire x1="-6.5024" y1="-3.3528" x2="-6.1214" y2="-3.7338" width="0.1524" layer="21" curve="90"/> +<wire x1="-6.1214" y1="-3.7338" x2="6.1214" y2="-3.7338" width="0.1524" layer="51"/> +<wire x1="6.5024" y1="-3.3528" x2="6.5024" y2="3.3528" width="0.1524" layer="21"/> +<wire x1="-6.5024" y1="3.3528" x2="-6.5024" y2="1.27" width="0.1524" layer="21"/> +<wire x1="-6.5024" y1="1.27" x2="-6.5024" y2="-1.27" width="0.1524" layer="21"/> +<wire x1="-6.5024" y1="-1.27" x2="-6.5024" y2="-3.3528" width="0.1524" layer="21"/> +<wire x1="-6.477" y1="-3.3782" x2="6.477" y2="-3.3782" width="0.0508" layer="21"/> +<wire x1="-6.5024" y1="1.27" x2="-6.5024" y2="-1.27" width="0.1524" layer="21" curve="-180"/> +<smd name="1" x="-5.715" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="2" x="-4.445" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="3" x="-3.175" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="4" x="-1.905" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="5" x="-0.635" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="6" x="0.635" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="7" x="1.905" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="8" x="3.175" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="13" x="3.175" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="14" x="1.905" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="15" x="0.635" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="16" x="-0.635" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="17" x="-1.905" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="18" x="-3.175" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="19" x="-4.445" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="20" x="-5.715" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="9" x="4.445" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="10" x="5.715" y="-5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="12" x="4.445" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<smd name="11" x="5.715" y="5.0292" dx="0.6604" dy="2.032" layer="1"/> +<text x="-3.81" y="-1.778" size="1.27" layer="27" ratio="10">>VALUE</text> +<text x="-6.858" y="-3.175" size="1.27" layer="25" ratio="10" rot="R90">>NAME</text> +<rectangle x1="-5.969" y1="-3.8608" x2="-5.461" y2="-3.7338" layer="51"/> +<rectangle x1="-5.969" y1="-5.334" x2="-5.461" y2="-3.8608" layer="51"/> +<rectangle x1="-4.699" y1="-3.8608" x2="-4.191" y2="-3.7338" layer="51"/> +<rectangle x1="-4.699" y1="-5.334" x2="-4.191" y2="-3.8608" layer="51"/> +<rectangle x1="-3.429" y1="-3.8608" x2="-2.921" y2="-3.7338" layer="51"/> +<rectangle x1="-3.429" y1="-5.334" x2="-2.921" y2="-3.8608" layer="51"/> +<rectangle x1="-2.159" y1="-3.8608" x2="-1.651" y2="-3.7338" layer="51"/> +<rectangle x1="-2.159" y1="-5.334" x2="-1.651" y2="-3.8608" layer="51"/> +<rectangle x1="-0.889" y1="-5.334" x2="-0.381" y2="-3.8608" layer="51"/> +<rectangle x1="-0.889" y1="-3.8608" x2="-0.381" y2="-3.7338" layer="51"/> +<rectangle x1="0.381" y1="-3.8608" x2="0.889" y2="-3.7338" layer="51"/> +<rectangle x1="0.381" y1="-5.334" x2="0.889" y2="-3.8608" layer="51"/> +<rectangle x1="1.651" y1="-3.8608" x2="2.159" y2="-3.7338" layer="51"/> +<rectangle x1="1.651" y1="-5.334" x2="2.159" y2="-3.8608" layer="51"/> +<rectangle x1="2.921" y1="-3.8608" x2="3.429" y2="-3.7338" layer="51"/> +<rectangle x1="2.921" y1="-5.334" x2="3.429" y2="-3.8608" layer="51"/> +<rectangle x1="-5.969" y1="3.8608" x2="-5.461" y2="5.334" layer="51"/> +<rectangle x1="-5.969" y1="3.7338" x2="-5.461" y2="3.8608" layer="51"/> +<rectangle x1="-4.699" y1="3.7338" x2="-4.191" y2="3.8608" layer="51"/> +<rectangle x1="-4.699" y1="3.8608" x2="-4.191" y2="5.334" layer="51"/> +<rectangle x1="-3.429" y1="3.7338" x2="-2.921" y2="3.8608" layer="51"/> +<rectangle x1="-3.429" y1="3.8608" x2="-2.921" y2="5.334" layer="51"/> +<rectangle x1="-2.159" y1="3.7338" x2="-1.651" y2="3.8608" layer="51"/> +<rectangle x1="-2.159" y1="3.8608" x2="-1.651" y2="5.334" layer="51"/> +<rectangle x1="-0.889" y1="3.7338" x2="-0.381" y2="3.8608" layer="51"/> +<rectangle x1="-0.889" y1="3.8608" x2="-0.381" y2="5.334" layer="51"/> +<rectangle x1="0.381" y1="3.7338" x2="0.889" y2="3.8608" layer="51"/> +<rectangle x1="0.381" y1="3.8608" x2="0.889" y2="5.334" layer="51"/> +<rectangle x1="1.651" y1="3.7338" x2="2.159" y2="3.8608" layer="51"/> +<rectangle x1="1.651" y1="3.8608" x2="2.159" y2="5.334" layer="51"/> +<rectangle x1="2.921" y1="3.7338" x2="3.429" y2="3.8608" layer="51"/> +<rectangle x1="2.921" y1="3.8608" x2="3.429" y2="5.334" layer="51"/> +<rectangle x1="4.191" y1="3.7338" x2="4.699" y2="3.8608" layer="51"/> +<rectangle x1="5.461" y1="3.7338" x2="5.969" y2="3.8608" layer="51"/> +<rectangle x1="4.191" y1="3.8608" x2="4.699" y2="5.334" layer="51"/> +<rectangle x1="5.461" y1="3.8608" x2="5.969" y2="5.334" layer="51"/> +<rectangle x1="4.191" y1="-3.8608" x2="4.699" y2="-3.7338" layer="51"/> +<rectangle x1="5.461" y1="-3.8608" x2="5.969" y2="-3.7338" layer="51"/> +<rectangle x1="4.191" y1="-5.334" x2="4.699" y2="-3.8608" layer="51"/> +<rectangle x1="5.461" y1="-5.334" x2="5.969" y2="-3.8608" layer="51"/> +</package> +</packages> +</library> </libraries> <attributes> </attributes> @@ -6649,21 +6740,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <attribute name="DIELECTRIC" value="X7R" x="53.086" y="1.524" size="1.778" layer="27" display="off"/> <attribute name="RATED_VOLTAGE" value="10V" x="53.086" y="1.524" size="1.778" layer="27" display="off"/> </element> -<element name="R6" library="resistor" package="R0402" value="10K" x="86.106" y="89.408"/> -<element name="R30" library="resistor" package="R0402" value="10K" x="85.598" y="88.138"/> -<element name="R31" library="resistor" package="R0402" value="10K" x="85.344" y="86.36"/> -<element name="U1" library="ON_Semiconductor-MC14551BDG" package="SOIC127P600X175-16N" value="MC14551BDG" x="91.186" y="87.376"> -<attribute name="MPN" value="MC14551BDG" x="78.232" y="106.172" size="1.778" layer="27" display="off"/> -<attribute name="OC_FARNELL" value="9665242" x="78.232" y="106.172" size="1.778" layer="27" display="off"/> -<attribute name="SUPPLIER" value="ON SEMICONDUCTOR" x="78.232" y="106.172" size="1.778" layer="27" display="off"/> -<attribute name="PACKAGE" value="SOIC-16" x="78.232" y="106.172" size="1.778" layer="27" display="off"/> -<attribute name="OC_NEWARK" value="71J5501" x="78.232" y="106.172" size="1.778" layer="27" display="off"/> -</element> -<element name="R32" library="resistor" package="R0603" value="15K" x="85.09" y="83.312"/> -<element name="C8" library="resistor" package="C0402" value="0.1 uF" x="85.344" y="84.582"> -<attribute name="RATED_VOLTAGE" value="10V" x="67.056" y="98.552" size="1.778" layer="27" display="off"/> -<attribute name="DIELECTRIC" value="X7R" x="67.056" y="98.552" size="1.778" layer="27" display="off"/> -</element> +<element name="R6" library="resistor" package="R0402" value="10K" x="89.916" y="93.218"/> +<element name="R30" library="resistor" package="R0402" value="10K" x="89.408" y="91.948"/> +<element name="R31" library="resistor" package="R0402" value="10K" x="89.154" y="90.17"/> <element name="JP8" library="jumper" package="JP1" value="" x="96.774" y="88.138"/> <element name="IC1" library="Alpha-IC" package="TSOP2-86L" value="IS45S32160F" x="-7.112" y="13.462"> <attribute name="MPN" value="IS45S32160F" x="-7.112" y="13.462" size="1.778" layer="27" display="off"/> @@ -6870,6 +6949,12 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <attribute name="RATED_VOLTAGE" value="25V" x="13.48" y="14.13" size="1.778" layer="27" rot="R90" display="off"/> <attribute name="DIELECTRIC" value="X7R" x="13.48" y="14.13" size="1.778" layer="27" rot="R90" display="off"/> </element> +<element name="IC5" library="74xx-eu" package="SO20W" value="74AC244DW" x="91.44" y="87.63" rot="R90"/> +<element name="C214" library="resistor" package="C0402" value="0.1uF" x="-1.27" y="-87.63"/> +<element name="R77" library="resistor" package="R0603" value="4.7k" x="-11.43" y="-93.98"/> +<element name="R80" library="resistor" package="R0603" value="4.7k" x="-11.43" y="-99.06"/> +<element name="R81" library="resistor" package="R0603" value="4.7k" x="-11.43" y="-104.14"/> +<element name="JP9" library="jumper" package="JP1" value="" x="-10.16" y="-109.22"/> </elements> <signals> <signal name="GND" class="1"> @@ -7490,10 +7575,6 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="LED12" pad="C"/> <contactref element="LED13" pad="C"/> <contactref element="LED14" pad="C"/> -<contactref element="U1" pad="8"/> -<contactref element="U1" pad="7"/> -<contactref element="R32" pad="1"/> -<contactref element="C8" pad="2"/> <contactref element="U$10" pad="10"/> <contactref element="U$10" pad="11"/> <contactref element="U$10" pad="22"/> @@ -7591,6 +7672,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="U$1" pad="170"/> <contactref element="U$1" pad="184"/> <contactref element="U$1" pad="202"/> +<contactref element="IC5" pad="10"/> +<contactref element="C214" pad="2"/> +<contactref element="R81" pad="2"/> <wire x1="156.298" y1="99.568" x2="151.55" y2="99.568" width="0" layer="19" extent="1-1"/> <wire x1="156.3996" y1="95.1992" x2="156.298" y2="99.568" width="0" layer="19" extent="1-1"/> <wire x1="147.5928" y1="93.7144" x2="151.55" y2="99.568" width="0" layer="19" extent="1-1"/> @@ -7718,11 +7802,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="144.2212" y1="18.6944" x2="145.4912" y2="18.6944" width="0" layer="19" extent="1-1"/> <wire x1="53.736" y1="1.524" x2="50.3936" y2="8.9916" width="0" layer="19" extent="1-1"/> <wire x1="145.4912" y1="28.1944" x2="145.4912" y2="18.6944" width="0" layer="19" extent="1-1"/> -<wire x1="155.9941" y1="26.0096" x2="145.4912" y2="28.1944" width="0" layer="19" extent="1-1"/> -<wire x1="156.1964" y1="22.4536" x2="155.9941" y2="26.0096" width="0" layer="19" extent="1-1"/> -<wire x1="157.4576" y1="18.4912" x2="156.1964" y2="22.4536" width="0" layer="19" extent="1-1"/> -<wire x1="155.9941" y1="32.1056" x2="155.9941" y2="26.0096" width="0" layer="19" extent="1-1"/> -<wire x1="13.48" y1="14.98" x2="23.7744" y2="11.5824" width="0" layer="19" extent="1-1"/> +<wire x1="13.35" y1="11.44" x2="23.7744" y2="11.5824" width="0" layer="19" extent="1-1"/> +<wire x1="11.27" y1="10.34" x2="13.35" y2="11.44" width="0" layer="19" extent="1-1"/> +<wire x1="13.48" y1="14.98" x2="13.35" y2="11.44" width="0" layer="19" extent="1-1"/> <wire x1="9.693" y1="18.826" x2="13.48" y2="14.98" width="0" layer="19" extent="1-1"/> <wire x1="7.874" y1="17.922" x2="9.693" y2="18.826" width="0" layer="19" extent="1-1"/> <wire x1="5.588" y1="17.36" x2="7.874" y2="17.922" width="0" layer="19" extent="1-1"/> @@ -7775,8 +7857,10 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="1.92" y1="-32.512" x2="-1.182" y2="-32.934" width="0" layer="19" extent="1-1"/> <wire x1="-13.042" y1="18.462" x2="-13.042" y2="8.462" width="0" layer="19" extent="1-1"/> <wire x1="-13.042" y1="21.462" x2="-13.042" y2="18.462" width="0" layer="19" extent="1-1"/> -<wire x1="13.35" y1="11.44" x2="1.666" y2="-69.85" width="0" layer="19" extent="1-1"/> -<wire x1="11.27" y1="10.34" x2="13.35" y2="11.44" width="0" layer="19" extent="1-1"/> +<wire x1="155.9941" y1="26.0096" x2="145.4912" y2="28.1944" width="0" layer="19" extent="1-1"/> +<wire x1="156.1964" y1="22.4536" x2="155.9941" y2="26.0096" width="0" layer="19" extent="1-1"/> +<wire x1="157.4576" y1="18.4912" x2="156.1964" y2="22.4536" width="0" layer="19" extent="1-1"/> +<wire x1="155.9941" y1="32.1056" x2="155.9941" y2="26.0096" width="0" layer="19" extent="1-1"/> <wire x1="35.688" y1="28.71" x2="39.0788" y2="17.0824" width="0" layer="19" extent="1-16"/> <wire x1="35.938" y1="38.55" x2="35.688" y2="28.71" width="0" layer="19" extent="1-1"/> <wire x1="40.0808" y1="47.2088" x2="35.938" y2="38.55" width="0" layer="19" extent="1-1"/> @@ -7980,15 +8064,14 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="87.8586" y1="96.647" x2="79.99" y2="96.894" width="0" layer="19" extent="1-1"/> <wire x1="96.178" y1="98.552" x2="87.8586" y2="96.647" width="0" layer="19" extent="1-1"/> <wire x1="97.878" y1="96.52" x2="96.178" y2="98.552" width="0" layer="19" extent="1-1"/> +<wire x1="96.4692" y1="93.345" x2="97.878" y2="96.52" width="0" layer="19" extent="1-1"/> <wire x1="82.268" y1="78.6892" x2="70.866" y2="78.486" width="0" layer="19" extent="1-1"/> -<wire x1="84.24" y1="83.312" x2="82.268" y2="78.6892" width="0" layer="19" extent="1-1"/> -<wire x1="85.994" y1="84.582" x2="84.24" y2="83.312" width="0" layer="19" extent="1-1"/> -<wire x1="88.7222" y1="84.201" x2="85.994" y2="84.582" width="0" layer="19" extent="1-1"/> -<wire x1="88.7222" y1="82.931" x2="88.7222" y2="84.201" width="0" layer="19" extent="1-1"/> <wire x1="112.5474" y1="100.203" x2="97.878" y2="96.52" width="0" layer="19" extent="1-1"/> <wire x1="114.72" y1="98.552" x2="112.5474" y2="100.203" width="0" layer="19" extent="1-1"/> <wire x1="116.42" y1="100.076" x2="114.72" y2="98.552" width="0" layer="19" extent="1-1"/> <wire x1="116.42" y1="96.52" x2="114.72" y2="98.552" width="0" layer="19" extent="1-1"/> +<wire x1="-0.62" y1="-87.63" x2="1.666" y2="-69.85" width="0" layer="19" extent="1-1"/> +<wire x1="-10.58" y1="-104.14" x2="-0.62" y2="-87.63" width="0" layer="19" extent="1-1"/> </signal> <signal name="AMPLIFIED"> <contactref element="U2" pad="2"/> @@ -8145,8 +8228,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="109.1414" y1="40.9678" x2="109.728" y2="41.5544" width="0.3048" layer="1"/> <wire x1="109.728" y1="41.5544" x2="111.3176" y2="41.5544" width="0.3048" layer="1"/> <wire x1="111.3176" y1="41.5544" x2="111.3248" y2="41.5472" width="0.3048" layer="1"/> -<contactref element="U$1" pad="69"/> -<wire x1="104.6484" y1="40.9678" x2="109.1414" y2="40.9678" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="65"/> +<wire x1="104.6484" y1="38.9612" x2="109.1414" y2="40.9678" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$18"> <contactref element="LED6" pad="A"/> @@ -8158,8 +8241,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <signal name="ARM_LED2"> <contactref element="R8" pad="6"/> <wire x1="111.32" y1="40.4598" x2="111.3248" y2="40.455" width="0.3048" layer="1"/> -<contactref element="U$1" pad="68"/> -<wire x1="104.6484" y1="40.4598" x2="111.3248" y2="40.455" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="66"/> +<wire x1="104.6484" y1="39.4692" x2="111.3248" y2="40.455" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$19"> <contactref element="LED7" pad="A"/> @@ -8188,8 +8271,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="108.7652" y1="39.4692" x2="109.728" y2="38.5064" width="0.3048" layer="1"/> <wire x1="109.728" y1="38.5064" x2="111.3176" y2="38.5064" width="0.3048" layer="1"/> <wire x1="111.3176" y1="38.5064" x2="111.3248" y2="38.4992" width="0.3048" layer="1"/> -<contactref element="U$1" pad="66"/> -<wire x1="104.6484" y1="39.4692" x2="108.7652" y2="39.4692" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="68"/> +<wire x1="104.6484" y1="40.4598" x2="108.7652" y2="39.4692" width="0" layer="19" extent="1-1"/> </signal> <signal name="AGND"> <polygon width="0.4064" layer="16" orphans="yes"> @@ -8934,14 +9017,10 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="R11" pad="2"/> <contactref element="LED10" pad="A"/> <contactref element="LED9" pad="A"/> -<contactref element="C47" pad="1"/> -<contactref element="C48" pad="1"/> <wire x1="110.0156" y1="8.7148" x2="110.8684" y2="8.7148" width="0.254" layer="1"/> <wire x1="110.8684" y1="8.7148" x2="111.5568" y2="8.0264" width="0.254" layer="1"/> <wire x1="111.5568" y1="8.0264" x2="111.5568" y2="7.7216" width="0.3048" layer="1"/> <via x="111.5568" y="7.7216" extent="1-16" drill="0.6" shape="square"/> -<wire x1="111.5568" y1="7.7216" x2="113.65" y2="7.7216" width="0.3048" layer="16"/> -<wire x1="113.45" y1="7.7216" x2="111.5568" y2="7.7216" width="0.4064" layer="1"/> <polygon width="0.4064" layer="2" isolate="0.3048" rank="2"> <vertex x="91.1352" y="1.016"/> <vertex x="91.1352" y="18.6944"/> @@ -8984,6 +9063,10 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="FB1" pad="1"/> <via x="92.3544" y="16.5608" extent="1-16" drill="0.6" shape="square"/> <wire x1="94.6404" y1="16.5608" x2="92.3544" y2="16.5608" width="0.6096" layer="1"/> +<contactref element="C47" pad="1"/> +<contactref element="C48" pad="1"/> +<wire x1="113.65" y1="7.7216" x2="113.45" y2="7.7216" width="0" layer="19" extent="1-16"/> +<wire x1="111.5568" y1="7.7216" x2="113.45" y2="7.7216" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$22"> <contactref element="C43" pad="2"/> @@ -9048,12 +9131,6 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="95.9868" y1="9.1032" x2="95.7868" y2="6.6648" width="0.6096" layer="1"/> <wire x1="95.8596" y1="4.3688" x2="95.9868" y2="4.4608" width="0.6096" layer="1"/> <wire x1="95.9868" y1="4.4608" x2="95.7868" y2="6.6648" width="0.6096" layer="1"/> -<contactref element="C183" pad="1"/> -<contactref element="C184" pad="1"/> -<contactref element="FB4" pad="2"/> -<wire x1="124.572" y1="20.828" x2="131.638" y2="28.194" width="0" layer="19" extent="1-1"/> -<wire x1="123.444" y1="18.542" x2="124.572" y2="20.828" width="0" layer="19" extent="1-1"/> -<wire x1="108.204" y1="12.9032" x2="123.444" y2="18.542" width="0" layer="19" extent="1-1"/> <wire x1="96.0868" y1="9.1032" x2="96.784" y2="9.1032" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_VPLL"> @@ -9392,10 +9469,6 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="84.1502" y1="9.525" x2="84.7344" y2="8.9408" width="0.4064" layer="1"/> <wire x1="84.7344" y1="8.9408" x2="84.7344" y2="3.7846" width="0.4064" layer="1"/> <wire x1="84.7344" y1="3.7846" x2="85.5472" y2="2.9718" width="0.4064" layer="1"/> -<contactref element="U1" pad="16"/> -<contactref element="C8" pad="1"/> -<wire x1="84.694" y1="84.582" x2="93.6498" y2="91.821" width="0" layer="19" extent="1-1"/> -<wire x1="68.9102" y1="17.145" x2="84.694" y2="84.582" width="0" layer="19" extent="1-1"/> </signal> <signal name="AVR_GPIO_11"> <contactref element="U3" pad="22"/> @@ -9409,6 +9482,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="67.056" y1="21.4376" x2="67.056" y2="21.7424" width="0.4064" layer="1"/> <wire x1="67.3608" y1="21.4376" x2="67.056" y2="21.7424" width="0.3048" layer="16"/> <wire x1="65.7098" y1="20.3962" x2="67.056" y2="21.7424" width="0.4064" layer="1"/> +<contactref element="U$1" pad="9"/> +<wire x1="83.3124" y1="29.5652" x2="81.3312" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="AVR_GPIO_10"> <contactref element="U3" pad="20"/> @@ -9454,13 +9529,11 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="87.4268" y1="10.7696" x2="87.4014" y2="10.795" width="0.3048" layer="1"/> <contactref element="R6" pad="2"/> <contactref element="U$1" pad="47"/> -<wire x1="100.3304" y1="31.138" x2="86.756" y2="89.408" width="0" layer="19" extent="1-1"/> +<wire x1="100.3304" y1="31.138" x2="90.566" y2="93.218" width="0" layer="19" extent="1-1"/> <wire x1="100.3304" y1="20.8792" x2="100.3304" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="RTC_SCL"> <contactref element="U6" pad="6"/> -<contactref element="U$1" pad="48"/> -<wire x1="100.813" y1="31.138" x2="100.813" y2="20.4474" width="0.3048" layer="1"/> <wire x1="100.813" y1="20.4474" x2="99.06" y2="18.6944" width="0.3048" layer="1"/> <wire x1="99.06" y1="18.6944" x2="91.7448" y2="18.6944" width="0.3048" layer="1"/> <wire x1="91.7448" y1="18.6944" x2="90.2208" y2="17.1704" width="0.3048" layer="1"/> @@ -9469,12 +9542,12 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="89.0016" y1="9.5504" x2="87.4268" y2="9.5504" width="0.3048" layer="1"/> <wire x1="87.4268" y1="9.5504" x2="87.4014" y2="9.525" width="0.3048" layer="1"/> <contactref element="R30" pad="2"/> -<wire x1="100.813" y1="31.138" x2="86.248" y2="88.138" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="48"/> +<wire x1="100.813" y1="31.138" x2="90.058" y2="91.948" width="0" layer="19" extent="1-1"/> +<wire x1="100.813" y1="20.4474" x2="100.813" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="RTC_SDA"> <contactref element="U6" pad="5"/> -<contactref element="U$1" pad="49"/> -<wire x1="101.321" y1="31.138" x2="101.321" y2="20.041" width="0.3048" layer="1"/> <wire x1="101.321" y1="20.041" x2="99.3648" y2="18.0848" width="0.3048" layer="1"/> <wire x1="99.3648" y1="18.0848" x2="92.0496" y2="18.0848" width="0.3048" layer="1"/> <wire x1="92.0496" y1="18.0848" x2="90.8304" y2="16.8656" width="0.3048" layer="1"/> @@ -9483,7 +9556,9 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="89.0016" y1="8.3312" x2="87.4776" y2="8.3312" width="0.3048" layer="1"/> <wire x1="87.4776" y1="8.3312" x2="87.4014" y2="8.255" width="0.3048" layer="1"/> <contactref element="R31" pad="2"/> -<wire x1="101.321" y1="31.138" x2="85.994" y2="86.36" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="49"/> +<wire x1="101.321" y1="31.138" x2="89.804" y2="90.17" width="0" layer="19" extent="1-1"/> +<wire x1="101.321" y1="20.041" x2="101.321" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$12"> <polygon width="0.4064" layer="2"> @@ -9995,6 +10070,10 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="U$1" pad="6"/> <contactref element="U$1" pad="41"/> <contactref element="U$1" pad="203"/> +<contactref element="IC5" pad="20"/> +<contactref element="C214" pad="1"/> +<contactref element="R77" pad="2"/> +<contactref element="R80" pad="2"/> <wire x1="110.0328" y1="53.1368" x2="158.902" y2="55.626" width="0" layer="19" extent="1-1"/> <wire x1="79.8072" y1="31.138" x2="79.8576" y2="31.1884" width="0" layer="19" extent="1-1"/> <wire x1="75.4892" y1="34.9734" x2="75.819" y2="34.8084" width="0" layer="19" extent="1-16"/> @@ -10175,7 +10254,11 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <wire x1="112.5474" y1="98.933" x2="106.4006" y2="97.663" width="0" layer="19" extent="1-1"/> <wire x1="114.72" y1="96.52" x2="112.5474" y2="98.933" width="0" layer="19" extent="1-1"/> <wire x1="116.42" y1="98.552" x2="114.72" y2="96.52" width="0" layer="19" extent="1-1"/> -<wire x1="79.728" y1="78.6892" x2="79.59" y2="94.996" width="0" layer="19" extent="1-1"/> +<wire x1="86.4108" y1="81.915" x2="79.59" y2="94.996" width="0" layer="19" extent="1-1"/> +<wire x1="79.728" y1="78.6892" x2="86.4108" y2="81.915" width="0" layer="19" extent="1-1"/> +<wire x1="-1.92" y1="-87.63" x2="0.366" y2="-69.85" width="0" layer="19" extent="1-1"/> +<wire x1="-10.58" y1="-93.98" x2="-1.92" y2="-87.63" width="0" layer="19" extent="1-1"/> +<wire x1="-10.58" y1="-99.06" x2="-10.58" y2="-93.98" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_CLK"> <contactref element="U7" pad="W11"/> @@ -10184,29 +10267,29 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FPGA_PROM_SCLK"> <contactref element="IC3" pad="6"/> -<contactref element="U1" pad="11"/> -<wire x1="93.6498" y1="85.471" x2="94.0054" y2="97.917" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="16"/> +<contactref element="IC5" pad="7"/> +<wire x1="96.4692" y1="89.535" x2="94.0054" y2="97.917" width="0" layer="19" extent="1-1"/> +<wire x1="86.4108" y1="86.995" x2="96.4692" y2="89.535" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_MOSI"> <contactref element="IC3" pad="5"/> -<contactref element="U1" pad="6"/> -<wire x1="88.7222" y1="85.471" x2="94.0054" y2="96.647" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="5"/> +<contactref element="IC5" pad="14"/> +<wire x1="96.4692" y1="86.995" x2="94.0054" y2="96.647" width="0" layer="19" extent="1-1"/> +<wire x1="86.4108" y1="89.535" x2="96.4692" y2="86.995" width="0" layer="19" extent="1-1"/> </signal> <signal name="KSM_PROM_CS_N"> -<contactref element="IC3" pad="1"/> -<contactref element="R9" pad="1"/> -<contactref element="U1" pad="2"/> <contactref element="IC4" pad="1"/> <contactref element="R73" pad="2"/> <wire x1="112.5474" y1="96.393" x2="114.72" y2="100.076" width="0" layer="19" extent="1-1"/> -<wire x1="96.178" y1="100.584" x2="112.5474" y2="96.393" width="0" layer="19" extent="1-1"/> -<wire x1="87.8586" y1="100.457" x2="96.178" y2="100.584" width="0" layer="19" extent="1-1"/> -<wire x1="88.7222" y1="90.551" x2="87.8586" y2="100.457" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_MISO"> <contactref element="IC3" pad="2"/> -<contactref element="U1" pad="15"/> -<wire x1="93.6498" y1="90.551" x2="87.8586" y2="99.187" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="8"/> +<contactref element="IC5" pad="17"/> +<wire x1="96.4692" y1="90.805" x2="87.8586" y2="99.187" width="0" layer="19" extent="1-1"/> +<wire x1="86.4108" y1="85.725" x2="96.4692" y2="90.805" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_PROM_W_N"> <contactref element="IC3" pad="3"/> @@ -10227,23 +10310,23 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FPGA_IRQ_N_0"> <contactref element="U7" pad="F14"/> -<contactref element="U$1" pad="175"/> -<wire x1="55.0808" y1="55.2088" x2="75.4892" y2="49.4768" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="122"/> +<wire x1="55.0808" y1="55.2088" x2="94.3106" y2="60.2972" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_IRQ_N_1"> <contactref element="U7" pad="F16"/> -<contactref element="U$1" pad="174"/> -<wire x1="55.0808" y1="53.2088" x2="75.4892" y2="49.9594" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="123"/> +<wire x1="55.0808" y1="53.2088" x2="93.828" y2="60.2972" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_IRQ_N_2"> <contactref element="U7" pad="E17"/> -<contactref element="U$1" pad="123"/> -<wire x1="56.0808" y1="52.2088" x2="93.828" y2="60.2972" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="174"/> +<wire x1="56.0808" y1="52.2088" x2="75.4892" y2="49.9594" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_IRQ_N_3"> <contactref element="U7" pad="C14"/> -<contactref element="U$1" pad="122"/> -<wire x1="58.0808" y1="55.2088" x2="94.3106" y2="60.2972" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="175"/> +<wire x1="58.0808" y1="55.2088" x2="75.4892" y2="49.4768" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_GPIO_A_0"> <contactref element="U7" pad="C15"/> @@ -10382,8 +10465,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <signal name="FPGA_PROGRAM_B"> <contactref element="U7" pad="N12"/> <contactref element="R25" pad="1"/> -<contactref element="U$1" pad="177"/> -<wire x1="48.0808" y1="57.2088" x2="75.4892" y2="48.4608" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="120"/> +<wire x1="48.0808" y1="57.2088" x2="95.3266" y2="60.2972" width="0" layer="19" extent="1-1"/> <wire x1="10.326" y1="26.416" x2="48.0808" y2="57.2088" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_DONE_INT"> @@ -10453,8 +10536,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <signal name="FPGA_INIT_B"> <contactref element="Q6" pad="1"/> <contactref element="R29" pad="2"/> -<contactref element="U$1" pad="176"/> -<wire x1="15.074" y1="26.416" x2="75.4892" y2="48.9688" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="119"/> +<wire x1="15.074" y1="26.416" x2="95.8092" y2="60.2972" width="0" layer="19" extent="1-1"/> <wire x1="4.13" y1="25.316" x2="15.074" y2="26.416" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$34"> @@ -10464,8 +10547,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FPGA_DONE"> <contactref element="R34" pad="1"/> -<contactref element="U$1" pad="119"/> -<wire x1="4.23" y1="37.592" x2="95.8092" y2="60.2972" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="177"/> +<wire x1="4.23" y1="37.592" x2="75.4892" y2="48.4608" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$35"> <contactref element="U$5" pad="P$30"/> @@ -10862,8 +10945,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="U$9" pad="7"/> <contactref element="JP2" pad="1"/> <contactref element="R22" pad="2"/> -<wire x1="10.343" y1="18.826" x2="6.51" y2="10.49" width="0" layer="19" extent="1-1"/> -<wire x1="13.97" y1="18.684" x2="10.343" y2="18.826" width="0" layer="19" extent="1-1"/> +<wire x1="10.343" y1="18.826" x2="13.97" y2="18.684" width="0" layer="19" extent="1-1"/> +<wire x1="6.51" y1="10.49" x2="10.343" y2="18.826" width="0" layer="19" extent="1-1"/> </signal> <signal name="VIN"> </signal> @@ -10871,16 +10954,18 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FT_RTS"> <contactref element="U$3" pad="15"/> -<contactref element="U$1" pad="44"/> -<wire x1="101.5156" y1="12.2148" x2="98.8064" y2="31.138" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="43"/> +<wire x1="101.5156" y1="12.2148" x2="98.3238" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_CTS"> <contactref element="U$3" pad="16"/> -<contactref element="U$1" pad="43"/> -<wire x1="101.5156" y1="11.7148" x2="98.3238" y2="31.138" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="44"/> +<wire x1="101.5156" y1="11.7148" x2="98.8064" y2="31.138" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_DTR"> <contactref element="U$3" pad="17"/> +<contactref element="U$1" pad="53"/> +<wire x1="101.5156" y1="11.2148" x2="104.6484" y2="32.9668" width="0" layer="19" extent="1-1"/> </signal> <signal name="VCC"> <contactref element="JP5" pad="1"/> @@ -10888,57 +10973,47 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="R30" pad="1"/> <contactref element="R31" pad="1"/> <contactref element="R6" pad="1"/> -<wire x1="84.948" y1="88.138" x2="85.456" y2="89.408" width="0" layer="19" extent="1-1"/> -<wire x1="84.694" y1="86.36" x2="84.948" y2="88.138" width="0" layer="19" extent="1-1"/> -<wire x1="56.6928" y1="2.9718" x2="84.694" y2="86.36" width="0" layer="19" extent="1-1"/> +<wire x1="88.758" y1="91.948" x2="89.266" y2="93.218" width="0" layer="19" extent="1-1"/> +<wire x1="88.504" y1="90.17" x2="88.758" y2="91.948" width="0" layer="19" extent="1-1"/> +<wire x1="56.6928" y1="2.9718" x2="88.504" y2="90.17" width="0" layer="19" extent="1-1"/> <wire x1="52.436" y1="1.524" x2="56.6928" y2="2.9718" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_CFG_SCLK"> -<contactref element="U1" pad="13"/> <contactref element="U7" pad="L12"/> -<wire x1="50.0808" y1="57.2088" x2="93.6498" y2="88.011" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="13"/> +<wire x1="50.0808" y1="57.2088" x2="86.4108" y2="90.805" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_CFG_MOSI"> -<contactref element="U1" pad="5"/> <contactref element="U7" pad="P22"/> -<wire x1="47.0808" y1="47.2088" x2="88.7222" y2="86.741" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="15"/> +<wire x1="47.0808" y1="47.2088" x2="86.4108" y2="88.265" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_CFG_CS_N"> -<contactref element="U1" pad="4"/> <contactref element="U7" pad="T19"/> -<wire x1="45.0808" y1="50.2088" x2="88.7222" y2="88.011" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="11"/> +<wire x1="45.0808" y1="50.2088" x2="86.4108" y2="93.345" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_CFG_MISO"> -<contactref element="U1" pad="14"/> <contactref element="U7" pad="R22"/> -<wire x1="46.0808" y1="47.2088" x2="93.6498" y2="89.281" width="0" layer="19" extent="1-1"/> -</signal> -<signal name="ARM_FPGA_CFG_CS_N"> -<contactref element="U1" pad="3"/> +<contactref element="IC5" pad="3"/> +<wire x1="46.0808" y1="47.2088" x2="96.4692" y2="84.455" width="0" layer="19" extent="1-1"/> </signal> <signal name="ARM_FPGA_CFG_MOSI"> -<contactref element="U1" pad="10"/> <contactref element="U$1" pad="107"/> -<wire x1="101.829" y1="60.2972" x2="93.6498" y2="84.201" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="6"/> +<wire x1="101.829" y1="60.2972" x2="96.4692" y2="88.265" width="0" layer="19" extent="1-1"/> </signal> <signal name="ARM_FPGA_CFG_MISO"> -<contactref element="U1" pad="1"/> <contactref element="U$1" pad="106"/> -<wire x1="102.3116" y1="60.2972" x2="88.7222" y2="91.821" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="12"/> +<wire x1="102.3116" y1="60.2972" x2="86.4108" y2="92.075" width="0" layer="19" extent="1-1"/> </signal> <signal name="ARM_FPGA_CFG_SCLK"> -<contactref element="U1" pad="12"/> <contactref element="U$1" pad="105"/> -<wire x1="102.8196" y1="60.2972" x2="93.6498" y2="86.741" width="0" layer="19" extent="1-1"/> -</signal> -<signal name="N$3"> -<contactref element="U1" pad="9"/> -<contactref element="R32" pad="2"/> -<contactref element="JP8" pad="1"/> -<wire x1="93.6498" y1="82.931" x2="96.774" y2="86.868" width="0" layer="19" extent="1-1"/> -<wire x1="85.94" y1="83.312" x2="93.6498" y2="82.931" width="0" layer="19" extent="1-1"/> +<contactref element="IC5" pad="4"/> +<wire x1="102.8196" y1="60.2972" x2="96.4692" y2="85.725" width="0" layer="19" extent="1-1"/> </signal> -<signal name="ARM_FPGA_CFG_CONTROL"> +<signal name="FPGA_CFG_CTRL_ARM_ENA"> <contactref element="JP8" pad="2"/> <contactref element="U$1" pad="118"/> <wire x1="96.3172" y1="60.2972" x2="96.774" y2="89.408" width="0" layer="19" extent="1-1"/> @@ -11011,8 +11086,6 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="R69" pad="2"/> <contactref element="LED17" pad="A"/> <contactref element="LED18" pad="A"/> -<contactref element="C181" pad="1"/> -<contactref element="C182" pad="1"/> <contactref element="U$10" pad="46"/> <contactref element="U$10" pad="24"/> <contactref element="U$10" pad="12"/> @@ -11021,6 +11094,8 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="C189" pad="1"/> <contactref element="FB4" pad="1"/> <contactref element="FB3" pad="1"/> +<contactref element="C181" pad="1"/> +<contactref element="C182" pad="1"/> <wire x1="128.128" y1="32.258" x2="129.98" y2="29.166" width="0" layer="19" extent="1-1"/> <wire x1="124.826" y1="32.512" x2="128.128" y2="32.258" width="0" layer="19" extent="1-1"/> <wire x1="121.48" y1="28.166" x2="124.826" y2="32.512" width="0" layer="19" extent="1-1"/> @@ -11056,6 +11131,12 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FT_MGMT_VPHY"> <contactref element="U$10" pad="3"/> +<contactref element="C183" pad="1"/> +<contactref element="C184" pad="1"/> +<contactref element="FB4" pad="2"/> +<wire x1="123.98" y1="22.166" x2="131.638" y2="28.194" width="0" layer="19" extent="1-1"/> +<wire x1="124.572" y1="20.828" x2="123.98" y2="22.166" width="0" layer="19" extent="1-1"/> +<wire x1="123.444" y1="18.542" x2="124.572" y2="20.828" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_MGMT_TXD"> <contactref element="U$10" pad="13"/> @@ -11069,16 +11150,18 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </signal> <signal name="FT_MGMT_RTS"> <contactref element="U$10" pad="15"/> -<contactref element="U$1" pad="146"/> -<wire x1="82.3218" y1="60.2972" x2="129.98" y2="24.666" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="145"/> +<wire x1="82.8298" y1="60.2972" x2="129.98" y2="24.666" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_MGMT_CTS"> <contactref element="U$10" pad="16"/> -<contactref element="U$1" pad="145"/> -<wire x1="82.8298" y1="60.2972" x2="129.98" y2="25.166" width="0" layer="19" extent="1-1"/> +<contactref element="U$1" pad="146"/> +<wire x1="82.3218" y1="60.2972" x2="129.98" y2="25.166" width="0" layer="19" extent="1-1"/> </signal> <signal name="FT_MGMT_DTR"> <contactref element="U$10" pad="17"/> +<contactref element="U$1" pad="142"/> +<wire x1="84.3284" y1="60.2972" x2="129.98" y2="25.666" width="0" layer="19" extent="1-1"/> </signal> <signal name="FMC_SDCKE0"> <contactref element="IC1" pad="67"/> @@ -11175,24 +11258,53 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <contactref element="R76" pad="2"/> <contactref element="Q1" pad="1"/> <contactref element="R75" pad="1"/> -<wire x1="9.37" y1="10.34" x2="13.51" y2="10.33" width="0" layer="19" extent="1-1"/> -<wire x1="12.05" y1="11.44" x2="9.37" y2="10.34" width="0" layer="19" extent="1-1"/> +<wire x1="12.05" y1="11.44" x2="13.51" y2="10.33" width="0" layer="19" extent="1-1"/> +<wire x1="9.37" y1="10.34" x2="12.05" y2="11.44" width="0" layer="19" extent="1-1"/> </signal> <signal name="N$14"> <contactref element="Q1" pad="3"/> <contactref element="JP2" pad="2"/> -<wire x1="10.32" y1="12.54" x2="6.51" y2="13.03" width="0" layer="19" extent="1-1"/> +<wire x1="6.51" y1="13.03" x2="10.32" y2="12.54" width="0" layer="19" extent="1-1"/> </signal> <signal name="FPGA_ENTROPY_DISABLE"> <contactref element="R76" pad="1"/> <contactref element="U7" pad="B18"/> <wire x1="12.21" y1="10.33" x2="59.0808" y2="51.2088" width="0" layer="19" extent="1-1"/> </signal> -<signal name="SDIO_D0"> -<contactref element="U$1" pad="140"/> +<signal name="ARM_FPGA_CFG_CS_N"> +<contactref element="IC5" pad="2"/> +<contactref element="U$1" pad="104"/> +<wire x1="104.6484" y1="58.4684" x2="96.4692" y2="83.185" width="0" layer="19" extent="1-1"/> </signal> -<signal name="SDIO_D1"> -<contactref element="U$1" pad="141"/> +<signal name="SPI_A_TRISTATE"> +<contactref element="IC5" pad="1"/> +<contactref element="R80" pad="1"/> +<contactref element="JP8" pad="1"/> +<wire x1="96.4692" y1="81.915" x2="96.774" y2="86.868" width="0" layer="19" extent="1-1"/> +<wire x1="-12.28" y1="-99.06" x2="96.4692" y2="81.915" width="0" layer="19" extent="1-1"/> +</signal> +<signal name="SPI_B_TRISTATE"> +<contactref element="IC5" pad="19"/> +<contactref element="R81" pad="1"/> +<contactref element="JP9" pad="1"/> +<wire x1="-12.28" y1="-104.14" x2="86.4108" y2="83.185" width="0" layer="19" extent="1-1"/> +<wire x1="-10.16" y1="-110.49" x2="-12.28" y2="-104.14" width="0" layer="19" extent="1-1"/> +</signal> +<signal name="FPGA_PROM_CS_N"> +<contactref element="IC3" pad="1"/> +<contactref element="R9" pad="1"/> +<contactref element="IC5" pad="9"/> +<contactref element="IC5" pad="18"/> +<contactref element="R77" pad="1"/> +<wire x1="87.8586" y1="100.457" x2="96.178" y2="100.584" width="0" layer="19" extent="1-1"/> +<wire x1="96.4692" y1="92.075" x2="96.178" y2="100.584" width="0" layer="19" extent="1-1"/> +<wire x1="86.4108" y1="84.455" x2="96.4692" y2="92.075" width="0" layer="19" extent="1-1"/> +<wire x1="-12.28" y1="-93.98" x2="86.4108" y2="84.455" width="0" layer="19" extent="1-1"/> +</signal> +<signal name="FPGA_CFG_CTRL_FPGA_DIS"> +<contactref element="JP9" pad="2"/> +<contactref element="U$1" pad="95"/> +<wire x1="-10.16" y1="-107.95" x2="104.6484" y2="53.9726" width="0" layer="19" extent="1-1"/> </signal> <signal name="SDIO_CK"> <contactref element="U$1" pad="163"/> @@ -11206,6 +11318,12 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <signal name="SDIO_D2"> <contactref element="U$1" pad="161"/> </signal> +<signal name="SDIO_D0"> +<contactref element="U$1" pad="140"/> +</signal> +<signal name="SDIO_D1"> +<contactref element="U$1" pad="141"/> +</signal> </signals> <errors> <approved hash="18,30,75340d2b0d22753d"/> diff --git a/eagle/alpha/rev02/rev02.sch b/eagle/alpha/rev02/rev02.sch index cc8e74b..007f997 100644 --- a/eagle/alpha/rev02/rev02.sch +++ b/eagle/alpha/rev02/rev02.sch @@ -19134,33 +19134,6 @@ Epson Toyocom FCC-255</description> <pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/> <pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/> </symbol> -<symbol name="FRAME_A3"> -<wire x1="288.29" y1="3.81" x2="383.54" y2="3.81" width="0.1016" layer="94"/> -<wire x1="383.54" y1="19.05" x2="383.54" y2="24.13" width="0.1016" layer="94"/> -<wire x1="383.54" y1="3.81" x2="383.54" y2="8.89" width="0.1016" layer="94"/> -<wire x1="383.54" y1="8.89" x2="383.54" y2="13.97" width="0.1016" layer="94"/> -<wire x1="383.54" y1="13.97" x2="383.54" y2="19.05" width="0.1016" layer="94"/> -<wire x1="383.54" y1="19.05" x2="383.54" y2="36.83" width="0.1016" layer="94"/> -<wire x1="297.18" y1="3.81" x2="297.18" y2="8.89" width="0.1016" layer="94"/> -<wire x1="297.18" y1="8.89" x2="297.18" y2="13.97" width="0.1016" layer="94"/> -<wire x1="297.18" y1="13.97" x2="297.18" y2="19.05" width="0.1016" layer="94"/> -<wire x1="297.18" y1="19.05" x2="297.18" y2="36.83" width="0.1016" layer="94"/> -<wire x1="297.18" y1="36.83" x2="383.54" y2="36.83" width="0.1016" layer="94"/> -<wire x1="341.63" y1="13.97" x2="341.63" y2="8.89" width="0.1016" layer="94"/> -<wire x1="341.63" y1="8.89" x2="383.54" y2="8.89" width="0.1016" layer="94"/> -<wire x1="341.63" y1="8.89" x2="297.18" y2="8.89" width="0.1016" layer="94"/> -<wire x1="297.18" y1="13.97" x2="341.63" y2="13.97" width="0.1016" layer="94"/> -<wire x1="341.63" y1="13.97" x2="383.54" y2="13.97" width="0.1016" layer="94"/> -<wire x1="297.18" y1="19.05" x2="383.54" y2="19.05" width="0.1016" layer="94"/> -<wire x1="341.63" y1="8.89" x2="341.63" y2="3.81" width="0.1016" layer="94"/> -<text x="298.45" y="15.24" size="2.54" layer="94" font="vector">>DRAWING_NAME</text> -<text x="298.45" y="10.16" size="2.286" layer="94" font="vector">>LAST_DATE_TIME</text> -<text x="357.505" y="10.16" size="2.54" layer="94" font="vector">>SHEET</text> -<text x="343.916" y="10.033" size="2.54" layer="94" font="vector">Sheet:</text> -<text x="343.916" y="4.953" size="2.54" layer="94" font="vector">www.microbuilder.eu</text> -<text x="298.45" y="5.08" size="2.54" layer="94" font="vector">Drawing:</text> -<frame x1="0" y1="0" x2="387.35" y2="260.35" columns="8" rows="5" layer="94"/> -</symbol> </symbols> <devicesets> <deviceset name="FERRITE" prefix="FB" uservalue="yes"> @@ -19355,20 +19328,6 @@ Epson Toyocom FCC-255</description> </device> </devices> </deviceset> -<deviceset name="FRAME_A3" prefix="FRAME" uservalue="yes"> -<description><b>FRAME</b><p> -DIN A3, landscape with location and doc. field</description> -<gates> -<gate name="G$1" symbol="FRAME_A3" x="0" y="0"/> -</gates> -<devices> -<device name=""> -<technologies> -<technology name=""/> -</technologies> -</device> -</devices> -</deviceset> </devicesets> </library> <library name="transistor-npn"> @@ -34605,7 +34564,7 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> <pin name="DQ7" x="30.48" y="33.02" length="short" rot="R180"/> <pin name="VDD@15" x="-12.7" y="58.42" length="short" direction="pwr" rot="R270"/> <pin name="DQM0" x="30.48" y="-33.02" length="short" rot="R180"/> -<pin name="!WE" x="-30.48" y="-48.26" length="short" direction="nc"/> +<pin name="!WE" x="-30.48" y="-48.26" length="short" direction="in"/> <pin name="!CAS" x="-30.48" y="5.08" length="short"/> <pin name="!RAS" x="-30.48" y="2.54" length="short"/> <pin name="!CS" x="-30.48" y="-35.56" length="short" direction="in"/> @@ -34680,96 +34639,96 @@ Auto generated by <i>make-symbol-device-package-bsdl.ulp Rev. 44</i> </symbol> <symbol name="STM32F429_LQFP-208_IO"> <description>STM32 ARM GPIO</description> -<wire x1="-38.1" y1="88.9" x2="35.56" y2="88.9" width="0.254" layer="94"/> -<wire x1="35.56" y1="88.9" x2="35.56" y2="-71.12" width="0.254" layer="94"/> -<wire x1="35.56" y1="-71.12" x2="-38.1" y2="-71.12" width="0.254" layer="94"/> -<wire x1="-38.1" y1="-71.12" x2="-38.1" y2="88.9" width="0.254" layer="94"/> -<pin name="PI8" x="38.1" y="30.48" length="short" rot="R180"/> -<pin name="PC13" x="-40.64" y="-58.42" length="short"/> -<pin name="PC14/OSC32_IN" x="-40.64" y="-60.96" length="short"/> -<pin name="PC15/OSC32_OUT" x="-40.64" y="-63.5" length="short"/> -<pin name="PI11" x="38.1" y="27.94" length="short" rot="R180"/> -<pin name="PI12" x="38.1" y="25.4" length="short" rot="R180"/> -<pin name="PI13" x="38.1" y="22.86" length="short" rot="R180"/> -<pin name="PI14" x="38.1" y="20.32" length="short" rot="R180"/> -<pin name="FMC_NIORD/PF6" x="38.1" y="81.28" length="short" rot="R180"/> -<pin name="FMC_NREG/PF7" x="38.1" y="78.74" length="short" rot="R180"/> -<pin name="FMC_NIOWR/PF8" x="38.1" y="76.2" length="short" rot="R180"/> -<pin name="FMC_CD/PF9" x="38.1" y="73.66" length="short" rot="R180"/> -<pin name="FMC_INTR/PF10" x="38.1" y="71.12" length="short" rot="R180"/> -<pin name="PC1" x="-40.64" y="-45.72" length="short"/> -<pin name="USART2_CTS/WKUP/PA0" x="-40.64" y="73.66" length="short"/> -<pin name="USART2_RTS/PA1" x="-40.64" y="76.2" length="short"/> -<pin name="USART2_TX/PA2" x="-40.64" y="81.28" length="short"/> -<pin name="FMC_SDCKE0/PH2" x="38.1" y="43.18" length="short" rot="R180"/> -<pin name="PH3/FMC_SDNE0" x="-40.64" y="0" length="short"/> -<pin name="I2C2_SCL/PH4" x="-40.64" y="2.54" length="short"/> -<pin name="I2C2_SDA/FMC_SDNWE/PH5" x="-40.64" y="5.08" length="short"/> -<pin name="USART2_RX/PA3" x="-40.64" y="78.74" length="short"/> -<pin name="PA4" x="-40.64" y="-12.7" length="short"/> -<pin name="SPI1_SCK/PA5" x="-40.64" y="38.1" length="short"/> -<pin name="SPI1_MISO/PA6" x="-40.64" y="35.56" length="short"/> -<pin name="SPI1_MOSI/PA7" x="-40.64" y="33.02" length="short"/> -<pin name="PC4" x="-40.64" y="-48.26" length="short"/> -<pin name="PC5" x="-40.64" y="-50.8" length="short"/> -<pin name="PB0" x="-40.64" y="-22.86" length="short"/> -<pin name="PB1" x="-40.64" y="-25.4" length="short"/> -<pin name="PI15" x="38.1" y="17.78" length="short" rot="R180"/> -<pin name="PJ0" x="38.1" y="10.16" length="short" rot="R180"/> -<pin name="PJ1" x="38.1" y="7.62" length="short" rot="R180"/> -<pin name="PJ2" x="38.1" y="5.08" length="short" rot="R180"/> -<pin name="PJ3" x="38.1" y="2.54" length="short" rot="R180"/> -<pin name="PJ4" x="38.1" y="0" length="short" rot="R180"/> -<pin name="PB10" x="-40.64" y="-33.02" length="short"/> -<pin name="PB11" x="-40.64" y="-35.56" length="short"/> -<pin name="PJ5" x="38.1" y="-2.54" length="short" rot="R180"/> -<pin name="FMC_SDNE1/PH6" x="38.1" y="40.64" length="short" rot="R180"/> -<pin name="FMC_SDCKE1/PH7" x="38.1" y="38.1" length="short" rot="R180"/> -<pin name="PB12" x="-40.64" y="-38.1" length="short"/> -<pin name="SPI2_SCK/PB13" x="-40.64" y="50.8" length="short"/> -<pin name="SPI2_MISO/PB14" x="-40.64" y="48.26" length="short"/> -<pin name="SPI2_MOSI/PB15" x="-40.64" y="45.72" length="short"/> -<pin name="PJ6" x="38.1" y="-5.08" length="short" rot="R180"/> -<pin name="PJ7" x="38.1" y="-7.62" length="short" rot="R180"/> -<pin name="PJ8" x="38.1" y="-10.16" length="short" rot="R180"/> -<pin name="PJ9" x="38.1" y="-12.7" length="short" rot="R180"/> -<pin name="PJ10" x="38.1" y="-15.24" length="short" rot="R180"/> -<pin name="PJ11" x="38.1" y="-17.78" length="short" rot="R180"/> -<pin name="PK0" x="38.1" y="-35.56" length="short" rot="R180"/> -<pin name="PK1" x="38.1" y="-38.1" length="short" rot="R180"/> -<pin name="PK2" x="38.1" y="-40.64" length="short" rot="R180"/> -<pin name="FMC_INT2/PG6" x="38.1" y="63.5" length="short" rot="R180"/> -<pin name="FMC_INT3/PG7" x="38.1" y="60.96" length="short" rot="R180"/> -<pin name="PC6" x="-40.64" y="-53.34" length="short"/> -<pin name="PC7" x="-40.64" y="-55.88" length="short"/> -<pin name="SDIO_D0/PC8" x="-40.64" y="20.32" length="short"/> -<pin name="SDIO_D1/PC9" x="-40.64" y="17.78" length="short"/> -<pin name="PA8" x="-40.64" y="-15.24" length="short"/> -<pin name="USART1_TX/PA9" x="-40.64" y="63.5" length="short"/> -<pin name="USART1_RX/PA10" x="-40.64" y="66.04" length="short"/> -<pin name="USART1_CTS/PA11" x="-40.64" y="58.42" length="short"/> -<pin name="USART1_RTS/PA12" x="-40.64" y="60.96" length="short"/> -<text x="-33.02" y="96.52" size="1.778" layer="95">>NAME</text> -<text x="-33.02" y="91.44" size="1.778" layer="96">>VALUE</text> -<pin name="SDIO_D2/SPI3_SCK/PC10" x="-40.64" y="15.24" length="short"/> -<pin name="SDIO_D3/SPI3_MISO/PC11" x="-40.64" y="12.7" length="short"/> -<pin name="SDIO_CK/SPI3_MOSI/PC12" x="-40.64" y="22.86" length="short"/> -<pin name="SDIO_CMD/PD2" x="-40.64" y="25.4" length="short"/> -<pin name="PJ12" x="38.1" y="-20.32" length="short" rot="R180"/> -<pin name="PJ13" x="38.1" y="-22.86" length="short" rot="R180"/> -<pin name="PJ14" x="38.1" y="-25.4" length="short" rot="R180"/> -<pin name="PJ15" x="38.1" y="-27.94" length="short" rot="R180"/> -<pin name="FMC_NE2/FMC_NCE3/PG9" x="38.1" y="58.42" length="short" rot="R180"/> -<pin name="FMC_NCE4_1/FMC_NE3/PG10" x="38.1" y="55.88" length="short" rot="R180"/> -<pin name="FMC_NCE4_2/PG11" x="38.1" y="53.34" length="short" rot="R180"/> -<pin name="FMC_NE4/PG12" x="38.1" y="50.8" length="short" rot="R180"/> -<pin name="PK3" x="38.1" y="-43.18" length="short" rot="R180"/> -<pin name="PK4" x="38.1" y="-45.72" length="short" rot="R180"/> -<pin name="PK5" x="38.1" y="-48.26" length="short" rot="R180"/> -<pin name="PK6" x="38.1" y="-50.8" length="short" rot="R180"/> -<pin name="PK7" x="38.1" y="-53.34" length="short" rot="R180"/> -<pin name="PB8" x="-40.64" y="-27.94" length="short"/> -<pin name="PB9" x="-40.64" y="-30.48" length="short"/> +<wire x1="-38.1" y1="81.28" x2="35.56" y2="81.28" width="0.254" layer="94"/> +<wire x1="35.56" y1="81.28" x2="35.56" y2="-78.74" width="0.254" layer="94"/> +<wire x1="35.56" y1="-78.74" x2="-38.1" y2="-78.74" width="0.254" layer="94"/> +<wire x1="-38.1" y1="-78.74" x2="-38.1" y2="81.28" width="0.254" layer="94"/> +<pin name="PI8" x="38.1" y="22.86" length="short" rot="R180"/> +<pin name="PC13" x="-40.64" y="-66.04" length="short"/> +<pin name="PC14" x="-40.64" y="-68.58" length="short"/> +<pin name="PC15" x="-40.64" y="-71.12" length="short"/> +<pin name="PI11" x="38.1" y="20.32" length="short" rot="R180"/> +<pin name="PI12" x="38.1" y="17.78" length="short" rot="R180"/> +<pin name="PI13" x="38.1" y="15.24" length="short" rot="R180"/> +<pin name="PI14" x="38.1" y="12.7" length="short" rot="R180"/> +<pin name="FMC_NIORD/PF6" x="38.1" y="73.66" length="short" rot="R180"/> +<pin name="FMC_NREG/PF7" x="38.1" y="71.12" length="short" rot="R180"/> +<pin name="FMC_NIOWR/PF8" x="38.1" y="68.58" length="short" rot="R180"/> +<pin name="FMC_CD/PF9" x="38.1" y="66.04" length="short" rot="R180"/> +<pin name="FMC_INTR/PF10" x="38.1" y="63.5" length="short" rot="R180"/> +<pin name="PC1" x="-40.64" y="-53.34" length="short"/> +<pin name="USART2_CTS/WKUP/PA0" x="-40.64" y="63.5" length="short"/> +<pin name="USART2_RTS/PA1" x="-40.64" y="66.04" length="short"/> +<pin name="USART2_TX/PA2" x="-40.64" y="71.12" length="short"/> +<pin name="FMC_SDCKE0/PH2" x="38.1" y="35.56" length="short" rot="R180"/> +<pin name="PH3" x="-40.64" y="-15.24" length="short"/> +<pin name="I2C2_SCL/PH4" x="-40.64" y="-12.7" length="short"/> +<pin name="I2C2_SDA/PH5" x="-40.64" y="-10.16" length="short"/> +<pin name="USART2_RX/PA3" x="-40.64" y="68.58" length="short"/> +<pin name="PA4" x="-40.64" y="73.66" length="short"/> +<pin name="SPI1_SCK/PA5" x="-40.64" y="22.86" length="short"/> +<pin name="SPI1_MISO/PA6" x="-40.64" y="20.32" length="short"/> +<pin name="SPI1_MOSI/PA7" x="-40.64" y="17.78" length="short"/> +<pin name="PC4" x="-40.64" y="-55.88" length="short"/> +<pin name="PC5" x="-40.64" y="-58.42" length="short"/> +<pin name="PB0" x="-40.64" y="-30.48" length="short"/> +<pin name="PB1" x="-40.64" y="-33.02" length="short"/> +<pin name="PI15" x="38.1" y="10.16" length="short" rot="R180"/> +<pin name="PJ0" x="38.1" y="2.54" length="short" rot="R180"/> +<pin name="PJ1" x="38.1" y="0" length="short" rot="R180"/> +<pin name="PJ2" x="38.1" y="-2.54" length="short" rot="R180"/> +<pin name="PJ3" x="38.1" y="-5.08" length="short" rot="R180"/> +<pin name="PJ4" x="38.1" y="-7.62" length="short" rot="R180"/> +<pin name="PB10" x="-40.64" y="-40.64" length="short"/> +<pin name="PB11" x="-40.64" y="-43.18" length="short"/> +<pin name="PJ5" x="38.1" y="-10.16" length="short" rot="R180"/> +<pin name="FMC_SDNE1/PH6" x="38.1" y="33.02" length="short" rot="R180"/> +<pin name="FMC_SDCKE1/PH7" x="38.1" y="30.48" length="short" rot="R180"/> +<pin name="PB12" x="-40.64" y="38.1" length="short"/> +<pin name="SPI2_SCK/PB13" x="-40.64" y="35.56" length="short"/> +<pin name="SPI2_MISO/PB14" x="-40.64" y="33.02" length="short"/> +<pin name="SPI2_MOSI/PB15" x="-40.64" y="30.48" length="short"/> +<pin name="PJ6" x="38.1" y="-12.7" length="short" rot="R180"/> +<pin name="PJ7" x="38.1" y="-15.24" length="short" rot="R180"/> +<pin name="PJ8" x="38.1" y="-17.78" length="short" rot="R180"/> +<pin name="PJ9" x="38.1" y="-20.32" length="short" rot="R180"/> +<pin name="PJ10" x="38.1" y="-22.86" length="short" rot="R180"/> +<pin name="PJ11" x="38.1" y="-25.4" length="short" rot="R180"/> +<pin name="PK0" x="38.1" y="-43.18" length="short" rot="R180"/> +<pin name="PK1" x="38.1" y="-45.72" length="short" rot="R180"/> +<pin name="PK2" x="38.1" y="-48.26" length="short" rot="R180"/> +<pin name="FMC_INT2/PG6" x="38.1" y="55.88" length="short" rot="R180"/> +<pin name="FMC_INT3/PG7" x="38.1" y="53.34" length="short" rot="R180"/> +<pin name="PC6" x="-40.64" y="-60.96" length="short"/> +<pin name="PC7" x="-40.64" y="-63.5" length="short"/> +<pin name="SDIO_D0/PC8" x="-40.64" y="5.08" length="short"/> +<pin name="SDIO_D1/PC9" x="-40.64" y="2.54" length="short"/> +<pin name="PA8" x="-40.64" y="55.88" length="short"/> +<pin name="USART1_TX/PA9" x="-40.64" y="53.34" length="short"/> +<pin name="USART1_RX/PA10" x="-40.64" y="50.8" length="short"/> +<pin name="USART1_CTS/PA11" x="-40.64" y="45.72" length="short"/> +<pin name="USART1_RTS/PA12" x="-40.64" y="48.26" length="short"/> +<text x="-33.02" y="88.9" size="1.778" layer="95">>NAME</text> +<text x="-33.02" y="83.82" size="1.778" layer="96">>VALUE</text> +<pin name="SDIO_D2/PC10" x="-40.64" y="0" length="short"/> +<pin name="SDIO_D3/PC11" x="-40.64" y="-2.54" length="short"/> +<pin name="SDIO_CK/PC12" x="-40.64" y="7.62" length="short"/> +<pin name="SDIO_CMD/PD2" x="-40.64" y="10.16" length="short"/> +<pin name="PJ12" x="38.1" y="-27.94" length="short" rot="R180"/> +<pin name="PJ13" x="38.1" y="-30.48" length="short" rot="R180"/> +<pin name="PJ14" x="38.1" y="-33.02" length="short" rot="R180"/> +<pin name="PJ15" x="38.1" y="-35.56" length="short" rot="R180"/> +<pin name="FMC_NE2/FMC_NCE3/PG9" x="38.1" y="50.8" length="short" rot="R180"/> +<pin name="FMC_NCE4_1/FMC_NE3/PG10" x="38.1" y="48.26" length="short" rot="R180"/> +<pin name="FMC_NCE4_2/PG11" x="38.1" y="45.72" length="short" rot="R180"/> +<pin name="FMC_NE4/PG12" x="38.1" y="43.18" length="short" rot="R180"/> +<pin name="PK3" x="38.1" y="-50.8" length="short" rot="R180"/> +<pin name="PK4" x="38.1" y="-53.34" length="short" rot="R180"/> +<pin name="PK5" x="38.1" y="-55.88" length="short" rot="R180"/> +<pin name="PK6" x="38.1" y="-58.42" length="short" rot="R180"/> +<pin name="PK7" x="38.1" y="-60.96" length="short" rot="R180"/> +<pin name="PB8/I2C1_SCL" x="-40.64" y="-35.56" length="short"/> +<pin name="PB9/I2C1_SDA" x="-40.64" y="-38.1" length="short"/> </symbol> <symbol name="STM32F429_LQFP-208_CFG"> <description>Basic configuration for STM32</description> @@ -35137,7 +35096,7 @@ Clock frequency: 166, 143 MHz</description> <connect gate="IO" pin="FMC_SDCKE1/PH7" pad="97"/> <connect gate="IO" pin="FMC_SDNE1/PH6" pad="96"/> <connect gate="IO" pin="I2C2_SCL/PH4" pad="48"/> -<connect gate="IO" pin="I2C2_SDA/FMC_SDNWE/PH5" pad="49"/> +<connect gate="IO" pin="I2C2_SDA/PH5" pad="49"/> <connect gate="IO" pin="PA4" pad="53"/> <connect gate="IO" pin="PA8" pad="142"/> <connect gate="IO" pin="PB0" pad="61"/> @@ -35145,17 +35104,17 @@ Clock frequency: 166, 143 MHz</description> <connect gate="IO" pin="PB10" pad="90"/> <connect gate="IO" pin="PB11" pad="91"/> <connect gate="IO" pin="PB12" pad="104"/> -<connect gate="IO" pin="PB8" pad="198"/> -<connect gate="IO" pin="PB9" pad="199"/> +<connect gate="IO" pin="PB8/I2C1_SCL" pad="198"/> +<connect gate="IO" pin="PB9/I2C1_SDA" pad="199"/> <connect gate="IO" pin="PC1" pad="36"/> <connect gate="IO" pin="PC13" pad="8"/> -<connect gate="IO" pin="PC14/OSC32_IN" pad="9"/> -<connect gate="IO" pin="PC15/OSC32_OUT" pad="10"/> +<connect gate="IO" pin="PC14" pad="9"/> +<connect gate="IO" pin="PC15" pad="10"/> <connect gate="IO" pin="PC4" pad="57"/> <connect gate="IO" pin="PC5" pad="58"/> <connect gate="IO" pin="PC6" pad="138"/> <connect gate="IO" pin="PC7" pad="139"/> -<connect gate="IO" pin="PH3/FMC_SDNE0" pad="47"/> +<connect gate="IO" pin="PH3" pad="47"/> <connect gate="IO" pin="PI11" pad="13"/> <connect gate="IO" pin="PI12" pad="19"/> <connect gate="IO" pin="PI13" pad="20"/> @@ -35186,12 +35145,12 @@ Clock frequency: 166, 143 MHz</description> <connect gate="IO" pin="PK5" pad="188"/> <connect gate="IO" pin="PK6" pad="189"/> <connect gate="IO" pin="PK7" pad="190"/> -<connect gate="IO" pin="SDIO_CK/SPI3_MOSI/PC12" pad="163"/> +<connect gate="IO" pin="SDIO_CK/PC12" pad="163"/> <connect gate="IO" pin="SDIO_CMD/PD2" pad="166"/> <connect gate="IO" pin="SDIO_D0/PC8" pad="140"/> <connect gate="IO" pin="SDIO_D1/PC9" pad="141"/> -<connect gate="IO" pin="SDIO_D2/SPI3_SCK/PC10" pad="161"/> -<connect gate="IO" pin="SDIO_D3/SPI3_MISO/PC11" pad="162"/> +<connect gate="IO" pin="SDIO_D2/PC10" pad="161"/> +<connect gate="IO" pin="SDIO_D3/PC11" pad="162"/> <connect gate="IO" pin="SPI1_MISO/PA6" pad="55"/> <connect gate="IO" pin="SPI1_MOSI/PA7" pad="56"/> <connect gate="IO" pin="SPI1_SCK/PA5" pad="54"/> @@ -35253,6 +35212,340 @@ Clock frequency: 166, 143 MHz</description> </deviceset> </devicesets> </library> +<library name="74xx-eu"> +<description><b>TTL Devices, 74xx Series with European Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 +<li>http://icmaster.com/ViewCompare.asp +</ul> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="DIL20"> +<description><b>Dual In Line Package</b></description> +<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/> +<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/> +<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/> +<wire x1="-12.7" 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layer="95">>NAME</text> +<text x="-7.62" y="-12.7" size="1.778" layer="96">>VALUE</text> +<pin name="G" x="-12.7" y="-7.62" length="middle" direction="in" function="dot"/> +<pin name="A1" x="-12.7" y="5.08" length="middle" direction="in"/> +<pin name="A2" x="-12.7" y="2.54" length="middle" direction="in"/> +<pin name="A3" x="-12.7" y="0" length="middle" direction="in"/> +<pin name="A4" x="-12.7" y="-2.54" length="middle" direction="in"/> +<pin name="Y4" x="12.7" y="-2.54" length="middle" direction="hiz" rot="R180"/> +<pin name="Y3" x="12.7" y="0" length="middle" direction="hiz" rot="R180"/> +<pin name="Y2" x="12.7" y="2.54" length="middle" direction="hiz" rot="R180"/> +<pin name="Y1" x="12.7" y="5.08" length="middle" direction="hiz" rot="R180"/> +</symbol> +<symbol name="PWRN"> +<text x="-0.635" y="-0.635" size="1.778" layer="95">>NAME</text> +<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text> +<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCC</text> +<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/> +<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="74*244" prefix="IC"> +<description>Octal <b>BUFFER</b> and <b>LINE DRIVER</b>, 3-state</description> +<gates> +<gate name="A" symbol="74244" x="30.48" y="10.16" swaplevel="1"/> +<gate name="B" symbol="74244" x="30.48" y="-17.78" swaplevel="1"/> +<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/> +</gates> +<devices> +<device name="N" package="DIL20"> +<connects> +<connect gate="A" pin="A1" pad="2"/> +<connect gate="A" pin="A2" pad="4"/> +<connect gate="A" pin="A3" pad="6"/> +<connect gate="A" pin="A4" pad="8"/> +<connect gate="A" pin="G" pad="1"/> +<connect gate="A" pin="Y1" pad="18"/> +<connect gate="A" pin="Y2" pad="16"/> +<connect gate="A" pin="Y3" pad="14"/> +<connect gate="A" pin="Y4" pad="12"/> +<connect gate="B" pin="A1" pad="11"/> +<connect gate="B" pin="A2" pad="13"/> +<connect gate="B" pin="A3" pad="15"/> +<connect gate="B" pin="A4" pad="17"/> +<connect gate="B" pin="G" pad="19"/> +<connect gate="B" pin="Y1" pad="9"/> +<connect gate="B" pin="Y2" pad="7"/> +<connect gate="B" pin="Y3" pad="5"/> +<connect gate="B" pin="Y4" pad="3"/> +<connect gate="P" pin="GND" pad="10"/> +<connect gate="P" pin="VCC" pad="20"/> +</connects> +<technologies> +<technology name="AC"/> +<technology name="ACT"/> +<technology name="HC"/> +<technology name="HCT"/> +<technology name="LS"/> +<technology name="S"/> +</technologies> +</device> +<device name="DW" package="SO20W"> +<connects> +<connect gate="A" pin="A1" pad="2"/> +<connect gate="A" pin="A2" pad="4"/> +<connect gate="A" pin="A3" pad="6"/> +<connect gate="A" pin="A4" pad="8"/> +<connect gate="A" pin="G" pad="1"/> +<connect gate="A" pin="Y1" pad="18"/> +<connect gate="A" pin="Y2" pad="16"/> +<connect gate="A" pin="Y3" pad="14"/> +<connect gate="A" pin="Y4" pad="12"/> +<connect gate="B" pin="A1" pad="11"/> +<connect gate="B" pin="A2" pad="13"/> +<connect gate="B" pin="A3" pad="15"/> +<connect gate="B" pin="A4" pad="17"/> +<connect gate="B" pin="G" pad="19"/> +<connect gate="B" pin="Y1" pad="9"/> +<connect gate="B" pin="Y2" pad="7"/> +<connect gate="B" pin="Y3" pad="5"/> +<connect gate="B" pin="Y4" pad="3"/> +<connect gate="P" pin="GND" pad="10"/> +<connect gate="P" pin="VCC" pad="20"/> +</connects> +<technologies> +<technology name="AC"/> +<technology name="ACT"/> +<technology name="HC"/> +<technology name="HCT"/> +<technology name="LS"/> +<technology name="S"/> +</technologies> +</device> +<device name="FK" package="LCC20"> +<connects> +<connect gate="A" pin="A1" pad="2"/> +<connect gate="A" pin="A2" pad="4"/> +<connect gate="A" pin="A3" pad="6"/> +<connect gate="A" pin="A4" pad="8"/> +<connect gate="A" pin="G" pad="1"/> +<connect gate="A" pin="Y1" pad="18"/> +<connect gate="A" pin="Y2" pad="16"/> +<connect gate="A" pin="Y3" pad="14"/> +<connect gate="A" pin="Y4" pad="12"/> +<connect gate="B" pin="A1" pad="11"/> +<connect gate="B" pin="A2" pad="13"/> +<connect gate="B" pin="A3" pad="15"/> +<connect gate="B" pin="A4" pad="17"/> +<connect gate="B" pin="G" pad="19"/> +<connect gate="B" pin="Y1" pad="9"/> +<connect gate="B" pin="Y2" pad="7"/> +<connect gate="B" pin="Y3" pad="5"/> +<connect gate="B" pin="Y4" pad="3"/> +<connect gate="P" pin="GND" pad="10"/> +<connect gate="P" pin="VCC" pad="20"/> +</connects> +<technologies> +<technology name="AC"/> +<technology name="ACT"/> +<technology name="HC"/> +<technology name="HCT"/> +<technology name="LS"/> +<technology name="S"/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> </libraries> <attributes> </attributes> @@ -36533,7 +36826,6 @@ Clock frequency: 166, 143 MHz</description> <part name="SUPPLY5" library="supply2" deviceset="GND" device=""/> <part name="FRAME22" library="frames" deviceset="A3L-LOC" device=""/> <part name="FT_VCC3V3_3" library="SUPPLY1" deviceset="VCC" device=""/> -<part name="FT_VCC3V3_4" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_5" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_6" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_7" library="SUPPLY1" deviceset="VCC" device=""/> @@ -36578,16 +36870,6 @@ Clock frequency: 166, 143 MHz</description> <part name="R6" library="resistor" deviceset="R-EU_" device="R0402" value="10K"/> <part name="R30" library="resistor" deviceset="R-EU_" device="R0402" value="10K"/> <part name="R31" library="resistor" deviceset="R-EU_" device="R0402" value="10K"/> -<part name="U1" library="ON_Semiconductor-MC14551BDG" deviceset="MC14551BDG" device=""/> -<part name="P+57" library="SUPPLY1" deviceset="VCC" device=""/> -<part name="SUPPLY13" library="supply2" deviceset="GND" device=""/> -<part name="R32" library="resistor" deviceset="R-EU_" device="R0603" value="15K"/> -<part name="C8" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF"> -<attribute name="DIELECTRIC" value="X7R"/> -<attribute name="RATED_VOLTAGE" value="10V"/> -</part> -<part name="SUPPLY14" library="supply2" deviceset="GND" device=""/> -<part name="FRAME10" library="microbuilder" deviceset="FRAME_A3" device=""/> <part name="JP8" library="jumper" deviceset="JP1Q" device=""/> <part name="IC1" library="Alpha-IC" deviceset="IS45S32160F" device=""/> <part name="U$10" library="FT232H" deviceset="FT232H_SERIAL" device=""/> @@ -36684,7 +36966,6 @@ Clock frequency: 166, 143 MHz</description> </part> <part name="FRAME24" library="frames" deviceset="A3L-LOC" device=""/> <part name="FT_VCC3V3_12" library="SUPPLY1" deviceset="VCC" device=""/> -<part name="FT_VCC3V3_13" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_14" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_15" library="SUPPLY1" deviceset="VCC" device=""/> <part name="FT_VCC3V3_16" library="SUPPLY1" deviceset="VCC" device=""/> @@ -36826,6 +37107,18 @@ Clock frequency: 166, 143 MHz</description> <part name="FRAME25" library="frames" deviceset="A3L-LOC" device=""/> <part name="FRAME3" library="frames" deviceset="A3L-LOC" device=""/> <part name="FRAME26" library="frames" deviceset="A3L-LOC" device=""/> +<part name="IC5" library="74xx-eu" deviceset="74*244" device="DW" technology="AC"/> +<part name="P+5" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="C214" library="resistor" deviceset="C-EU" device="C0402" value="0.1uF"/> +<part name="R77" library="resistor" deviceset="R-EU_" device="R0603" value="4.7k"/> +<part name="P+6" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="SUPPLY20" library="supply2" deviceset="GND" device=""/> +<part name="R80" library="resistor" deviceset="R-EU_" device="R0603" value="4.7k"/> +<part name="P+12" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="R81" library="resistor" deviceset="R-EU_" device="R0603" value="4.7k"/> +<part name="SUPPLY14" library="supply2" deviceset="GND" device=""/> +<part name="JP9" library="jumper" deviceset="JP1Q" device=""/> +<part name="FRAME10" library="frames" deviceset="A4L-LOC" device=""/> </parts> <sheets> <sheet> @@ -36860,57 +37153,58 @@ Clock frequency: 166, 143 MHz</description> <sheet> <description>Input power</description> <plain> -<text x="22.86" y="77.47" size="2.54" layer="91">15V LDO powered from external 18V +<text x="43.18" y="74.93" size="2.54" layer="91">15V LDO powered from external 18V and supplying stable 15V to noise source</text> -<text x="-170.18" y="81.28" size="3.81" layer="91">Main power input +<text x="-175.26" y="60.96" size="3.81" layer="91">Main power input 18V DC</text> -<text x="-105.41" y="55.88" size="1.778" layer="91">To mitigate component ageing in the avalanche noise circuit, +<text x="-85.09" y="53.34" size="1.778" layer="91">To mitigate component ageing in the avalanche noise circuit, this jumper can be used to decide if FPGA/ARM/None should be allowed to turn off the entropy source (default On through pull-up)</text> -<text x="91.44" y="35.56" size="1.778" layer="91">Max 3 ohm ESR</text> +<text x="111.76" y="33.02" size="1.778" layer="91">Max 3 ohm ESR</text> <text x="-53.34" y="-22.86" size="2.54" layer="91">*) Intermediate Regulator: 18V -> 5V</text> <text x="30.48" y="-104.14" size="1.778" layer="91">*) VCC_5V0 = 0.8V x (1 + 6.3/1.21) = 4.965V *) Current sharing not used *) SYNC is not used</text> +<text x="-83.82" y="78.74" size="3.81" layer="91">Entropy source power</text> </plain> <instances> <instance part="FRAME6" gate="G$1" x="-198.12" y="-142.24"/> -<instance part="JP1" gate="G$1" x="-160.02" y="55.88"/> -<instance part="SUPPLY1" gate="GND" x="-139.7" y="50.8" rot="MR0"/> -<instance part="U$9" gate="G$1" x="58.42" y="50.8"/> -<instance part="SUPPLY7" gate="GND" x="40.64" y="30.48" rot="MR0"/> -<instance part="C1" gate="G$1" x="76.2" y="53.34" smashed="yes" rot="R180"> -<attribute name="NAME" x="78.74" y="53.34" size="1.6764" layer="95"/> -<attribute name="VALUE" x="78.74" y="50.8" size="1.6764" layer="96"/> -<attribute name="DIELECTRIC" x="78.74" y="48.26" size="1.27" layer="96"/> -<attribute name="RATED_VOLTAGE" x="76.2" y="53.34" size="1.778" layer="96" rot="R180" display="off"/> -</instance> -<instance part="C4" gate="G$1" x="76.2" y="38.1" smashed="yes" rot="R180"> -<attribute name="NAME" x="78.74" y="38.1" size="1.6764" layer="95"/> -<attribute name="VALUE" x="78.74" y="35.56" size="1.6764" layer="96"/> -<attribute name="DIELECTRIC" x="78.74" y="33.02" size="1.27" layer="96"/> -<attribute name="RATED_VOLTAGE" x="76.2" y="38.1" size="1.778" layer="96" rot="R180" display="off"/> -</instance> -<instance part="SUPPLY9" gate="GND" x="76.2" y="30.48" rot="MR0"/> -<instance part="C5" gate="G$1" x="88.9" y="45.72" smashed="yes"> -<attribute name="NAME" x="91.44" y="43.18" size="1.6764" layer="95" font="vector"/> -<attribute name="VALUE" x="91.44" y="40.64" size="1.6764" layer="96" font="vector"/> -<attribute name="DIELECTRIC" x="88.9" y="45.72" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="88.9" y="45.72" size="1.778" layer="96" display="off"/> -</instance> -<instance part="SUPPLY12" gate="GND" x="88.9" y="30.48" rot="MR0"/> -<instance part="R22" gate="G$1" x="-7.62" y="58.42" rot="R270"/> -<instance part="PWR_18V" gate="VCC" x="-139.7" y="73.66" smashed="yes"> -<attribute name="VALUE" x="-137.16" y="73.66" size="1.778" layer="96"/> -</instance> -<instance part="PWR_18V1" gate="VCC" x="27.94" y="68.58" smashed="yes"> -<attribute name="VALUE" x="30.48" y="68.58" size="1.778" layer="96"/> -</instance> -<instance part="PWR_18V2" gate="VCC" x="96.52" y="68.58" smashed="yes"> -<attribute name="VALUE" x="99.06" y="68.58" size="1.778" layer="96"/> +<instance part="JP1" gate="G$1" x="-165.1" y="35.56"/> +<instance part="SUPPLY1" gate="GND" x="-144.78" y="30.48" rot="MR0"/> +<instance part="U$9" gate="G$1" x="78.74" y="48.26"/> +<instance part="SUPPLY7" gate="GND" x="60.96" y="27.94" rot="MR0"/> +<instance part="C1" gate="G$1" x="96.52" y="50.8" smashed="yes" rot="R180"> +<attribute name="NAME" x="99.06" y="50.8" size="1.6764" layer="95"/> +<attribute name="VALUE" x="99.06" y="48.26" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="99.06" y="45.72" size="1.27" layer="96"/> +<attribute name="RATED_VOLTAGE" x="96.52" y="50.8" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C4" gate="G$1" x="96.52" y="35.56" smashed="yes" rot="R180"> +<attribute name="NAME" x="99.06" y="35.56" size="1.6764" layer="95"/> +<attribute name="VALUE" x="99.06" y="33.02" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="99.06" y="30.48" size="1.27" layer="96"/> +<attribute name="RATED_VOLTAGE" x="96.52" y="35.56" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SUPPLY9" gate="GND" x="96.52" y="27.94" rot="MR0"/> +<instance part="C5" gate="G$1" x="109.22" y="43.18" smashed="yes"> +<attribute name="NAME" x="111.76" y="40.64" size="1.6764" layer="95" font="vector"/> +<attribute name="VALUE" x="111.76" y="38.1" size="1.6764" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="109.22" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="109.22" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY12" gate="GND" x="109.22" y="27.94" rot="MR0"/> +<instance part="R22" gate="G$1" x="12.7" y="55.88" rot="R270"/> +<instance part="PWR_18V" gate="VCC" x="-144.78" y="53.34" smashed="yes"> +<attribute name="VALUE" x="-142.24" y="53.34" size="1.778" layer="96"/> +</instance> +<instance part="PWR_18V1" gate="VCC" x="48.26" y="66.04" smashed="yes"> +<attribute name="VALUE" x="50.8" y="66.04" size="1.778" layer="96"/> +</instance> +<instance part="PWR_18V2" gate="VCC" x="116.84" y="66.04" smashed="yes"> +<attribute name="VALUE" x="119.38" y="66.04" size="1.778" layer="96"/> </instance> <instance part="U$8" gate="G$1" x="-10.16" y="-58.42"/> <instance part="SUPPLY197" gate="GND" x="-12.7" y="-99.06"/> @@ -37001,29 +37295,29 @@ be allowed to turn off the entropy source <instance part="PWR_18V3" gate="VCC" x="-121.92" y="-30.48" smashed="yes"> <attribute name="VALUE" x="-119.38" y="-30.48" size="1.778" layer="96"/> </instance> -<instance part="PWR_18V4" gate="VCC" x="-7.62" y="68.58" smashed="yes"> -<attribute name="VALUE" x="-5.08" y="68.58" size="1.778" layer="96"/> +<instance part="PWR_18V4" gate="VCC" x="12.7" y="66.04" smashed="yes"> +<attribute name="VALUE" x="15.24" y="66.04" size="1.778" layer="96"/> </instance> <instance part="PWR_18V5" gate="VCC" x="86.36" y="-30.48" smashed="yes"> <attribute name="VALUE" x="88.9" y="-30.48" size="1.778" layer="96"/> </instance> -<instance part="Q1" gate="G$1" x="-43.18" y="41.91"/> -<instance part="R75" gate="G$1" x="-53.34" y="29.21" rot="R270"> -<attribute name="TOLERANCE" x="-53.34" y="29.21" size="1.778" layer="96" rot="R270" display="off"/> +<instance part="Q1" gate="G$1" x="-22.86" y="39.37"/> +<instance part="R75" gate="G$1" x="-33.02" y="26.67" rot="R270"> +<attribute name="TOLERANCE" x="-33.02" y="26.67" size="1.778" layer="96" rot="R270" display="off"/> </instance> -<instance part="R76" gate="G$1" x="-63.5" y="39.37"> -<attribute name="TOLERANCE" x="-63.5" y="39.37" size="1.778" layer="96" display="off"/> +<instance part="R76" gate="G$1" x="-43.18" y="36.83"> +<attribute name="TOLERANCE" x="-43.18" y="36.83" size="1.778" layer="96" display="off"/> </instance> -<instance part="SUPPLY222" gate="GND" x="-53.34" y="16.51" rot="MR0"/> -<instance part="SUPPLY223" gate="GND" x="-33.02" y="16.51" rot="MR0"/> -<instance part="JP2" gate="A" x="-21.59" y="50.8" rot="R90"/> -<instance part="C213" gate="G$1" x="27.94" y="40.64" smashed="yes"> -<attribute name="NAME" x="24.13" y="40.64" size="1.6764" layer="95" font="vector" rot="R180"/> -<attribute name="VALUE" x="24.13" y="38.1" size="1.6764" layer="96" font="vector" rot="R180"/> -<attribute name="DIELECTRIC" x="27.94" y="40.64" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="27.94" y="40.64" size="1.778" layer="96" display="off"/> +<instance part="SUPPLY222" gate="GND" x="-33.02" y="13.97" rot="MR0"/> +<instance part="SUPPLY223" gate="GND" x="-12.7" y="13.97" rot="MR0"/> +<instance part="JP2" gate="A" x="-1.27" y="48.26" rot="R90"/> +<instance part="C213" gate="G$1" x="48.26" y="38.1" smashed="yes"> +<attribute name="NAME" x="44.45" y="38.1" size="1.6764" layer="95" font="vector" rot="R180"/> +<attribute name="VALUE" x="44.45" y="35.56" size="1.6764" layer="96" font="vector" rot="R180"/> +<attribute name="DIELECTRIC" x="48.26" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="38.1" size="1.778" layer="96" display="off"/> </instance> -<instance part="SUPPLY224" gate="GND" x="27.94" y="30.48" rot="MR0"/> +<instance part="SUPPLY224" gate="GND" x="48.26" y="27.94" rot="MR0"/> </instances> <busses> </busses> @@ -37031,25 +37325,25 @@ be allowed to turn off the entropy source <net name="GND" class="1"> <segment> <pinref part="JP1" gate="G$1" pin="GND"/> -<wire x1="-157.48" y1="58.42" x2="-139.7" y2="58.42" width="0.1524" layer="91"/> -<wire x1="-139.7" y1="58.42" x2="-139.7" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-162.56" y1="38.1" x2="-144.78" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-144.78" y1="38.1" x2="-144.78" y2="33.02" width="0.1524" layer="91"/> <pinref part="SUPPLY1" gate="GND" pin="GND"/> </segment> <segment> <pinref part="U$9" gate="G$1" pin="GND"/> <pinref part="SUPPLY7" gate="GND" pin="GND"/> -<wire x1="43.18" y1="43.18" x2="40.64" y2="43.18" width="0.1524" layer="91"/> -<wire x1="40.64" y1="43.18" x2="40.64" y2="33.02" width="0.1524" layer="91"/> +<wire x1="63.5" y1="40.64" x2="60.96" y2="40.64" width="0.1524" layer="91"/> +<wire x1="60.96" y1="40.64" x2="60.96" y2="30.48" width="0.1524" layer="91"/> </segment> <segment> <pinref part="C4" gate="G$1" pin="1"/> <pinref part="SUPPLY9" gate="GND" pin="GND"/> -<wire x1="76.2" y1="35.56" x2="76.2" y2="33.02" width="0.1524" layer="91"/> +<wire x1="96.52" y1="33.02" x2="96.52" y2="30.48" width="0.1524" layer="91"/> </segment> <segment> <pinref part="C5" gate="G$1" pin="2"/> <pinref part="SUPPLY12" gate="GND" pin="GND"/> -<wire x1="88.9" y1="40.64" x2="88.9" y2="33.02" width="0.1524" layer="91"/> +<wire x1="109.22" y1="38.1" x2="109.22" y2="30.48" width="0.1524" layer="91"/> </segment> <segment> <pinref part="SUPPLY197" gate="GND" pin="GND"/> @@ -37124,37 +37418,37 @@ be allowed to turn off the entropy source <segment> <pinref part="SUPPLY222" gate="GND" pin="GND"/> <pinref part="R75" gate="G$1" pin="2"/> -<wire x1="-53.34" y1="19.05" x2="-53.34" y2="24.13" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="16.51" x2="-33.02" y2="21.59" width="0.1524" layer="91"/> </segment> <segment> <pinref part="Q1" gate="G$1" pin="S"/> -<wire x1="-38.1" y1="39.37" x2="-33.02" y2="39.37" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="36.83" x2="-12.7" y2="36.83" width="0.1524" layer="91"/> <pinref part="SUPPLY223" gate="GND" pin="GND"/> -<wire x1="-33.02" y1="39.37" x2="-33.02" y2="19.05" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="36.83" x2="-12.7" y2="16.51" width="0.1524" layer="91"/> </segment> <segment> <pinref part="SUPPLY224" gate="GND" pin="GND"/> <pinref part="C213" gate="G$1" pin="2"/> -<wire x1="27.94" y1="33.02" x2="27.94" y2="35.56" width="0.1524" layer="91"/> +<wire x1="48.26" y1="30.48" x2="48.26" y2="33.02" width="0.1524" layer="91"/> </segment> </net> <net name="PWR_18V" class="0"> <segment> <pinref part="JP1" gate="G$1" pin="PWR"/> -<wire x1="-157.48" y1="63.5" x2="-139.7" y2="63.5" width="0.1524" layer="91"/> -<label x="-137.16" y="69.85" size="1.778" layer="95"/> +<wire x1="-162.56" y1="43.18" x2="-144.78" y2="43.18" width="0.1524" layer="91"/> +<label x="-142.24" y="49.53" size="1.778" layer="95"/> <pinref part="PWR_18V" gate="VCC" pin="VCC"/> -<wire x1="-139.7" y1="63.5" x2="-139.7" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-144.78" y1="43.18" x2="-144.78" y2="50.8" width="0.1524" layer="91"/> </segment> <segment> -<wire x1="27.94" y1="58.42" x2="43.18" y2="58.42" width="0.1524" layer="91"/> -<label x="30.48" y="66.04" size="1.778" layer="95"/> +<wire x1="48.26" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/> +<label x="50.8" y="63.5" size="1.778" layer="95"/> <pinref part="U$9" gate="G$1" pin="IN"/> <pinref part="PWR_18V1" gate="VCC" pin="VCC"/> -<wire x1="27.94" y1="58.42" x2="27.94" y2="66.04" width="0.1524" layer="91"/> +<wire x1="48.26" y1="55.88" x2="48.26" y2="63.5" width="0.1524" layer="91"/> <pinref part="C213" gate="G$1" pin="1"/> -<wire x1="27.94" y1="58.42" x2="27.94" y2="43.18" width="0.1524" layer="91"/> -<junction x="27.94" y="58.42"/> +<wire x1="48.26" y1="55.88" x2="48.26" y2="40.64" width="0.1524" layer="91"/> +<junction x="48.26" y="55.88"/> </segment> <segment> <pinref part="U$8" gate="G$1" pin="VIN"/> @@ -37185,57 +37479,54 @@ be allowed to turn off the entropy source </segment> <segment> <pinref part="R22" gate="G$1" pin="1"/> -<wire x1="-7.62" y1="66.04" x2="-7.62" y2="63.5" width="0.1524" layer="91"/> +<wire x1="12.7" y1="63.5" x2="12.7" y2="60.96" width="0.1524" layer="91"/> <pinref part="PWR_18V4" gate="VCC" pin="VCC"/> -<label x="-5.08" y="66.04" size="1.778" layer="95"/> +<label x="15.24" y="63.5" size="1.778" layer="95"/> </segment> </net> <net name="N$1" class="0"> <segment> <pinref part="C1" gate="G$1" pin="1"/> <pinref part="U$9" gate="G$1" pin="ADJ"/> -<wire x1="76.2" y1="50.8" x2="73.66" y2="50.8" width="0.1524" layer="91"/> +<wire x1="96.52" y1="48.26" x2="93.98" y2="48.26" width="0.1524" layer="91"/> </segment> </net> <net name="N$2" class="0"> <segment> <pinref part="C4" gate="G$1" pin="2"/> <pinref part="U$9" gate="G$1" pin="REF/BYP"/> -<wire x1="76.2" y1="43.18" x2="73.66" y2="43.18" width="0.1524" layer="91"/> +<wire x1="96.52" y1="40.64" x2="93.98" y2="40.64" width="0.1524" layer="91"/> </segment> </net> <net name="15V_LDO_ENABLE" class="0"> <segment> <pinref part="U$9" gate="G$1" pin="!SHDN"/> -<wire x1="43.18" y1="50.8" x2="-2.54" y2="50.8" width="0.1524" layer="91"/> -</segment> -<segment> +<wire x1="63.5" y1="48.26" x2="12.7" y2="48.26" width="0.1524" layer="91"/> <pinref part="JP2" gate="A" pin="1"/> -<label x="0" y="52.07" size="1.778" layer="95"/> +<label x="20.32" y="49.53" size="1.778" layer="95"/> <pinref part="R22" gate="G$1" pin="2"/> -<wire x1="-7.62" y1="50.8" x2="-2.54" y2="50.8" width="0.1524" layer="91"/> -<wire x1="-7.62" y1="53.34" x2="-7.62" y2="50.8" width="0.1524" layer="91"/> -<wire x1="-13.97" y1="50.8" x2="-7.62" y2="50.8" width="0.1524" layer="91"/> -<junction x="-7.62" y="50.8"/> +<wire x1="12.7" y1="50.8" x2="12.7" y2="48.26" width="0.1524" layer="91"/> +<wire x1="6.35" y1="48.26" x2="12.7" y2="48.26" width="0.1524" layer="91"/> +<junction x="12.7" y="48.26"/> </segment> </net> <net name="15V_STABLE" class="0"> <segment> <pinref part="U$9" gate="G$1" pin="OUT"/> -<wire x1="73.66" y1="58.42" x2="76.2" y2="58.42" width="0.1524" layer="91"/> -<label x="99.06" y="58.42" size="1.778" layer="95" xref="yes"/> +<wire x1="93.98" y1="55.88" x2="96.52" y2="55.88" width="0.1524" layer="91"/> +<label x="119.38" y="55.88" size="1.778" layer="95" xref="yes"/> <pinref part="C1" gate="G$1" pin="2"/> -<wire x1="76.2" y1="58.42" x2="88.9" y2="58.42" width="0.1524" layer="91"/> -<junction x="76.2" y="58.42"/> +<wire x1="96.52" y1="55.88" x2="109.22" y2="55.88" width="0.1524" layer="91"/> +<junction x="96.52" y="55.88"/> <pinref part="C5" gate="G$1" pin="1"/> -<wire x1="88.9" y1="58.42" x2="96.52" y2="58.42" width="0.1524" layer="91"/> -<wire x1="96.52" y1="58.42" x2="99.06" y2="58.42" width="0.1524" layer="91"/> -<wire x1="88.9" y1="48.26" x2="88.9" y2="58.42" width="0.1524" layer="91"/> -<junction x="88.9" y="58.42"/> +<wire x1="109.22" y1="55.88" x2="116.84" y2="55.88" width="0.1524" layer="91"/> +<wire x1="116.84" y1="55.88" x2="119.38" y2="55.88" width="0.1524" layer="91"/> +<wire x1="109.22" y1="45.72" x2="109.22" y2="55.88" width="0.1524" layer="91"/> +<junction x="109.22" y="55.88"/> <pinref part="PWR_18V2" gate="VCC" pin="VCC"/> -<wire x1="96.52" y1="66.04" x2="96.52" y2="58.42" width="0.1524" layer="91"/> -<junction x="96.52" y="58.42"/> -<label x="99.06" y="66.04" size="1.778" layer="95"/> +<wire x1="116.84" y1="63.5" x2="116.84" y2="55.88" width="0.1524" layer="91"/> +<junction x="116.84" y="55.88"/> +<label x="119.38" y="63.5" size="1.778" layer="95"/> </segment> </net> <net name="N$52" class="0"> @@ -37289,11 +37580,11 @@ be allowed to turn off the entropy source <pinref part="R65" gate="G$1" pin="2"/> <junction x="25.4" y="-40.64"/> <wire x1="25.4" y1="-45.72" x2="25.4" y2="-40.64" width="0.1524" layer="91"/> -<wire x1="12.7" y1="-40.64" x2="25.4" y2="-40.64" width="0.1524" layer="91"/> <wire x1="50.8" y1="-45.72" x2="50.8" y2="-40.64" width="0.1524" layer="91"/> <wire x1="50.8" y1="-40.64" x2="35.56" y2="-40.64" width="0.1524" layer="91"/> <pinref part="C111" gate="G$1" pin="+"/> -<wire x1="35.56" y1="-40.64" x2="12.7" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="35.56" y1="-40.64" x2="25.4" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="25.4" y1="-40.64" x2="12.7" y2="-40.64" width="0.1524" layer="91"/> <wire x1="66.04" y1="-48.26" x2="66.04" y2="-40.64" width="0.1524" layer="91"/> <wire x1="66.04" y1="-40.64" x2="50.8" y2="-40.64" width="0.1524" layer="91"/> <junction x="50.8" y="-40.64"/> @@ -37316,27 +37607,27 @@ be allowed to turn off the entropy source <segment> <pinref part="R76" gate="G$1" pin="2"/> <pinref part="Q1" gate="G$1" pin="G"/> -<wire x1="-58.42" y1="39.37" x2="-53.34" y2="39.37" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="36.83" x2="-33.02" y2="36.83" width="0.1524" layer="91"/> <pinref part="R75" gate="G$1" pin="1"/> -<wire x1="-53.34" y1="39.37" x2="-48.26" y2="39.37" width="0.1524" layer="91"/> -<wire x1="-53.34" y1="34.29" x2="-53.34" y2="39.37" width="0.1524" layer="91"/> -<junction x="-53.34" y="39.37"/> +<wire x1="-33.02" y1="36.83" x2="-27.94" y2="36.83" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="31.75" x2="-33.02" y2="36.83" width="0.1524" layer="91"/> +<junction x="-33.02" y="36.83"/> </segment> </net> <net name="N$14" class="0"> <segment> <pinref part="Q1" gate="G$1" pin="D"/> -<wire x1="-38.1" y1="44.45" x2="-33.02" y2="44.45" width="0.1524" layer="91"/> -<wire x1="-33.02" y1="44.45" x2="-33.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="41.91" x2="-12.7" y2="41.91" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="41.91" x2="-12.7" y2="48.26" width="0.1524" layer="91"/> <pinref part="JP2" gate="A" pin="2"/> -<wire x1="-29.21" y1="50.8" x2="-33.02" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-8.89" y1="48.26" x2="-12.7" y2="48.26" width="0.1524" layer="91"/> </segment> </net> <net name="FPGA_ENTROPY_DISABLE" class="0"> <segment> <pinref part="R76" gate="G$1" pin="1"/> -<wire x1="-68.58" y1="39.37" x2="-76.2" y2="39.37" width="0.1524" layer="91"/> -<label x="-76.2" y="39.37" size="1.778" layer="95" rot="R180" xref="yes"/> +<wire x1="-48.26" y1="36.83" x2="-55.88" y2="36.83" width="0.1524" layer="91"/> +<label x="-55.88" y="36.83" size="1.778" layer="95" rot="R180" xref="yes"/> </segment> </net> </nets> @@ -37434,13 +37725,13 @@ for the Alpha.</text> </net> <net name="AMPLIFIED" class="0"> <segment> -<wire x1="63.5" y1="30.48" x2="45.72" y2="30.48" width="0.1524" layer="91"/> -<label x="45.72" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="63.5" y1="30.48" x2="33.02" y2="30.48" width="0.1524" layer="91"/> +<label x="33.02" y="30.48" size="1.27" layer="95"/> <pinref part="U2" gate="A" pin="IN_A"/> </segment> <segment> -<wire x1="7.62" y1="30.48" x2="11.43" y2="30.48" width="0.1524" layer="91"/> -<label x="11.43" y="30.48" size="1.27" layer="95" xref="yes"/> +<wire x1="7.62" y1="30.48" x2="26.67" y2="30.48" width="0.1524" layer="91"/> +<label x="16.51" y="30.48" size="1.27" layer="95"/> <wire x1="-5.08" y1="40.64" x2="-5.08" y2="35.56" width="0.1524" layer="91"/> <junction x="-5.08" y="30.48"/> <junction x="-5.08" y="30.48"/> @@ -37517,18 +37808,18 @@ for the Alpha.</text> <wire x1="-100.33" y1="20.32" x2="-100.33" y2="10.16" width="0.1524" layer="91"/> <pinref part="R2" gate="G$1" pin="2"/> <wire x1="-100.33" y1="20.32" x2="-100.33" y2="22.86" width="0.1524" layer="91"/> -<label x="-86.36" y="20.32" size="1.27" layer="95" xref="yes"/> +<label x="-76.2" y="20.32" size="1.27" layer="95"/> <junction x="-100.33" y="20.32"/> <wire x1="-100.33" y1="20.32" x2="-92.71" y2="20.32" width="0.1524" layer="91"/> <pinref part="TP2" gate="G$1" pin="TP"/> -<wire x1="-92.71" y1="20.32" x2="-86.36" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-92.71" y1="20.32" x2="-66.04" y2="20.32" width="0.1524" layer="91"/> <wire x1="-92.71" y1="20.32" x2="-92.71" y2="22.86" width="0.1524" layer="91"/> <junction x="-92.71" y="20.32"/> </segment> <segment> <pinref part="C2" gate="G$1" pin="1"/> -<wire x1="-33.02" y1="20.32" x2="-39.37" y2="20.32" width="0.1524" layer="91"/> -<label x="-39.37" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-33.02" y1="20.32" x2="-57.15" y2="20.32" width="0.1524" layer="91"/> +<label x="-57.15" y="20.32" size="1.27" layer="95"/> </segment> </net> <net name="AMP_P1" class="0"> @@ -37908,7 +38199,7 @@ One 10uF bypass cap for the package. </instance> <instance part="SUPPLY25" gate="GND" x="53.34" y="-20.32"/> <instance part="P+10" gate="VCC" x="53.34" y="7.62" smashed="yes"/> -<instance part="P+11" gate="VCC" x="106.68" y="19.05" smashed="yes"/> +<instance part="P+11" gate="VCC" x="106.68" y="21.59" smashed="yes"/> <instance part="SUPPLY26" gate="GND" x="106.68" y="-20.32"/> <instance part="C18" gate="G$1" x="152.4" y="7.62" smashed="yes"> <attribute name="NAME" x="152.4" y="12.7" size="1.27" layer="95" font="vector"/> @@ -38154,9 +38445,8 @@ One 10uF bypass cap for the package. <net name="VCCO_3V3" class="0"> <segment> <pinref part="C29" gate="G$1" pin="1"/> -<wire x1="106.68" y1="15.24" x2="106.68" y2="16.51" width="0.1524" layer="91"/> <pinref part="C18" gate="G$1" pin="1"/> -<wire x1="106.68" y1="16.51" x2="106.68" y2="10.16" width="0.1524" layer="91"/> +<wire x1="106.68" y1="19.05" x2="106.68" y2="10.16" width="0.1524" layer="91"/> <wire x1="106.68" y1="10.16" x2="111.76" y2="10.16" width="0.1524" layer="91"/> <junction x="106.68" y="10.16"/> <wire x1="111.76" y1="10.16" x2="116.84" y2="10.16" width="0.1524" layer="91"/> @@ -38247,7 +38537,6 @@ One 10uF bypass cap for the package. <label x="55.88" y="5.08" size="1.778" layer="95"/> </segment> <segment> -<wire x1="-142.24" y1="48.26" x2="-142.24" y2="49.53" width="0.1524" layer="91"/> <pinref part="P+65" gate="VCC" pin="VCC"/> <label x="-160.02" y="48.26" size="1.778" layer="95"/> <wire x1="-142.24" y1="49.53" x2="-142.24" y2="33.02" width="0.1524" layer="91"/> @@ -38369,20 +38658,14 @@ One 10uF bypass cap for the package. <sheet> <description>ARM I/O</description> <plain> -<text x="-12.7" y="91.44" size="1.27" layer="91">FPGA_DONE can be swapped with any -other available GPIO pin on the ARM</text> -<text x="-170.18" y="66.04" size="1.27" layer="91">XXX cross RTS/CTS?</text> -<text x="-175.26" y="50.8" size="1.27" layer="91">XXX cross RTS/CTS?</text> -<text x="-17.78" y="100.33" size="1.778" layer="91">*) FPGA_GPIO_*, FPGA_IRQ_N_* and -FPGA_{PROGRAM,INIT}_B signals -can be swapped with any other -available GPIO on the ARM</text> +<text x="-121.92" y="-95.25" size="1.778" layer="91">All of these input/outputs can be swapped +with equivalent functionality pins.</text> <text x="-167.64" y="104.14" size="3.81" layer="91">Input/output, STM32</text> </plain> <instances> <instance part="FRAME25" gate="G$1" x="-193.04" y="-129.54"/> <instance part="U$1" gate="FMC" x="99.06" y="2.54"/> -<instance part="U$1" gate="IO" x="-83.82" y="-7.62"/> +<instance part="U$1" gate="IO" x="-83.82" y="0"/> </instances> <busses> <bus name="FMC_D[0..31],FMC_A[0..25]"> @@ -38876,29 +39159,29 @@ available GPIO on the ARM</text> <net name="FT_TXD" class="0"> <segment> <pinref part="U$1" gate="IO" pin="USART2_RX/PA3"/> -<wire x1="-124.46" y1="71.12" x2="-132.08" y2="71.12" width="0.1524" layer="91"/> -<label x="-132.08" y="71.12" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="68.58" x2="-132.08" y2="68.58" width="0.1524" layer="91"/> +<label x="-132.08" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FT_RXD" class="0"> <segment> <pinref part="U$1" gate="IO" pin="USART2_TX/PA2"/> -<wire x1="-124.46" y1="73.66" x2="-132.08" y2="73.66" width="0.1524" layer="91"/> -<label x="-132.08" y="73.66" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="71.12" x2="-132.08" y2="71.12" width="0.1524" layer="91"/> +<label x="-132.08" y="71.12" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="ARM_LED1" class="0"> <segment> -<wire x1="-45.72" y1="-7.62" x2="-38.1" y2="-7.62" width="0.1524" layer="91"/> -<label x="-38.1" y="-7.62" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ4"/> +<wire x1="-45.72" y1="2.54" x2="-38.1" y2="2.54" width="0.1524" layer="91"/> +<label x="-38.1" y="2.54" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ0"/> </segment> </net> <net name="ARM_LED2" class="0"> <segment> -<wire x1="-45.72" y1="-5.08" x2="-38.1" y2="-5.08" width="0.1524" layer="91"/> -<label x="-38.1" y="-5.08" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ3"/> +<wire x1="-45.72" y1="0" x2="-38.1" y2="0" width="0.1524" layer="91"/> +<label x="-38.1" y="0" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ1"/> </segment> </net> <net name="ARM_LED3" class="0"> @@ -38910,15 +39193,16 @@ available GPIO on the ARM</text> </net> <net name="ARM_LED4" class="0"> <segment> -<wire x1="-45.72" y1="0" x2="-38.1" y2="0" width="0.1524" layer="91"/> -<label x="-38.1" y="0" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ1"/> +<wire x1="-45.72" y1="-5.08" x2="-38.1" y2="-5.08" width="0.1524" layer="91"/> +<label x="-38.1" y="-5.08" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ3"/> </segment> </net> <net name="AVR_GPIO_11" class="0"> <segment> <wire x1="-132.08" y1="-68.58" x2="-124.46" y2="-68.58" width="0.1524" layer="91"/> <label x="-132.08" y="-68.58" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PC14"/> </segment> </net> <net name="AVR_GPIO_10" class="0"> @@ -38930,89 +39214,89 @@ available GPIO on the ARM</text> </net> <net name="RTC_SCL" class="0"> <segment> +<wire x1="-124.46" y1="-12.7" x2="-132.08" y2="-12.7" width="0.1524" layer="91"/> +<label x="-132.08" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="I2C2_SCL/PH4"/> -<wire x1="-124.46" y1="-5.08" x2="-132.08" y2="-5.08" width="0.1524" layer="91"/> -<label x="-132.08" y="-5.08" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="RTC_SDA" class="0"> <segment> -<pinref part="U$1" gate="IO" pin="I2C2_SDA/FMC_SDNWE/PH5"/> -<wire x1="-124.46" y1="-2.54" x2="-132.08" y2="-2.54" width="0.1524" layer="91"/> -<label x="-132.08" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="-10.16" x2="-132.08" y2="-10.16" width="0.1524" layer="91"/> +<label x="-132.08" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="I2C2_SDA/PH5"/> </segment> </net> <net name="RTC_MFP" class="0"> <segment> -<wire x1="-124.46" y1="-7.62" x2="-132.08" y2="-7.62" width="0.1524" layer="91"/> -<label x="-132.08" y="-7.62" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PH3/FMC_SDNE0"/> +<wire x1="-124.46" y1="-15.24" x2="-132.08" y2="-15.24" width="0.1524" layer="91"/> +<label x="-132.08" y="-15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PH3"/> </segment> </net> <net name="FPGA_IRQ_N_0" class="0"> <segment> -<wire x1="-45.72" y1="-30.48" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> -<label x="-38.1" y="-30.48" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ13"/> +<wire x1="-45.72" y1="-22.86" x2="-38.1" y2="-22.86" width="0.1524" layer="91"/> +<label x="-38.1" y="-22.86" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ10"/> </segment> </net> <net name="FPGA_IRQ_N_1" class="0"> <segment> -<wire x1="-45.72" y1="-27.94" x2="-38.1" y2="-27.94" width="0.1524" layer="91"/> -<label x="-38.1" y="-27.94" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ12"/> +<wire x1="-45.72" y1="-25.4" x2="-38.1" y2="-25.4" width="0.1524" layer="91"/> +<label x="-38.1" y="-25.4" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ11"/> </segment> </net> <net name="FPGA_IRQ_N_2" class="0"> <segment> -<wire x1="-45.72" y1="-25.4" x2="-38.1" y2="-25.4" width="0.1524" layer="91"/> -<label x="-38.1" y="-25.4" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ11"/> +<wire x1="-45.72" y1="-27.94" x2="-38.1" y2="-27.94" width="0.1524" layer="91"/> +<label x="-38.1" y="-27.94" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ12"/> </segment> </net> <net name="FPGA_IRQ_N_3" class="0"> <segment> -<wire x1="-45.72" y1="-22.86" x2="-38.1" y2="-22.86" width="0.1524" layer="91"/> -<label x="-38.1" y="-22.86" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ10"/> +<wire x1="-45.72" y1="-30.48" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> +<label x="-38.1" y="-30.48" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ13"/> </segment> </net> <net name="FPGA_PROGRAM_B" class="0"> <segment> -<wire x1="-45.72" y1="-35.56" x2="-38.1" y2="-35.56" width="0.1524" layer="91"/> -<label x="-38.1" y="-35.56" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ15"/> +<wire x1="-45.72" y1="-17.78" x2="-38.1" y2="-17.78" width="0.1524" layer="91"/> +<label x="-38.1" y="-17.78" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ8"/> </segment> </net> <net name="FPGA_INIT_B" class="0"> <segment> -<wire x1="-45.72" y1="-33.02" x2="-38.1" y2="-33.02" width="0.1524" layer="91"/> -<label x="-38.1" y="-33.02" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ14"/> +<wire x1="-45.72" y1="-15.24" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> +<label x="-38.1" y="-15.24" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ7"/> </segment> </net> <net name="ARM_FPGA_CFG_SCLK" class="0"> <segment> -<wire x1="-124.46" y1="43.18" x2="-132.08" y2="43.18" width="0.1524" layer="91"/> -<label x="-132.08" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="35.56" x2="-132.08" y2="35.56" width="0.1524" layer="91"/> +<label x="-132.08" y="35.56" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI2_SCK/PB13"/> </segment> </net> <net name="ARM_FPGA_CFG_MISO" class="0"> <segment> -<wire x1="-124.46" y1="40.64" x2="-132.08" y2="40.64" width="0.1524" layer="91"/> -<label x="-132.08" y="40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="33.02" x2="-132.08" y2="33.02" width="0.1524" layer="91"/> +<label x="-132.08" y="33.02" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI2_MISO/PB14"/> </segment> </net> <net name="ARM_FPGA_CFG_MOSI" class="0"> <segment> -<wire x1="-124.46" y1="38.1" x2="-132.08" y2="38.1" width="0.1524" layer="91"/> -<label x="-132.08" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="30.48" x2="-132.08" y2="30.48" width="0.1524" layer="91"/> +<label x="-132.08" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI2_MOSI/PB15"/> </segment> </net> -<net name="ARM_FPGA_CFG_CONTROL" class="0"> +<net name="FPGA_CFG_CTRL_ARM_ENA" class="0"> <segment> <wire x1="-45.72" y1="-12.7" x2="-38.1" y2="-12.7" width="0.1524" layer="91"/> <label x="-38.1" y="-12.7" size="1.27" layer="95" xref="yes"/> @@ -39021,114 +39305,142 @@ available GPIO on the ARM</text> </net> <net name="KSM_PROM_SCLK" class="0"> <segment> -<wire x1="-124.46" y1="30.48" x2="-132.08" y2="30.48" width="0.1524" layer="91"/> -<label x="-132.08" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="22.86" x2="-132.08" y2="22.86" width="0.1524" layer="91"/> +<label x="-132.08" y="22.86" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI1_SCK/PA5"/> </segment> </net> <net name="KSM_PROM_MISO" class="0"> <segment> -<wire x1="-124.46" y1="27.94" x2="-132.08" y2="27.94" width="0.1524" layer="91"/> -<label x="-132.08" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="20.32" x2="-132.08" y2="20.32" width="0.1524" layer="91"/> +<label x="-132.08" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI1_MISO/PA6"/> </segment> </net> <net name="KSM_PROM_MOSI" class="0"> <segment> -<wire x1="-124.46" y1="25.4" x2="-132.08" y2="25.4" width="0.1524" layer="91"/> -<label x="-132.08" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="17.78" x2="-132.08" y2="17.78" width="0.1524" layer="91"/> +<label x="-132.08" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SPI1_MOSI/PA7"/> </segment> </net> <net name="SDIO_CK" class="0"> <segment> -<wire x1="-124.46" y1="15.24" x2="-132.08" y2="15.24" width="0.1524" layer="91"/> -<label x="-132.08" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U$1" gate="IO" pin="SDIO_CK/SPI3_MOSI/PC12"/> +<wire x1="-124.46" y1="7.62" x2="-132.08" y2="7.62" width="0.1524" layer="91"/> +<label x="-132.08" y="7.62" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="SDIO_CK/PC12"/> </segment> </net> <net name="SDIO_CMD" class="0"> <segment> -<wire x1="-124.46" y1="17.78" x2="-132.08" y2="17.78" width="0.1524" layer="91"/> -<label x="-132.08" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="10.16" x2="-132.08" y2="10.16" width="0.1524" layer="91"/> +<label x="-132.08" y="10.16" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SDIO_CMD/PD2"/> </segment> </net> <net name="SDIO_D3" class="0"> <segment> -<wire x1="-124.46" y1="5.08" x2="-132.08" y2="5.08" width="0.1524" layer="91"/> -<label x="-132.08" y="5.08" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U$1" gate="IO" pin="SDIO_D3/SPI3_MISO/PC11"/> +<wire x1="-124.46" y1="-2.54" x2="-132.08" y2="-2.54" width="0.1524" layer="91"/> +<label x="-132.08" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="SDIO_D3/PC11"/> </segment> </net> <net name="SDIO_D2" class="0"> <segment> -<wire x1="-124.46" y1="7.62" x2="-132.08" y2="7.62" width="0.1524" layer="91"/> -<label x="-132.08" y="7.62" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U$1" gate="IO" pin="SDIO_D2/SPI3_SCK/PC10"/> +<wire x1="-124.46" y1="0" x2="-132.08" y2="0" width="0.1524" layer="91"/> +<label x="-132.08" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="SDIO_D2/PC10"/> </segment> </net> <net name="SDIO_D0" class="0"> <segment> -<wire x1="-124.46" y1="12.7" x2="-132.08" y2="12.7" width="0.1524" layer="91"/> -<label x="-132.08" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="5.08" x2="-132.08" y2="5.08" width="0.1524" layer="91"/> +<label x="-132.08" y="5.08" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SDIO_D0/PC8"/> </segment> </net> <net name="SDIO_D1" class="0"> <segment> -<wire x1="-124.46" y1="10.16" x2="-132.08" y2="10.16" width="0.1524" layer="91"/> -<label x="-132.08" y="10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="2.54" x2="-132.08" y2="2.54" width="0.1524" layer="91"/> +<label x="-132.08" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> <pinref part="U$1" gate="IO" pin="SDIO_D1/PC9"/> </segment> </net> <net name="FT_RTS" class="0"> <segment> -<pinref part="U$1" gate="IO" pin="USART2_RTS/PA1"/> -<wire x1="-124.46" y1="68.58" x2="-132.08" y2="68.58" width="0.1524" layer="91"/> -<label x="-132.08" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="63.5" x2="-132.08" y2="63.5" width="0.1524" layer="91"/> +<label x="-132.08" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="USART2_CTS/WKUP/PA0"/> </segment> </net> <net name="FT_CTS" class="0"> <segment> <wire x1="-124.46" y1="66.04" x2="-132.08" y2="66.04" width="0.1524" layer="91"/> <label x="-132.08" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U$1" gate="IO" pin="USART2_CTS/WKUP/PA0"/> +<pinref part="U$1" gate="IO" pin="USART2_RTS/PA1"/> </segment> </net> <net name="FT_MGMT_RXD" class="0"> <segment> -<wire x1="-124.46" y1="55.88" x2="-132.08" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-124.46" y1="53.34" x2="-132.08" y2="53.34" width="0.1524" layer="91"/> <pinref part="U$1" gate="IO" pin="USART1_TX/PA9"/> -<label x="-132.08" y="55.88" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-132.08" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FT_MGMT_TXD" class="0"> <segment> -<wire x1="-124.46" y1="58.42" x2="-132.08" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-124.46" y1="50.8" x2="-132.08" y2="50.8" width="0.1524" layer="91"/> <pinref part="U$1" gate="IO" pin="USART1_RX/PA10"/> -<label x="-132.08" y="58.42" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-132.08" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FT_MGMT_CTS" class="0"> <segment> -<wire x1="-124.46" y1="50.8" x2="-132.08" y2="50.8" width="0.1524" layer="91"/> -<pinref part="U$1" gate="IO" pin="USART1_CTS/PA11"/> -<label x="-132.08" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="48.26" x2="-132.08" y2="48.26" width="0.1524" layer="91"/> +<label x="-132.08" y="48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="USART1_RTS/PA12"/> </segment> </net> <net name="FT_MGMT_RTS" class="0"> <segment> -<wire x1="-124.46" y1="53.34" x2="-132.08" y2="53.34" width="0.1524" layer="91"/> -<pinref part="U$1" gate="IO" pin="USART1_RTS/PA12"/> -<label x="-132.08" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-124.46" y1="45.72" x2="-132.08" y2="45.72" width="0.1524" layer="91"/> +<label x="-132.08" y="45.72" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U$1" gate="IO" pin="USART1_CTS/PA11"/> </segment> </net> <net name="FPGA_DONE" class="0"> <segment> -<wire x1="-45.72" y1="-15.24" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> -<label x="-38.1" y="-15.24" size="1.27" layer="95" xref="yes"/> -<pinref part="U$1" gate="IO" pin="PJ7"/> +<wire x1="-45.72" y1="-35.56" x2="-38.1" y2="-35.56" width="0.1524" layer="91"/> +<label x="-38.1" y="-35.56" size="1.27" layer="95" xref="yes"/> +<pinref part="U$1" gate="IO" pin="PJ15"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_FPGA_DIS" class="0"> +<segment> +<pinref part="U$1" gate="IO" pin="PJ5"/> +<wire x1="-45.72" y1="-10.16" x2="-38.1" y2="-10.16" width="0.1524" layer="91"/> +<label x="-38.1" y="-10.16" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_DTR" class="0"> +<segment> +<pinref part="U$1" gate="IO" pin="PA4"/> +<wire x1="-124.46" y1="73.66" x2="-132.08" y2="73.66" width="0.1524" layer="91"/> +<label x="-132.08" y="73.66" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_DTR" class="0"> +<segment> +<pinref part="U$1" gate="IO" pin="PA8"/> +<wire x1="-124.46" y1="55.88" x2="-132.08" y2="55.88" width="0.1524" layer="91"/> +<label x="-132.08" y="55.88" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_CS_N" class="0"> +<segment> +<pinref part="U$1" gate="IO" pin="PB12"/> +<wire x1="-124.46" y1="38.1" x2="-132.08" y2="38.1" width="0.1524" layer="91"/> +<label x="-132.08" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> </nets> @@ -39136,121 +39448,122 @@ available GPIO on the ARM</text> <sheet> <description>SDRAM</description> <plain> +<text x="-63.5" y="109.22" size="3.81" layer="91">2x512 Mbit SDRAM memory for the ARM</text> </plain> <instances> <instance part="FRAME22" gate="G$1" x="-193.04" y="-129.54"/> -<instance part="IC1" gate="G$1" x="-88.9" y="38.1"/> -<instance part="P+59" gate="VCC" x="-104.14" y="105.41" smashed="yes"/> -<instance part="P+60" gate="VCC" x="-91.44" y="105.41" smashed="yes"/> -<instance part="SUPPLY215" gate="GND" x="-88.9" y="-30.48"/> -<instance part="P+58" gate="VCC" x="-114.3" y="-36.83" smashed="yes"/> -<instance part="SUPPLY214" gate="GND" x="-114.3" y="-76.2"/> -<instance part="C194" gate="G$1" x="-88.9" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-88.9" y="-43.18" size="1.27" layer="95" font="vector"/> +<instance part="IC1" gate="G$1" x="-88.9" y="25.4"/> +<instance part="P+59" gate="VCC" x="-104.14" y="92.71" smashed="yes"/> +<instance part="P+60" gate="VCC" x="-91.44" y="92.71" smashed="yes"/> +<instance part="SUPPLY215" gate="GND" x="-88.9" y="-43.18"/> +<instance part="P+58" gate="VCC" x="-114.3" y="-49.53" smashed="yes"/> +<instance part="SUPPLY214" gate="GND" x="-114.3" y="-88.9"/> +<instance part="C194" gate="G$1" x="-88.9" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-88.9" y="-55.88" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C195" gate="G$1" x="-93.98" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-93.98" y="-43.18" size="1.27" layer="95" font="vector"/> +<instance part="C195" gate="G$1" x="-93.98" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-93.98" y="-55.88" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C196" gate="G$1" x="-99.06" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-99.06" y="-43.18" size="1.27" layer="95" font="vector"/> +<instance part="C196" gate="G$1" x="-99.06" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-99.06" y="-55.88" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C197" gate="G$1" x="-104.14" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-104.14" y="-43.18" size="1.27" layer="95" font="vector"/> -<attribute name="DIELECTRIC" x="-104.14" y="-48.26" size="1.6764" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="-104.14" y="-48.26" size="1.6764" layer="96" display="off"/> +<instance part="C197" gate="G$1" x="-104.14" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-104.14" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="-104.14" y="-60.96" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-104.14" y="-60.96" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C198" gate="G$1" x="-104.14" y="-60.96" smashed="yes"> -<attribute name="NAME" x="-106.68" y="-68.58" size="1.27" layer="95" font="vector"/> +<instance part="C198" gate="G$1" x="-104.14" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-106.68" y="-81.28" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C199" gate="G$1" x="-109.22" y="-60.96" smashed="yes"> -<attribute name="NAME" x="-111.76" y="-68.58" size="1.27" layer="95" font="vector"/> +<instance part="C199" gate="G$1" x="-109.22" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-111.76" y="-81.28" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C200" gate="G$1" x="-109.22" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-109.22" y="-43.18" size="1.27" layer="95" font="vector"/> -<attribute name="RATED_VOLTAGE" x="-109.22" y="-48.26" size="1.6764" layer="96" display="off"/> +<instance part="C200" gate="G$1" x="-109.22" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-109.22" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="RATED_VOLTAGE" x="-109.22" y="-60.96" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C201" gate="G$1" x="-114.3" y="-48.26" smashed="yes"> -<attribute name="NAME" x="-114.3" y="-43.18" size="1.27" layer="95" font="vector"/> -<attribute name="DIELECTRIC" x="-114.3" y="-48.26" size="1.6764" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="-114.3" y="-48.26" size="1.6764" layer="96" display="off"/> +<instance part="C201" gate="G$1" x="-114.3" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-114.3" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="-114.3" y="-60.96" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-114.3" y="-60.96" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C206" gate="G$1" x="-88.9" y="-60.96" smashed="yes"> -<attribute name="NAME" x="-91.44" y="-68.58" size="1.27" layer="95" font="vector"/> +<instance part="C206" gate="G$1" x="-88.9" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-91.44" y="-81.28" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C207" gate="G$1" x="-93.98" y="-60.96" smashed="yes"> -<attribute name="NAME" x="-96.52" y="-68.58" size="1.27" layer="95" font="vector"/> +<instance part="C207" gate="G$1" x="-93.98" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-96.52" y="-81.28" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C208" gate="G$1" x="-99.06" y="-60.96" smashed="yes"> -<attribute name="NAME" x="-101.6" y="-68.58" size="1.27" layer="95" font="vector"/> +<instance part="C208" gate="G$1" x="-99.06" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-101.6" y="-81.28" size="1.27" layer="95" font="vector"/> </instance> -<instance part="IC2" gate="G$1" x="88.9" y="35.56"/> -<instance part="P+61" gate="VCC" x="73.66" y="102.87" smashed="yes"/> -<instance part="P+62" gate="VCC" x="86.36" y="102.87" smashed="yes"/> -<instance part="SUPPLY216" gate="GND" x="88.9" y="-33.02"/> -<instance part="P+63" gate="VCC" x="63.5" y="-39.37" smashed="yes"/> -<instance part="SUPPLY217" gate="GND" x="63.5" y="-78.74"/> -<instance part="C190" gate="G$1" x="88.9" y="-50.8" smashed="yes"> -<attribute name="NAME" x="88.9" y="-45.72" size="1.27" layer="95" font="vector"/> +<instance part="IC2" gate="G$1" x="88.9" y="22.86"/> +<instance part="P+61" gate="VCC" x="73.66" y="90.17" smashed="yes"/> +<instance part="P+62" gate="VCC" x="86.36" y="90.17" smashed="yes"/> +<instance part="SUPPLY216" gate="GND" x="88.9" y="-45.72"/> +<instance part="P+63" gate="VCC" x="63.5" y="-52.07" smashed="yes"/> +<instance part="SUPPLY217" gate="GND" x="63.5" y="-91.44"/> +<instance part="C190" gate="G$1" x="88.9" y="-63.5" smashed="yes"> +<attribute name="NAME" x="88.9" y="-58.42" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C191" gate="G$1" x="83.82" y="-50.8" smashed="yes"> -<attribute name="NAME" x="83.82" y="-45.72" size="1.27" layer="95" font="vector"/> +<instance part="C191" gate="G$1" x="83.82" y="-63.5" smashed="yes"> +<attribute name="NAME" x="83.82" y="-58.42" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C192" gate="G$1" x="78.74" y="-50.8" smashed="yes"> -<attribute name="NAME" x="78.74" y="-45.72" size="1.27" layer="95" font="vector"/> +<instance part="C192" gate="G$1" x="78.74" y="-63.5" smashed="yes"> +<attribute name="NAME" x="78.74" y="-58.42" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C193" gate="G$1" x="73.66" y="-50.8" smashed="yes"> -<attribute name="NAME" x="73.66" y="-45.72" size="1.27" layer="95" font="vector"/> -<attribute name="DIELECTRIC" x="73.66" y="-50.8" size="1.6764" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="73.66" y="-50.8" size="1.6764" layer="96" display="off"/> +<instance part="C193" gate="G$1" x="73.66" y="-63.5" smashed="yes"> +<attribute name="NAME" x="73.66" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="73.66" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="73.66" y="-63.5" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C202" gate="G$1" x="73.66" y="-63.5" smashed="yes"> -<attribute name="NAME" x="71.12" y="-71.12" size="1.27" layer="95" font="vector"/> +<instance part="C202" gate="G$1" x="73.66" y="-76.2" smashed="yes"> +<attribute name="NAME" x="71.12" y="-83.82" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C203" gate="G$1" x="68.58" y="-63.5" smashed="yes"> -<attribute name="NAME" x="66.04" y="-71.12" size="1.27" layer="95" font="vector"/> +<instance part="C203" gate="G$1" x="68.58" y="-76.2" smashed="yes"> +<attribute name="NAME" x="66.04" y="-83.82" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C204" gate="G$1" x="68.58" y="-50.8" smashed="yes"> -<attribute name="NAME" x="68.58" y="-45.72" size="1.27" layer="95" font="vector"/> -<attribute name="RATED_VOLTAGE" x="68.58" y="-50.8" size="1.6764" layer="96" display="off"/> +<instance part="C204" gate="G$1" x="68.58" y="-63.5" smashed="yes"> +<attribute name="NAME" x="68.58" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="RATED_VOLTAGE" x="68.58" y="-63.5" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C205" gate="G$1" x="63.5" y="-50.8" smashed="yes"> -<attribute name="NAME" x="63.5" y="-45.72" size="1.27" layer="95" font="vector"/> -<attribute name="DIELECTRIC" x="63.5" y="-50.8" size="1.6764" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="63.5" y="-50.8" size="1.6764" layer="96" display="off"/> +<instance part="C205" gate="G$1" x="63.5" y="-63.5" smashed="yes"> +<attribute name="NAME" x="63.5" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="63.5" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="63.5" y="-63.5" size="1.6764" layer="96" display="off"/> </instance> -<instance part="C209" gate="G$1" x="88.9" y="-63.5" smashed="yes"> -<attribute name="NAME" x="86.36" y="-71.12" size="1.27" layer="95" font="vector"/> +<instance part="C209" gate="G$1" x="88.9" y="-76.2" smashed="yes"> +<attribute name="NAME" x="86.36" y="-83.82" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C210" gate="G$1" x="83.82" y="-63.5" smashed="yes"> -<attribute name="NAME" x="81.28" y="-71.12" size="1.27" layer="95" font="vector"/> +<instance part="C210" gate="G$1" x="83.82" y="-76.2" smashed="yes"> +<attribute name="NAME" x="81.28" y="-83.82" size="1.27" layer="95" font="vector"/> </instance> -<instance part="C211" gate="G$1" x="78.74" y="-63.5" smashed="yes"> -<attribute name="NAME" x="76.2" y="-71.12" size="1.27" layer="95" font="vector"/> +<instance part="C211" gate="G$1" x="78.74" y="-76.2" smashed="yes"> +<attribute name="NAME" x="76.2" y="-83.82" size="1.27" layer="95" font="vector"/> </instance> </instances> <busses> <bus name="FMC_A[0..25]"> <segment> -<wire x1="-134.62" y1="93.98" x2="-148.59" y2="93.98" width="0.762" layer="92"/> -<wire x1="-134.62" y1="93.98" x2="-134.62" y2="48.26" width="0.762" layer="92"/> -<label x="-151.13" y="96.52" size="1.778" layer="95"/> +<wire x1="-134.62" y1="81.28" x2="-148.59" y2="81.28" width="0.762" layer="92"/> +<wire x1="-134.62" y1="81.28" x2="-134.62" y2="35.56" width="0.762" layer="92"/> +<label x="-151.13" y="83.82" size="1.778" layer="95"/> </segment> <segment> -<wire x1="43.18" y1="91.44" x2="29.21" y2="91.44" width="0.762" layer="92"/> -<wire x1="43.18" y1="91.44" x2="43.18" y2="45.72" width="0.762" layer="92"/> -<label x="26.67" y="93.98" size="1.778" layer="95"/> +<wire x1="43.18" y1="78.74" x2="29.21" y2="78.74" width="0.762" layer="92"/> +<wire x1="43.18" y1="78.74" x2="43.18" y2="33.02" width="0.762" layer="92"/> +<label x="26.67" y="81.28" size="1.778" layer="95"/> </segment> </bus> <bus name="FMC_D[0..31]"> <segment> -<wire x1="-43.18" y1="10.16" x2="-43.18" y2="93.98" width="0.762" layer="92"/> -<wire x1="-43.18" y1="93.98" x2="-27.94" y2="93.98" width="0.762" layer="92"/> -<label x="-43.18" y="93.98" size="1.778" layer="95"/> +<wire x1="-43.18" y1="-2.54" x2="-43.18" y2="81.28" width="0.762" layer="92"/> +<wire x1="-43.18" y1="81.28" x2="-27.94" y2="81.28" width="0.762" layer="92"/> +<label x="-43.18" y="81.28" size="1.778" layer="95"/> </segment> <segment> -<wire x1="134.62" y1="7.62" x2="134.62" y2="91.44" width="0.762" layer="92"/> -<wire x1="134.62" y1="91.44" x2="149.86" y2="91.44" width="0.762" layer="92"/> -<label x="134.62" y="91.44" size="1.778" layer="95"/> +<wire x1="134.62" y1="-5.08" x2="134.62" y2="78.74" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.762" layer="92"/> +<label x="134.62" y="78.74" size="1.778" layer="95"/> </segment> </bus> </busses> @@ -39258,953 +39571,947 @@ available GPIO on the ARM</text> <net name="GND" class="1"> <segment> <pinref part="IC1" gate="G$1" pin="VSS@86"/> -<wire x1="-73.66" y1="-20.32" x2="-73.66" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-73.66" y1="-25.4" x2="-76.2" y2="-25.4" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="-33.02" x2="-73.66" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="-38.1" x2="-76.2" y2="-38.1" width="0.1524" layer="91"/> <pinref part="IC1" gate="G$1" pin="VSSQ@6"/> -<wire x1="-76.2" y1="-25.4" x2="-78.74" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-78.74" y1="-25.4" x2="-81.28" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-81.28" y1="-25.4" x2="-86.36" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-86.36" y1="-25.4" x2="-88.9" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-88.9" y1="-25.4" x2="-91.44" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-91.44" y1="-25.4" x2="-93.98" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-93.98" y1="-25.4" x2="-96.52" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-96.52" y1="-25.4" x2="-99.06" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-99.06" y1="-25.4" x2="-101.6" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-101.6" y1="-25.4" x2="-104.14" y2="-25.4" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="-25.4" x2="-104.14" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="-38.1" x2="-78.74" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="-38.1" x2="-81.28" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-38.1" x2="-88.9" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="-38.1" x2="-91.44" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="-38.1" x2="-93.98" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-38.1" x2="-96.52" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-38.1" x2="-99.06" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-38.1" x2="-101.6" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-101.6" y1="-38.1" x2="-104.14" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-38.1" x2="-104.14" y2="-33.02" width="0.1524" layer="91"/> <pinref part="IC1" gate="G$1" pin="VSSQ@12"/> -<wire x1="-101.6" y1="-20.32" x2="-101.6" y2="-25.4" width="0.1524" layer="91"/> -<junction x="-101.6" y="-25.4"/> +<wire x1="-101.6" y1="-33.02" x2="-101.6" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-101.6" y="-38.1"/> <pinref part="IC1" gate="G$1" pin="VSSQ@32"/> -<wire x1="-99.06" y1="-20.32" x2="-99.06" y2="-25.4" width="0.1524" layer="91"/> -<junction x="-99.06" y="-25.4"/> +<wire x1="-99.06" y1="-33.02" x2="-99.06" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-99.06" y="-38.1"/> <pinref part="IC1" gate="G$1" pin="VSSQ@38"/> -<wire x1="-96.52" y1="-20.32" x2="-96.52" y2="-25.4" width="0.1524" layer="91"/> -<junction x="-96.52" y="-25.4"/> +<wire x1="-96.52" y1="-33.02" x2="-96.52" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-96.52" y="-38.1"/> <pinref part="IC1" gate="G$1" pin="VSSQ@46"/> -<wire x1="-93.98" y1="-20.32" x2="-93.98" y2="-25.4" width="0.1524" layer="91"/> -<junction x="-93.98" y="-25.4"/> +<wire x1="-93.98" y1="-33.02" x2="-93.98" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-93.98" y="-38.1"/> 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pin="2"/> -<junction x="68.58" y="-55.88"/> +<junction x="68.58" y="-68.58"/> <pinref part="C209" gate="G$1" pin="2"/> -<wire x1="88.9" y1="-68.58" x2="83.82" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="88.9" y1="-81.28" x2="83.82" y2="-81.28" width="0.1524" layer="91"/> <pinref part="C210" gate="G$1" pin="2"/> -<junction x="83.82" y="-68.58"/> -<wire x1="83.82" y1="-68.58" x2="78.74" y2="-68.58" width="0.1524" layer="91"/> +<junction x="83.82" y="-81.28"/> +<wire x1="83.82" y1="-81.28" x2="78.74" y2="-81.28" width="0.1524" layer="91"/> <pinref part="C211" gate="G$1" pin="2"/> -<junction x="78.74" y="-68.58"/> -<wire x1="78.74" y1="-68.58" x2="73.66" y2="-68.58" width="0.1524" layer="91"/> +<junction x="78.74" y="-81.28"/> +<wire x1="78.74" y1="-81.28" x2="73.66" y2="-81.28" width="0.1524" layer="91"/> <pinref part="C202" gate="G$1" pin="2"/> -<junction x="73.66" y="-68.58"/> -<wire x1="73.66" y1="-68.58" x2="68.58" y2="-68.58" width="0.1524" layer="91"/> +<junction x="73.66" y="-81.28"/> +<wire x1="73.66" y1="-81.28" x2="68.58" y2="-81.28" width="0.1524" layer="91"/> <pinref part="C203" gate="G$1" pin="2"/> -<junction x="68.58" y="-68.58"/> -<wire x1="68.58" y1="-68.58" x2="63.5" y2="-68.58" width="0.1524" layer="91"/> +<junction x="68.58" y="-81.28"/> +<wire x1="68.58" y1="-81.28" x2="63.5" y2="-81.28" width="0.1524" layer="91"/> </segment> </net> <net name="VCCO_3V3" class="0"> <segment> -<wire x1="-104.14" y1="101.6" x2="-104.14" y2="102.87" width="0.1524" layer="91"/> <pinref part="P+59" gate="VCC" pin="VCC"/> -<wire x1="-104.14" y1="102.87" x2="-104.14" y2="99.06" width="0.1524" layer="91"/> -<label x="-119.38" y="101.6" size="1.778" layer="95"/> +<wire x1="-104.14" y1="90.17" x2="-104.14" y2="86.36" width="0.1524" layer="91"/> +<label x="-119.38" y="88.9" size="1.778" layer="95"/> <pinref part="IC1" gate="G$1" pin="VDD@43"/> -<wire x1="-104.14" y1="99.06" x2="-104.14" y2="96.52" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="99.06" x2="-101.6" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-101.6" y1="99.06" x2="-99.06" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-99.06" y1="99.06" x2="-96.52" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-96.52" y1="99.06" x2="-96.52" y2="96.52" width="0.1524" layer="91"/> -<junction x="-104.14" y="99.06"/> +<wire x1="-104.14" y1="86.36" x2="-104.14" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="86.36" x2="-101.6" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-101.6" y1="86.36" x2="-99.06" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="86.36" x2="-96.52" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="86.36" x2="-96.52" y2="83.82" width="0.1524" layer="91"/> +<junction x="-104.14" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDD@29"/> -<wire x1="-99.06" y1="96.52" x2="-99.06" y2="99.06" width="0.1524" layer="91"/> -<junction x="-99.06" y="99.06"/> +<wire x1="-99.06" y1="83.82" x2="-99.06" y2="86.36" width="0.1524" layer="91"/> +<junction x="-99.06" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDD@15"/> -<wire x1="-101.6" y1="96.52" x2="-101.6" y2="99.06" width="0.1524" layer="91"/> -<junction x="-101.6" y="99.06"/> +<wire x1="-101.6" y1="83.82" x2="-101.6" y2="86.36" width="0.1524" layer="91"/> +<junction x="-101.6" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDD@1"/> </segment> <segment> -<wire x1="-91.44" y1="101.6" x2="-91.44" y2="102.87" width="0.1524" layer="91"/> <pinref part="P+60" gate="VCC" pin="VCC"/> -<wire x1="-91.44" y1="102.87" x2="-91.44" y2="99.06" width="0.1524" layer="91"/> -<label x="-88.9" y="101.6" size="1.778" layer="95"/> +<wire x1="-91.44" y1="90.17" x2="-91.44" y2="86.36" width="0.1524" layer="91"/> +<label x="-88.9" y="88.9" size="1.778" layer="95"/> <pinref part="IC1" gate="G$1" pin="VDDQ@81"/> -<wire x1="-91.44" y1="99.06" x2="-91.44" y2="96.52" width="0.1524" layer="91"/> -<wire x1="-91.44" y1="99.06" x2="-88.9" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-88.9" y1="99.06" x2="-86.36" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-86.36" y1="99.06" x2="-83.82" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-83.82" y1="99.06" x2="-81.28" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-81.28" y1="99.06" x2="-78.74" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-78.74" y1="99.06" x2="-76.2" y2="99.06" width="0.1524" layer="91"/> -<wire x1="-76.2" y1="99.06" x2="-76.2" y2="96.52" width="0.1524" layer="91"/> -<junction x="-91.44" y="99.06"/> +<wire x1="-91.44" y1="86.36" x2="-91.44" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="86.36" x2="-88.9" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="86.36" x2="-86.36" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="86.36" x2="-83.82" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="86.36" x2="-81.28" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="86.36" x2="-78.74" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="86.36" x2="-76.2" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="86.36" x2="-76.2" y2="83.82" width="0.1524" layer="91"/> +<junction x="-91.44" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@75"/> -<wire x1="-78.74" y1="96.52" x2="-78.74" y2="99.06" width="0.1524" layer="91"/> -<junction x="-78.74" y="99.06"/> +<wire x1="-78.74" y1="83.82" x2="-78.74" y2="86.36" width="0.1524" layer="91"/> +<junction x="-78.74" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@55"/> -<wire x1="-81.28" y1="96.52" x2="-81.28" y2="99.06" width="0.1524" layer="91"/> -<junction x="-81.28" y="99.06"/> +<wire x1="-81.28" y1="83.82" x2="-81.28" y2="86.36" width="0.1524" layer="91"/> +<junction x="-81.28" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@49"/> -<wire x1="-83.82" y1="96.52" x2="-83.82" y2="99.06" width="0.1524" layer="91"/> -<junction x="-83.82" y="99.06"/> +<wire x1="-83.82" y1="83.82" x2="-83.82" y2="86.36" width="0.1524" layer="91"/> +<junction x="-83.82" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@41"/> -<wire x1="-86.36" y1="96.52" x2="-86.36" y2="99.06" width="0.1524" layer="91"/> -<junction x="-86.36" y="99.06"/> +<wire x1="-86.36" y1="83.82" x2="-86.36" y2="86.36" width="0.1524" layer="91"/> +<junction x="-86.36" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@35"/> -<wire x1="-88.9" y1="96.52" x2="-88.9" y2="99.06" width="0.1524" layer="91"/> -<junction x="-88.9" y="99.06"/> +<wire x1="-88.9" y1="83.82" x2="-88.9" y2="86.36" width="0.1524" layer="91"/> +<junction x="-88.9" y="86.36"/> <pinref part="IC1" gate="G$1" pin="VDDQ@3"/> </segment> <segment> <pinref part="C201" gate="G$1" pin="1"/> -<wire x1="-114.3" y1="-40.64" x2="-114.3" y2="-39.37" width="0.1524" layer="91"/> <pinref part="P+58" gate="VCC" pin="VCC"/> -<wire x1="-114.3" y1="-39.37" x2="-114.3" y2="-45.72" width="0.1524" layer="91"/> -<junction x="-114.3" y="-45.72"/> -<wire x1="-114.3" y1="-45.72" x2="-109.22" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="-114.3" y1="-52.07" x2="-114.3" y2="-58.42" width="0.1524" layer="91"/> +<junction x="-114.3" y="-58.42"/> +<wire x1="-114.3" y1="-58.42" x2="-109.22" y2="-58.42" width="0.1524" layer="91"/> <pinref part="C200" gate="G$1" pin="1"/> -<junction x="-109.22" y="-45.72"/> -<wire x1="-109.22" y1="-45.72" x2="-104.14" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-109.22" y="-58.42"/> +<wire x1="-109.22" y1="-58.42" x2="-104.14" y2="-58.42" width="0.1524" layer="91"/> <pinref part="C197" gate="G$1" pin="1"/> -<junction x="-104.14" y="-45.72"/> -<wire x1="-104.14" y1="-45.72" x2="-99.06" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-104.14" y="-58.42"/> +<wire x1="-104.14" y1="-58.42" x2="-99.06" y2="-58.42" width="0.1524" layer="91"/> <pinref part="C196" gate="G$1" pin="1"/> -<junction x="-99.06" y="-45.72"/> -<wire x1="-99.06" y1="-45.72" x2="-93.98" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-99.06" y="-58.42"/> +<wire x1="-99.06" y1="-58.42" x2="-93.98" y2="-58.42" width="0.1524" layer="91"/> <pinref part="C195" gate="G$1" pin="1"/> -<junction x="-93.98" y="-45.72"/> -<wire x1="-93.98" y1="-45.72" x2="-88.9" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-93.98" y="-58.42"/> +<wire x1="-93.98" y1="-58.42" x2="-88.9" y2="-58.42" width="0.1524" layer="91"/> <pinref part="C194" gate="G$1" pin="1"/> -<wire x1="-88.9" y1="-45.72" x2="-83.82" y2="-45.72" width="0.1524" layer="91"/> -<wire x1="-83.82" y1="-45.72" x2="-83.82" y2="-58.42" width="0.1524" layer="91"/> -<junction x="-88.9" y="-45.72"/> +<wire x1="-88.9" y1="-58.42" x2="-83.82" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-58.42" x2="-83.82" y2="-71.12" width="0.1524" layer="91"/> +<junction x="-88.9" y="-58.42"/> <pinref part="C199" gate="G$1" pin="1"/> <pinref part="C198" gate="G$1" pin="1"/> -<junction x="-104.14" y="-58.42"/> -<wire x1="-88.9" y1="-58.42" x2="-93.98" y2="-58.42" width="0.1524" layer="91"/> -<wire x1="-93.98" y1="-58.42" x2="-99.06" y2="-58.42" width="0.1524" layer="91"/> -<wire x1="-99.06" y1="-58.42" x2="-104.14" y2="-58.42" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="-58.42" x2="-109.22" y2="-58.42" width="0.1524" layer="91"/> +<junction x="-104.14" y="-71.12"/> +<wire x1="-88.9" y1="-71.12" x2="-93.98" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-71.12" x2="-99.06" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-71.12" x2="-104.14" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-71.12" x2="-109.22" y2="-71.12" width="0.1524" layer="91"/> <pinref part="C208" gate="G$1" pin="1"/> -<junction x="-99.06" y="-58.42"/> +<junction x="-99.06" y="-71.12"/> <pinref part="C207" gate="G$1" pin="1"/> -<junction x="-93.98" y="-58.42"/> +<junction x="-93.98" y="-71.12"/> <pinref part="C206" gate="G$1" pin="1"/> -<wire x1="-83.82" y1="-58.42" x2="-88.9" y2="-58.42" width="0.1524" layer="91"/> -<junction x="-88.9" y="-58.42"/> -<label x="-129.54" y="-40.64" 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x2="81.28" y2="93.98" width="0.1524" layer="91"/> -<junction x="73.66" y="96.52"/> +<wire x1="73.66" y1="83.82" x2="73.66" y2="81.28" width="0.1524" layer="91"/> +<wire x1="73.66" y1="83.82" x2="76.2" y2="83.82" width="0.1524" layer="91"/> +<wire x1="76.2" y1="83.82" x2="78.74" y2="83.82" width="0.1524" layer="91"/> +<wire x1="78.74" y1="83.82" x2="81.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="81.28" y1="83.82" x2="81.28" y2="81.28" width="0.1524" layer="91"/> +<junction x="73.66" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDD@29"/> -<wire x1="78.74" y1="93.98" x2="78.74" y2="96.52" width="0.1524" layer="91"/> -<junction x="78.74" y="96.52"/> +<wire x1="78.74" y1="81.28" x2="78.74" y2="83.82" width="0.1524" layer="91"/> +<junction x="78.74" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDD@15"/> -<wire x1="76.2" y1="93.98" x2="76.2" y2="96.52" width="0.1524" layer="91"/> -<junction x="76.2" y="96.52"/> +<wire x1="76.2" y1="81.28" x2="76.2" y2="83.82" width="0.1524" layer="91"/> +<junction x="76.2" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDD@1"/> </segment> <segment> -<wire x1="86.36" y1="99.06" x2="86.36" y2="100.33" width="0.1524" layer="91"/> <pinref part="P+62" gate="VCC" pin="VCC"/> -<wire x1="86.36" y1="100.33" x2="86.36" y2="96.52" width="0.1524" layer="91"/> -<label x="88.9" y="99.06" size="1.778" layer="95"/> +<wire x1="86.36" y1="87.63" x2="86.36" y2="83.82" width="0.1524" layer="91"/> +<label x="88.9" y="86.36" size="1.778" layer="95"/> <pinref part="IC2" gate="G$1" pin="VDDQ@81"/> -<wire x1="86.36" y1="96.52" x2="86.36" y2="93.98" width="0.1524" layer="91"/> -<wire x1="86.36" y1="96.52" x2="88.9" y2="96.52" width="0.1524" layer="91"/> -<wire x1="88.9" y1="96.52" x2="91.44" y2="96.52" width="0.1524" layer="91"/> -<wire x1="91.44" y1="96.52" x2="93.98" y2="96.52" width="0.1524" layer="91"/> -<wire x1="93.98" y1="96.52" x2="96.52" y2="96.52" width="0.1524" layer="91"/> -<wire x1="96.52" y1="96.52" x2="99.06" y2="96.52" width="0.1524" layer="91"/> -<wire x1="99.06" y1="96.52" x2="101.6" y2="96.52" width="0.1524" layer="91"/> -<wire x1="101.6" y1="96.52" x2="101.6" y2="93.98" width="0.1524" layer="91"/> -<junction x="86.36" y="96.52"/> +<wire x1="86.36" y1="83.82" x2="86.36" y2="81.28" width="0.1524" layer="91"/> +<wire x1="86.36" y1="83.82" x2="88.9" y2="83.82" width="0.1524" layer="91"/> +<wire x1="88.9" y1="83.82" x2="91.44" y2="83.82" width="0.1524" layer="91"/> +<wire x1="91.44" y1="83.82" x2="93.98" y2="83.82" width="0.1524" layer="91"/> +<wire x1="93.98" y1="83.82" x2="96.52" y2="83.82" width="0.1524" layer="91"/> +<wire x1="96.52" y1="83.82" x2="99.06" y2="83.82" width="0.1524" layer="91"/> +<wire x1="99.06" y1="83.82" x2="101.6" y2="83.82" width="0.1524" layer="91"/> +<wire x1="101.6" y1="83.82" x2="101.6" y2="81.28" width="0.1524" layer="91"/> +<junction x="86.36" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@75"/> -<wire x1="99.06" y1="93.98" x2="99.06" y2="96.52" width="0.1524" layer="91"/> -<junction x="99.06" y="96.52"/> +<wire x1="99.06" y1="81.28" x2="99.06" y2="83.82" width="0.1524" layer="91"/> +<junction x="99.06" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@55"/> -<wire x1="96.52" y1="93.98" x2="96.52" y2="96.52" width="0.1524" layer="91"/> -<junction x="96.52" y="96.52"/> +<wire x1="96.52" y1="81.28" x2="96.52" y2="83.82" width="0.1524" layer="91"/> +<junction x="96.52" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@49"/> -<wire x1="93.98" y1="93.98" x2="93.98" y2="96.52" width="0.1524" layer="91"/> -<junction x="93.98" y="96.52"/> +<wire x1="93.98" y1="81.28" x2="93.98" y2="83.82" width="0.1524" layer="91"/> +<junction x="93.98" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@41"/> -<wire x1="91.44" y1="93.98" x2="91.44" y2="96.52" width="0.1524" layer="91"/> -<junction x="91.44" y="96.52"/> +<wire x1="91.44" y1="81.28" x2="91.44" y2="83.82" width="0.1524" layer="91"/> +<junction x="91.44" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@35"/> -<wire x1="88.9" y1="93.98" x2="88.9" y2="96.52" width="0.1524" layer="91"/> -<junction x="88.9" y="96.52"/> +<wire x1="88.9" y1="81.28" x2="88.9" y2="83.82" width="0.1524" layer="91"/> +<junction x="88.9" y="83.82"/> <pinref part="IC2" gate="G$1" pin="VDDQ@3"/> </segment> <segment> <pinref part="C205" gate="G$1" pin="1"/> -<wire x1="63.5" y1="-43.18" x2="63.5" y2="-41.91" width="0.1524" layer="91"/> <pinref part="P+63" gate="VCC" pin="VCC"/> -<wire x1="63.5" y1="-41.91" x2="63.5" y2="-48.26" width="0.1524" layer="91"/> -<junction x="63.5" y="-48.26"/> -<wire x1="63.5" y1="-48.26" x2="68.58" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="63.5" y1="-54.61" x2="63.5" y2="-60.96" width="0.1524" layer="91"/> +<junction x="63.5" y="-60.96"/> +<wire x1="63.5" y1="-60.96" x2="68.58" y2="-60.96" width="0.1524" layer="91"/> <pinref part="C204" gate="G$1" pin="1"/> -<junction x="68.58" y="-48.26"/> -<wire x1="68.58" y1="-48.26" x2="73.66" y2="-48.26" width="0.1524" layer="91"/> +<junction x="68.58" y="-60.96"/> +<wire x1="68.58" y1="-60.96" x2="73.66" y2="-60.96" width="0.1524" layer="91"/> <pinref part="C193" gate="G$1" pin="1"/> -<junction x="73.66" y="-48.26"/> -<wire x1="73.66" y1="-48.26" x2="78.74" y2="-48.26" width="0.1524" layer="91"/> +<junction x="73.66" y="-60.96"/> +<wire x1="73.66" y1="-60.96" x2="78.74" y2="-60.96" width="0.1524" layer="91"/> <pinref part="C192" gate="G$1" pin="1"/> -<junction x="78.74" y="-48.26"/> -<wire x1="78.74" y1="-48.26" x2="83.82" y2="-48.26" width="0.1524" layer="91"/> +<junction x="78.74" y="-60.96"/> +<wire x1="78.74" y1="-60.96" x2="83.82" y2="-60.96" width="0.1524" layer="91"/> <pinref part="C191" gate="G$1" pin="1"/> -<junction x="83.82" y="-48.26"/> -<wire x1="83.82" y1="-48.26" x2="88.9" y2="-48.26" width="0.1524" layer="91"/> +<junction x="83.82" y="-60.96"/> +<wire x1="83.82" y1="-60.96" x2="88.9" y2="-60.96" width="0.1524" layer="91"/> <pinref part="C190" gate="G$1" pin="1"/> -<wire x1="88.9" y1="-48.26" x2="93.98" y2="-48.26" width="0.1524" layer="91"/> -<wire x1="93.98" y1="-48.26" x2="93.98" y2="-60.96" width="0.1524" layer="91"/> -<junction x="88.9" y="-48.26"/> +<wire x1="88.9" y1="-60.96" x2="93.98" y2="-60.96" width="0.1524" layer="91"/> +<wire x1="93.98" y1="-60.96" x2="93.98" y2="-73.66" width="0.1524" layer="91"/> +<junction x="88.9" y="-60.96"/> <pinref part="C203" gate="G$1" pin="1"/> <pinref part="C202" gate="G$1" pin="1"/> -<junction x="73.66" y="-60.96"/> -<wire x1="88.9" y1="-60.96" x2="83.82" y2="-60.96" width="0.1524" layer="91"/> -<wire x1="83.82" y1="-60.96" x2="78.74" y2="-60.96" width="0.1524" layer="91"/> -<wire x1="78.74" y1="-60.96" x2="73.66" y2="-60.96" width="0.1524" layer="91"/> -<wire x1="73.66" y1="-60.96" x2="68.58" y2="-60.96" width="0.1524" layer="91"/> +<junction x="73.66" y="-73.66"/> +<wire x1="88.9" y1="-73.66" x2="83.82" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-73.66" x2="78.74" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-73.66" x2="73.66" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="73.66" y1="-73.66" x2="68.58" y2="-73.66" width="0.1524" layer="91"/> <pinref part="C211" gate="G$1" pin="1"/> -<junction x="78.74" y="-60.96"/> +<junction x="78.74" y="-73.66"/> <pinref part="C210" gate="G$1" pin="1"/> -<junction x="83.82" y="-60.96"/> +<junction x="83.82" y="-73.66"/> <pinref part="C209" gate="G$1" pin="1"/> -<wire x1="93.98" y1="-60.96" x2="88.9" y2="-60.96" width="0.1524" layer="91"/> -<junction x="88.9" y="-60.96"/> -<label x="48.26" y="-43.18" size="1.778" layer="95"/> +<wire x1="93.98" y1="-73.66" x2="88.9" y2="-73.66" width="0.1524" layer="91"/> +<junction x="88.9" y="-73.66"/> +<label x="48.26" y="-55.88" size="1.778" layer="95"/> </segment> </net> <net name="FMC_A0" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A0"/> -<wire x1="-134.62" y1="88.9" x2="-119.38" y2="88.9" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="76.2" x2="-119.38" y2="76.2" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A0"/> -<wire x1="43.18" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/> +<wire x1="43.18" y1="73.66" x2="58.42" y2="73.66" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A1" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A1"/> -<wire x1="-134.62" y1="86.36" x2="-119.38" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="73.66" x2="-119.38" y2="73.66" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A1"/> -<wire x1="43.18" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/> +<wire x1="43.18" y1="71.12" x2="58.42" y2="71.12" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A2" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A2"/> -<wire x1="-134.62" y1="83.82" x2="-119.38" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="71.12" x2="-119.38" y2="71.12" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A2"/> -<wire x1="43.18" y1="81.28" x2="58.42" y2="81.28" width="0.1524" layer="91"/> +<wire x1="43.18" y1="68.58" x2="58.42" y2="68.58" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A3" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A3"/> -<wire x1="-134.62" y1="81.28" x2="-119.38" y2="81.28" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="68.58" x2="-119.38" y2="68.58" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A3"/> -<wire x1="43.18" y1="78.74" x2="58.42" y2="78.74" width="0.1524" layer="91"/> +<wire x1="43.18" y1="66.04" x2="58.42" y2="66.04" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A4" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A4"/> -<wire x1="-134.62" y1="78.74" x2="-119.38" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="66.04" x2="-119.38" y2="66.04" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A4"/> -<wire x1="43.18" y1="76.2" x2="58.42" y2="76.2" width="0.1524" layer="91"/> +<wire x1="43.18" y1="63.5" x2="58.42" y2="63.5" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A5" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A5"/> -<wire x1="-134.62" y1="76.2" x2="-119.38" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="63.5" x2="-119.38" y2="63.5" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A5"/> -<wire x1="43.18" y1="73.66" x2="58.42" y2="73.66" width="0.1524" layer="91"/> +<wire x1="43.18" y1="60.96" x2="58.42" y2="60.96" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A6" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A6"/> -<wire x1="-134.62" y1="73.66" x2="-119.38" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="60.96" x2="-119.38" y2="60.96" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A6"/> -<wire x1="43.18" y1="71.12" x2="58.42" y2="71.12" width="0.1524" layer="91"/> +<wire x1="43.18" y1="58.42" x2="58.42" y2="58.42" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A7" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A7"/> -<wire x1="-134.62" y1="71.12" x2="-119.38" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="58.42" x2="-119.38" y2="58.42" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A7"/> -<wire x1="43.18" y1="68.58" x2="58.42" y2="68.58" width="0.1524" layer="91"/> +<wire x1="43.18" y1="55.88" x2="58.42" y2="55.88" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A8" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A8"/> -<wire x1="-134.62" y1="68.58" x2="-119.38" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="55.88" x2="-119.38" y2="55.88" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A8"/> -<wire x1="43.18" y1="66.04" x2="58.42" y2="66.04" width="0.1524" layer="91"/> +<wire x1="43.18" y1="53.34" x2="58.42" y2="53.34" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A9" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A9"/> -<wire x1="-134.62" y1="66.04" x2="-119.38" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="53.34" x2="-119.38" y2="53.34" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A9"/> -<wire x1="43.18" y1="63.5" x2="58.42" y2="63.5" width="0.1524" layer="91"/> +<wire x1="43.18" y1="50.8" x2="58.42" y2="50.8" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A10" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A10"/> -<wire x1="-134.62" y1="63.5" x2="-119.38" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="50.8" x2="-119.38" y2="50.8" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A10"/> -<wire x1="43.18" y1="60.96" x2="58.42" y2="60.96" width="0.1524" layer="91"/> +<wire x1="43.18" y1="48.26" x2="58.42" y2="48.26" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A11" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A11"/> -<wire x1="-134.62" y1="60.96" x2="-119.38" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="48.26" x2="-119.38" y2="48.26" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A11"/> -<wire x1="43.18" y1="58.42" x2="58.42" y2="58.42" width="0.1524" layer="91"/> +<wire x1="43.18" y1="45.72" x2="58.42" y2="45.72" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_A12" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="A12"/> -<wire x1="-134.62" y1="58.42" x2="-119.38" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="45.72" x2="-119.38" y2="45.72" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="A12"/> -<wire x1="43.18" y1="55.88" x2="58.42" y2="55.88" width="0.1524" layer="91"/> +<wire x1="43.18" y1="43.18" x2="58.42" y2="43.18" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D0" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ0"/> -<wire x1="-43.18" y1="88.9" x2="-58.42" y2="88.9" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="76.2" x2="-58.42" y2="76.2" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ0"/> -<wire x1="134.62" y1="86.36" x2="119.38" y2="86.36" width="0.1524" layer="91"/> +<wire x1="134.62" y1="73.66" x2="119.38" y2="73.66" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D1" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ1"/> -<wire x1="-43.18" y1="86.36" x2="-58.42" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="73.66" x2="-58.42" y2="73.66" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ1"/> -<wire x1="134.62" y1="83.82" x2="119.38" y2="83.82" width="0.1524" layer="91"/> +<wire x1="134.62" y1="71.12" x2="119.38" y2="71.12" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D2" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ2"/> -<wire x1="-43.18" y1="83.82" x2="-58.42" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="71.12" x2="-58.42" y2="71.12" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ2"/> -<wire x1="134.62" y1="81.28" x2="119.38" y2="81.28" width="0.1524" layer="91"/> +<wire x1="134.62" y1="68.58" x2="119.38" y2="68.58" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D3" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ3"/> -<wire x1="-43.18" y1="81.28" x2="-58.42" y2="81.28" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="68.58" x2="-58.42" y2="68.58" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ3"/> -<wire x1="134.62" y1="78.74" x2="119.38" y2="78.74" width="0.1524" layer="91"/> +<wire x1="134.62" y1="66.04" x2="119.38" y2="66.04" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D4" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ4"/> -<wire x1="-43.18" y1="78.74" x2="-58.42" y2="78.74" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="66.04" x2="-58.42" y2="66.04" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ4"/> -<wire x1="134.62" y1="76.2" x2="119.38" y2="76.2" width="0.1524" layer="91"/> +<wire x1="134.62" y1="63.5" x2="119.38" y2="63.5" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D5" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ5"/> -<wire x1="-43.18" y1="76.2" x2="-58.42" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="63.5" x2="-58.42" y2="63.5" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ5"/> -<wire x1="134.62" y1="73.66" x2="119.38" y2="73.66" width="0.1524" layer="91"/> +<wire x1="134.62" y1="60.96" x2="119.38" y2="60.96" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D6" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ6"/> -<wire x1="-43.18" y1="73.66" x2="-58.42" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="60.96" x2="-58.42" y2="60.96" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ6"/> -<wire x1="134.62" y1="71.12" x2="119.38" y2="71.12" width="0.1524" layer="91"/> +<wire x1="134.62" y1="58.42" x2="119.38" y2="58.42" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D7" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ7"/> -<wire x1="-43.18" y1="71.12" x2="-58.42" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="58.42" x2="-58.42" y2="58.42" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ7"/> -<wire x1="134.62" y1="68.58" x2="119.38" y2="68.58" width="0.1524" layer="91"/> +<wire x1="134.62" y1="55.88" x2="119.38" y2="55.88" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D8" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ8"/> -<wire x1="-43.18" y1="68.58" x2="-58.42" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="55.88" x2="-58.42" y2="55.88" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ8"/> -<wire x1="134.62" y1="66.04" x2="119.38" y2="66.04" width="0.1524" layer="91"/> +<wire x1="134.62" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D10" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ9"/> -<wire x1="-43.18" y1="66.04" x2="-58.42" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="53.34" x2="-58.42" y2="53.34" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC1" gate="G$1" pin="DQ10"/> -<wire x1="-43.18" y1="63.5" x2="-58.42" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="50.8" x2="-58.42" y2="50.8" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ9"/> -<wire x1="134.62" y1="63.5" x2="119.38" y2="63.5" width="0.1524" layer="91"/> +<wire x1="134.62" y1="50.8" x2="119.38" y2="50.8" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ10"/> -<wire x1="134.62" y1="60.96" x2="119.38" y2="60.96" width="0.1524" layer="91"/> +<wire x1="134.62" y1="48.26" x2="119.38" y2="48.26" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D11" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ11"/> -<wire x1="-43.18" y1="60.96" x2="-58.42" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="48.26" x2="-58.42" y2="48.26" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ11"/> -<wire x1="134.62" y1="58.42" x2="119.38" y2="58.42" width="0.1524" layer="91"/> +<wire x1="134.62" y1="45.72" x2="119.38" y2="45.72" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D12" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ12"/> -<wire x1="-43.18" y1="58.42" x2="-58.42" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="45.72" x2="-58.42" y2="45.72" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ12"/> -<wire x1="134.62" y1="55.88" x2="119.38" y2="55.88" width="0.1524" layer="91"/> +<wire x1="134.62" y1="43.18" x2="119.38" y2="43.18" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D13" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ13"/> -<wire x1="-43.18" y1="55.88" x2="-58.42" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="43.18" x2="-58.42" y2="43.18" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ13"/> -<wire x1="134.62" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/> +<wire x1="134.62" y1="40.64" x2="119.38" y2="40.64" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D14" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ14"/> -<wire x1="-43.18" y1="53.34" x2="-58.42" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="40.64" x2="-58.42" y2="40.64" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ14"/> -<wire x1="134.62" y1="50.8" x2="119.38" y2="50.8" width="0.1524" layer="91"/> +<wire x1="134.62" y1="38.1" x2="119.38" y2="38.1" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D15" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ15"/> -<wire x1="-43.18" y1="50.8" x2="-58.42" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="38.1" x2="-58.42" y2="38.1" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ15"/> -<wire x1="134.62" y1="48.26" x2="119.38" y2="48.26" width="0.1524" layer="91"/> +<wire x1="134.62" y1="35.56" x2="119.38" y2="35.56" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D16" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ16"/> -<wire x1="-43.18" y1="48.26" x2="-58.42" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="35.56" x2="-58.42" y2="35.56" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ16"/> -<wire x1="134.62" y1="45.72" x2="119.38" y2="45.72" width="0.1524" layer="91"/> +<wire x1="134.62" y1="33.02" x2="119.38" y2="33.02" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D17" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ17"/> -<wire x1="-43.18" y1="45.72" x2="-58.42" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="33.02" x2="-58.42" y2="33.02" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ17"/> -<wire x1="134.62" y1="43.18" x2="119.38" y2="43.18" width="0.1524" layer="91"/> +<wire x1="134.62" y1="30.48" x2="119.38" y2="30.48" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D18" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ18"/> -<wire x1="-43.18" y1="43.18" x2="-58.42" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="30.48" x2="-58.42" y2="30.48" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ18"/> -<wire x1="134.62" y1="40.64" x2="119.38" y2="40.64" width="0.1524" layer="91"/> +<wire x1="134.62" y1="27.94" x2="119.38" y2="27.94" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D19" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ19"/> -<wire x1="-43.18" y1="40.64" x2="-58.42" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="27.94" x2="-58.42" y2="27.94" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ19"/> -<wire x1="134.62" y1="38.1" x2="119.38" y2="38.1" width="0.1524" layer="91"/> +<wire x1="134.62" y1="25.4" x2="119.38" y2="25.4" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D20" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ20"/> -<wire x1="-43.18" y1="38.1" x2="-58.42" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="25.4" x2="-58.42" y2="25.4" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ20"/> -<wire x1="134.62" y1="35.56" x2="119.38" y2="35.56" width="0.1524" layer="91"/> +<wire x1="134.62" y1="22.86" x2="119.38" y2="22.86" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D21" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ21"/> -<wire x1="-43.18" y1="35.56" x2="-58.42" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="22.86" x2="-58.42" y2="22.86" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ21"/> -<wire x1="134.62" y1="33.02" x2="119.38" y2="33.02" width="0.1524" layer="91"/> +<wire x1="134.62" y1="20.32" x2="119.38" y2="20.32" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D22" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ22"/> -<wire x1="-43.18" y1="33.02" x2="-58.42" y2="33.02" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="20.32" x2="-58.42" y2="20.32" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ22"/> -<wire x1="134.62" y1="30.48" x2="119.38" y2="30.48" width="0.1524" layer="91"/> +<wire x1="134.62" y1="17.78" x2="119.38" y2="17.78" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D23" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ23"/> -<wire x1="-43.18" y1="30.48" x2="-58.42" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="17.78" x2="-58.42" y2="17.78" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ23"/> -<wire x1="134.62" y1="27.94" x2="119.38" y2="27.94" width="0.1524" layer="91"/> +<wire x1="134.62" y1="15.24" x2="119.38" y2="15.24" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D24" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ24"/> -<wire x1="-43.18" y1="27.94" x2="-58.42" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="15.24" x2="-58.42" y2="15.24" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ24"/> -<wire x1="134.62" y1="25.4" x2="119.38" y2="25.4" width="0.1524" layer="91"/> +<wire x1="134.62" y1="12.7" x2="119.38" y2="12.7" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D25" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ25"/> -<wire x1="-43.18" y1="25.4" x2="-58.42" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="12.7" x2="-58.42" y2="12.7" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ25"/> -<wire x1="134.62" y1="22.86" x2="119.38" y2="22.86" width="0.1524" layer="91"/> +<wire x1="134.62" y1="10.16" x2="119.38" y2="10.16" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D26" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ26"/> -<wire x1="-43.18" y1="22.86" x2="-58.42" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="10.16" x2="-58.42" y2="10.16" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ26"/> -<wire x1="134.62" y1="20.32" x2="119.38" y2="20.32" width="0.1524" layer="91"/> +<wire x1="134.62" y1="7.62" x2="119.38" y2="7.62" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D27" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ27"/> -<wire x1="-43.18" y1="20.32" x2="-58.42" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="7.62" x2="-58.42" y2="7.62" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ27"/> -<wire x1="134.62" y1="17.78" x2="119.38" y2="17.78" width="0.1524" layer="91"/> +<wire x1="134.62" y1="5.08" x2="119.38" y2="5.08" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D28" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ28"/> -<wire x1="-43.18" y1="17.78" x2="-58.42" y2="17.78" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="5.08" x2="-58.42" y2="5.08" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ28"/> -<wire x1="134.62" y1="15.24" x2="119.38" y2="15.24" width="0.1524" layer="91"/> +<wire x1="134.62" y1="2.54" x2="119.38" y2="2.54" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D29" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ29"/> -<wire x1="-43.18" y1="15.24" x2="-58.42" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="2.54" x2="-58.42" y2="2.54" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ29"/> -<wire x1="134.62" y1="12.7" x2="119.38" y2="12.7" width="0.1524" layer="91"/> +<wire x1="134.62" y1="0" x2="119.38" y2="0" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D30" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ30"/> -<wire x1="-43.18" y1="12.7" x2="-58.42" y2="12.7" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="0" x2="-58.42" y2="0" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ30"/> -<wire x1="134.62" y1="10.16" x2="119.38" y2="10.16" width="0.1524" layer="91"/> +<wire x1="134.62" y1="-2.54" x2="119.38" y2="-2.54" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_D31" class="2"> <segment> <pinref part="IC1" gate="G$1" pin="DQ31"/> -<wire x1="-43.18" y1="10.16" x2="-58.42" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="-2.54" x2="-58.42" y2="-2.54" width="0.1524" layer="91"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQ31"/> -<wire x1="134.62" y1="7.62" x2="119.38" y2="7.62" width="0.1524" layer="91"/> +<wire x1="134.62" y1="-5.08" x2="119.38" y2="-5.08" width="0.1524" layer="91"/> </segment> </net> <net name="FMC_SDCKE0" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="CKE"/> -<wire x1="-119.38" y1="15.24" x2="-134.62" y2="15.24" width="0.1524" layer="91"/> -<label x="-134.62" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="2.54" x2="-134.62" y2="2.54" width="0.1524" layer="91"/> +<label x="-134.62" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDNE0" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="!CS"/> -<wire x1="-119.38" y1="2.54" x2="-134.62" y2="2.54" width="0.1524" layer="91"/> -<label x="-134.62" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="-10.16" x2="-134.62" y2="-10.16" width="0.1524" layer="91"/> +<label x="-134.62" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDNWE" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="!WE"/> -<wire x1="-119.38" y1="-10.16" x2="-134.62" y2="-10.16" width="0.1524" layer="91"/> -<label x="-134.62" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="-22.86" x2="-134.62" y2="-22.86" width="0.1524" layer="91"/> +<label x="-134.62" y="-22.86" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="!WE"/> -<wire x1="58.42" y1="-12.7" x2="43.18" y2="-12.7" width="0.1524" layer="91"/> -<label x="43.18" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="-25.4" x2="43.18" y2="-25.4" width="0.1524" layer="91"/> +<label x="43.18" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDNCAS" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="!CAS"/> -<wire x1="-119.38" y1="43.18" x2="-134.62" y2="43.18" width="0.1524" layer="91"/> -<label x="-134.62" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="30.48" x2="-134.62" y2="30.48" width="0.1524" layer="91"/> +<label x="-134.62" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="!CAS"/> -<wire x1="58.42" y1="40.64" x2="43.18" y2="40.64" width="0.1524" layer="91"/> -<label x="43.18" y="40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="27.94" x2="43.18" y2="27.94" width="0.1524" layer="91"/> +<label x="43.18" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDNRAS" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="!RAS"/> -<wire x1="-119.38" y1="40.64" x2="-134.62" y2="40.64" width="0.1524" layer="91"/> -<label x="-134.62" y="40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="27.94" x2="-134.62" y2="27.94" width="0.1524" layer="91"/> +<label x="-134.62" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="!RAS"/> -<wire x1="58.42" y1="38.1" x2="43.18" y2="38.1" width="0.1524" layer="91"/> -<label x="43.18" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="25.4" x2="43.18" y2="25.4" width="0.1524" layer="91"/> +<label x="43.18" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_A14" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="BA0"/> -<wire x1="-134.62" y1="50.8" x2="-119.38" y2="50.8" width="0.1524" layer="91"/> -<label x="-132.08" y="50.8" size="1.27" layer="95"/> +<wire x1="-134.62" y1="38.1" x2="-119.38" y2="38.1" width="0.1524" layer="91"/> +<label x="-132.08" y="38.1" size="1.27" layer="95"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="BA0"/> -<wire x1="43.18" y1="48.26" x2="58.42" y2="48.26" width="0.1524" layer="91"/> -<label x="45.72" y="48.26" size="1.27" layer="95"/> +<wire x1="43.18" y1="35.56" x2="58.42" y2="35.56" width="0.1524" layer="91"/> +<label x="45.72" y="35.56" size="1.27" layer="95"/> </segment> </net> <net name="FMC_A15" class="3"> <segment> <pinref part="IC1" gate="G$1" pin="BA1"/> -<wire x1="-134.62" y1="48.26" x2="-119.38" y2="48.26" width="0.1524" layer="91"/> -<label x="-132.08" y="48.26" size="1.27" layer="95"/> +<wire x1="-134.62" y1="35.56" x2="-119.38" y2="35.56" width="0.1524" layer="91"/> +<label x="-132.08" y="35.56" size="1.27" layer="95"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="BA1"/> -<wire x1="43.18" y1="45.72" x2="58.42" y2="45.72" width="0.1524" layer="91"/> -<label x="45.72" y="45.72" size="1.27" layer="95"/> +<wire x1="43.18" y1="33.02" x2="58.42" y2="33.02" width="0.1524" layer="91"/> +<label x="45.72" y="33.02" size="1.27" layer="95"/> </segment> </net> <net name="FMC_NBL0" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="DQM0"/> -<wire x1="-58.42" y1="5.08" x2="-43.18" y2="5.08" width="0.1524" layer="91"/> -<label x="-43.18" y="5.08" size="1.27" layer="95" xref="yes"/> +<wire x1="-58.42" y1="-7.62" x2="-43.18" y2="-7.62" width="0.1524" layer="91"/> +<label x="-43.18" y="-7.62" size="1.27" layer="95" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQM0"/> -<wire x1="119.38" y1="2.54" x2="134.62" y2="2.54" width="0.1524" layer="91"/> -<label x="134.62" y="2.54" size="1.27" layer="95" xref="yes"/> +<wire x1="119.38" y1="-10.16" x2="134.62" y2="-10.16" width="0.1524" layer="91"/> +<label x="134.62" y="-10.16" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="FMC_NBL1" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="DQM1"/> -<wire x1="-58.42" y1="2.54" x2="-43.18" y2="2.54" width="0.1524" layer="91"/> -<label x="-43.18" y="2.54" size="1.27" layer="95" xref="yes"/> +<wire x1="-58.42" y1="-10.16" x2="-43.18" y2="-10.16" width="0.1524" layer="91"/> +<label x="-43.18" y="-10.16" size="1.27" layer="95" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQM1"/> -<wire x1="119.38" y1="0" x2="134.62" y2="0" width="0.1524" layer="91"/> -<label x="134.62" y="0" size="1.27" layer="95" xref="yes"/> +<wire x1="119.38" y1="-12.7" x2="134.62" y2="-12.7" width="0.1524" layer="91"/> +<label x="134.62" y="-12.7" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="FMC_NBL2" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="DQM2"/> -<wire x1="-58.42" y1="0" x2="-43.18" y2="0" width="0.1524" layer="91"/> -<label x="-43.18" y="0" size="1.27" layer="95" xref="yes"/> +<wire x1="-58.42" y1="-12.7" x2="-43.18" y2="-12.7" width="0.1524" layer="91"/> +<label x="-43.18" y="-12.7" size="1.27" layer="95" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQM2"/> -<wire x1="119.38" y1="-2.54" x2="134.62" y2="-2.54" width="0.1524" layer="91"/> -<label x="134.62" y="-2.54" size="1.27" layer="95" xref="yes"/> +<wire x1="119.38" y1="-15.24" x2="134.62" y2="-15.24" width="0.1524" layer="91"/> +<label x="134.62" y="-15.24" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="FMC_NBL3" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="DQM3"/> -<wire x1="-58.42" y1="-2.54" x2="-43.18" y2="-2.54" width="0.1524" layer="91"/> -<label x="-43.18" y="-2.54" size="1.27" layer="95" xref="yes"/> +<wire x1="-58.42" y1="-15.24" x2="-43.18" y2="-15.24" width="0.1524" layer="91"/> +<label x="-43.18" y="-15.24" size="1.27" layer="95" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="DQM3"/> -<wire x1="119.38" y1="-5.08" x2="134.62" y2="-5.08" width="0.1524" layer="91"/> -<label x="134.62" y="-5.08" size="1.27" layer="95" xref="yes"/> +<wire x1="119.38" y1="-17.78" x2="134.62" y2="-17.78" width="0.1524" layer="91"/> +<label x="134.62" y="-17.78" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="FMC_SDCLK" class="0"> <segment> <pinref part="IC1" gate="G$1" pin="CLK"/> -<wire x1="-119.38" y1="27.94" x2="-134.62" y2="27.94" width="0.1524" layer="91"/> -<label x="-134.62" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="-119.38" y1="15.24" x2="-134.62" y2="15.24" width="0.1524" layer="91"/> +<label x="-134.62" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> <segment> <pinref part="IC2" gate="G$1" pin="CLK"/> -<wire x1="58.42" y1="25.4" x2="43.18" y2="25.4" width="0.1524" layer="91"/> -<label x="43.18" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="12.7" x2="43.18" y2="12.7" width="0.1524" layer="91"/> +<label x="43.18" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDCKE1" class="0"> <segment> <pinref part="IC2" gate="G$1" pin="CKE"/> -<wire x1="58.42" y1="12.7" x2="43.18" y2="12.7" width="0.1524" layer="91"/> -<label x="43.18" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="0" x2="43.18" y2="0" width="0.1524" layer="91"/> +<label x="43.18" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FMC_SDNE1" class="0"> <segment> <pinref part="IC2" gate="G$1" pin="!CS"/> -<wire x1="58.42" y1="0" x2="43.18" y2="0" width="0.1524" layer="91"/> -<label x="43.18" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="58.42" y1="-12.7" x2="43.18" y2="-12.7" width="0.1524" layer="91"/> +<label x="43.18" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> </nets> @@ -40213,9 +40520,9 @@ available GPIO on the ARM</text> <description>Keystore memory</description> <plain> <text x="22.86" y="10.16" size="1.778" layer="91">*) HOLD feature not used</text> -<text x="-40.64" y="45.72" size="2.54" layer="91">Keystore memory -This memory holds cryptographic keys -wrapped with master key in MKM.</text> +<text x="-40.64" y="45.72" size="2.54" layer="91">This memory holds cryptographic keys +wrapped with the master key.</text> +<text x="-40.64" y="60.96" size="3.81" layer="91">Keystore memory, 128 Mbit</text> </plain> <instances> <instance part="FRAME20" gate="G$1" x="-193.04" y="-129.54"/> @@ -40548,6 +40855,7 @@ This requirement also applies to using our own USB VID/PID. </text> <text x="-48.26" y="0" size="1.778" layer="91">CL 10pF</text> <text x="81.28" y="73.66" size="1.9304" layer="91">XXX EEPROM for USB settings or not?</text> +<text x="-45.72" y="93.98" size="3.81" layer="91">Application access USB UART</text> </plain> <instances> <instance part="U$3" gate="G$1" x="10.16" y="20.32"/> @@ -40663,7 +40971,6 @@ This requirement also applies to using our own USB VID/PID. </instance> <instance part="FRAME2" gate="G$1" x="-195.58" y="-132.08"/> <instance part="FT_VCC3V3_3" gate="VCC" x="45.72" y="-45.72" smashed="yes"/> -<instance part="FT_VCC3V3_4" gate="VCC" x="45.72" y="-45.72" smashed="yes"/> <instance part="FT_VCC3V3_5" gate="VCC" x="-86.36" y="-45.72" smashed="yes"/> <instance part="FT_VCC3V3_6" gate="VCC" x="-53.34" y="-45.72" smashed="yes"/> <instance part="FT_VCC3V3_7" gate="VCC" x="-27.94" y="-45.72" smashed="yes"/> @@ -40938,16 +41245,6 @@ This requirement also applies to using our own USB VID/PID. <label x="73.66" y="40.64" size="1.778" layer="95"/> </segment> <segment> -<pinref part="C47" gate="G$1" pin="1"/> -<wire x1="45.72" y1="-63.5" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> -<pinref part="C48" gate="G$1" pin="1"/> -<wire x1="45.72" y1="-58.42" x2="45.72" y2="-48.26" width="0.1524" layer="91"/> -<wire x1="53.34" y1="-63.5" x2="53.34" y2="-58.42" width="0.1524" layer="91"/> -<wire x1="53.34" y1="-58.42" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> -<junction x="45.72" y="-58.42"/> -<label x="38.1" y="-43.18" size="1.778" layer="95"/> -</segment> -<segment> <pinref part="FT_VCC3V3" gate="VCC" pin="VCC"/> <wire x1="12.7" y1="73.66" x2="12.7" y2="66.04" width="0.1524" layer="91"/> <pinref part="U$3" gate="G$1" pin="VCCIO@46"/> @@ -40976,10 +41273,6 @@ This requirement also applies to using our own USB VID/PID. <label x="73.66" y="-43.18" size="1.778" layer="95"/> </segment> <segment> -<pinref part="FT_VCC3V3_3" gate="VCC" pin="VCC"/> -<pinref part="FT_VCC3V3_4" gate="VCC" pin="VCC"/> -</segment> -<segment> <wire x1="-53.34" y1="-58.42" x2="-53.34" y2="-48.26" width="0.1524" layer="91"/> <label x="-58.42" y="-43.18" size="1.778" layer="95"/> <pinref part="FB2" gate="G$1" pin="P$1"/> @@ -40993,6 +41286,17 @@ This requirement also applies to using our own USB VID/PID. <wire x1="-5.08" y1="-58.42" x2="-7.62" y2="-58.42" width="0.1524" layer="91"/> <pinref part="FT_VCC3V3_8" gate="VCC" pin="VCC"/> </segment> +<segment> +<pinref part="C47" gate="G$1" pin="1"/> +<wire x1="45.72" y1="-63.5" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C48" gate="G$1" pin="1"/> +<wire x1="45.72" y1="-58.42" x2="45.72" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="53.34" y1="-63.5" x2="53.34" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="53.34" y1="-58.42" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> +<junction x="45.72" y="-58.42"/> +<label x="38.1" y="-43.18" size="1.778" layer="95"/> +<pinref part="FT_VCC3V3_3" gate="VCC" pin="VCC"/> +</segment> </net> <net name="N$22" class="0"> <segment> @@ -41223,7 +41527,6 @@ copy of reference circuit</text> </instance> <instance part="FRAME24" gate="G$1" x="-193.04" y="-129.54"/> <instance part="FT_VCC3V3_12" gate="VCC" x="48.26" y="-43.18" smashed="yes"/> -<instance part="FT_VCC3V3_13" gate="VCC" x="48.26" y="-43.18" smashed="yes"/> <instance part="FT_VCC3V3_14" gate="VCC" x="-83.82" y="-43.18" smashed="yes"/> <instance part="FT_VCC3V3_15" gate="VCC" x="-50.8" y="-43.18" smashed="yes"/> <instance part="FT_VCC3V3_16" gate="VCC" x="-25.4" y="-43.18" smashed="yes"/> @@ -41486,16 +41789,6 @@ copy of reference circuit</text> <label x="76.2" y="43.18" size="1.778" layer="95"/> </segment> <segment> -<pinref part="C181" gate="G$1" pin="1"/> -<wire x1="48.26" y1="-60.96" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> -<pinref part="C182" gate="G$1" pin="1"/> -<wire x1="48.26" y1="-55.88" x2="48.26" y2="-45.72" width="0.1524" layer="91"/> -<wire x1="55.88" y1="-60.96" x2="55.88" y2="-55.88" width="0.1524" layer="91"/> -<wire x1="55.88" y1="-55.88" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> -<junction x="48.26" y="-55.88"/> -<label x="40.64" y="-40.64" size="1.778" layer="95"/> -</segment> -<segment> <pinref part="FT_VCC3V1" gate="VCC" pin="VCC"/> <wire x1="15.24" y1="76.2" x2="15.24" y2="68.58" width="0.1524" layer="91"/> <pinref part="U$10" gate="G$1" pin="VCCIO@46"/> @@ -41524,10 +41817,6 @@ copy of reference circuit</text> <label x="76.2" y="-40.64" size="1.778" layer="95"/> </segment> <segment> -<pinref part="FT_VCC3V3_12" gate="VCC" pin="VCC"/> -<pinref part="FT_VCC3V3_13" gate="VCC" pin="VCC"/> -</segment> -<segment> <wire x1="-50.8" y1="-55.88" x2="-50.8" y2="-45.72" width="0.1524" layer="91"/> <label x="-55.88" y="-40.64" size="1.778" layer="95"/> <pinref part="FB4" gate="G$1" pin="P$1"/> @@ -41541,6 +41830,17 @@ copy of reference circuit</text> <wire x1="-2.54" y1="-55.88" x2="-5.08" y2="-55.88" width="0.1524" layer="91"/> <pinref part="FT_VCC3V3_17" gate="VCC" pin="VCC"/> </segment> +<segment> +<pinref part="C181" gate="G$1" pin="1"/> +<wire x1="48.26" y1="-60.96" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C182" gate="G$1" pin="1"/> +<wire x1="48.26" y1="-55.88" x2="48.26" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="55.88" y1="-60.96" x2="55.88" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="55.88" y1="-55.88" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> +<junction x="48.26" y="-55.88"/> +<label x="40.64" y="-40.64" size="1.778" layer="95"/> +<pinref part="FT_VCC3V3_12" gate="VCC" pin="VCC"/> +</segment> </net> <net name="N$8" class="0"> <segment> @@ -41565,22 +41865,6 @@ copy of reference circuit</text> <pinref part="Y2" gate="G$1" pin="1"/> </segment> </net> -<net name="FT_VPHY" class="0"> -<segment> -<pinref part="C183" gate="G$1" pin="1"/> -<wire x1="-38.1" y1="-55.88" x2="-25.4" y2="-55.88" width="0.1524" layer="91"/> -<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-60.96" width="0.1524" layer="91"/> -<pinref part="C184" gate="G$1" pin="1"/> -<wire x1="-38.1" y1="-60.96" x2="-38.1" y2="-55.88" width="0.1524" layer="91"/> -<junction x="-38.1" y="-55.88"/> -<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-45.72" width="0.1524" layer="91"/> -<junction x="-25.4" y="-55.88"/> -<label x="-27.94" y="-40.64" size="1.778" layer="95"/> -<pinref part="FB4" gate="G$1" pin="P$2"/> -<wire x1="-38.1" y1="-55.88" x2="-43.18" y2="-55.88" width="0.1524" layer="91"/> -<pinref part="FT_VCC3V3_16" gate="VCC" pin="VCC"/> -</segment> -</net> <net name="FT_MGMT_VPLL" class="0"> <segment> <pinref part="U$10" gate="G$1" pin="VPLL"/> @@ -41622,6 +41906,20 @@ copy of reference circuit</text> <wire x1="7.62" y1="68.58" x2="-8.89" y2="68.58" width="0.1524" layer="91"/> <label x="-8.89" y="68.58" size="1.778" layer="95"/> </segment> +<segment> +<pinref part="C183" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-55.88" x2="-25.4" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C184" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-60.96" x2="-38.1" y2="-55.88" width="0.1524" layer="91"/> +<junction x="-38.1" y="-55.88"/> +<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-25.4" y="-55.88"/> +<label x="-27.94" y="-35.56" size="1.778" layer="95"/> +<pinref part="FB4" gate="G$1" pin="P$2"/> +<wire x1="-38.1" y1="-55.88" x2="-43.18" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="FT_VCC3V3_16" gate="VCC" pin="VCC"/> +</segment> </net> <net name="FT_MGMT_TXD" class="0"> <segment> @@ -41664,8 +41962,8 @@ copy of reference circuit</text> <description>Tamper circuit Master Key Memory</description> <plain> -<text x="-81.28" y="63.5" size="2.54" layer="91">AVR Tiny Tamper Detect MCU</text> -<text x="132.08" y="40.64" size="2.54" layer="91">Panic button</text> +<text x="-81.28" y="63.5" size="3.81" layer="91">AVR Tiny Tamper Detect MCU</text> +<text x="121.92" y="38.1" size="2.54" layer="91">Panic button</text> <text x="137.16" y="-12.7" size="2.54" layer="91">Expansion GPIO</text> <text x="121.92" y="93.98" size="1.778" layer="91">Place a jumper between pins 1-2 to "emulate" having a battery present.</text> @@ -41720,8 +42018,8 @@ to "emulate" having a battery present.</text> <instance part="JP5" gate="G$1" x="165.1" y="-40.64" rot="R180"/> <instance part="SUPPLY52" gate="GND" x="149.86" y="-50.8"/> <instance part="P+24" gate="VCC" x="127" y="-17.78"/> -<instance part="U$4" gate="A" x="154.94" y="25.4"/> -<instance part="SUPPLY53" gate="GND" x="172.72" y="7.62"/> +<instance part="U$4" gate="A" x="144.78" y="22.86"/> +<instance part="SUPPLY53" gate="GND" x="162.56" y="5.08"/> <instance part="JP6" gate="G$1" x="162.56" y="78.74" rot="R180"/> <instance part="SUPPLY54" gate="GND" x="149.86" y="68.58"/> <instance part="P+25" gate="VCC" x="142.24" y="88.9" smashed="yes"/> @@ -41794,20 +42092,20 @@ to "emulate" having a battery present.</text> <segment> <pinref part="U$4" gate="A" pin="G1"/> <pinref part="SUPPLY53" gate="GND" pin="GND"/> -<wire x1="170.18" y1="27.94" x2="172.72" y2="27.94" width="0.1524" layer="91"/> -<wire x1="172.72" y1="27.94" x2="172.72" y2="22.86" width="0.1524" layer="91"/> +<wire x1="160.02" y1="25.4" x2="162.56" y2="25.4" width="0.1524" layer="91"/> +<wire x1="162.56" y1="25.4" x2="162.56" y2="20.32" width="0.1524" layer="91"/> <pinref part="U$4" gate="A" pin="G2"/> -<wire x1="172.72" y1="22.86" x2="172.72" y2="15.24" width="0.1524" layer="91"/> -<wire x1="172.72" y1="15.24" x2="172.72" y2="10.16" width="0.1524" layer="91"/> -<wire x1="170.18" y1="22.86" x2="172.72" y2="22.86" width="0.1524" layer="91"/> -<junction x="172.72" y="22.86"/> +<wire x1="162.56" y1="20.32" x2="162.56" y2="12.7" width="0.1524" layer="91"/> +<wire x1="162.56" y1="12.7" x2="162.56" y2="7.62" width="0.1524" layer="91"/> +<wire x1="160.02" y1="20.32" x2="162.56" y2="20.32" width="0.1524" layer="91"/> +<junction x="162.56" y="20.32"/> <pinref part="U$4" gate="A" pin="B2"/> -<wire x1="162.56" y1="15.24" x2="172.72" y2="15.24" width="0.1524" layer="91"/> -<junction x="172.72" y="15.24"/> +<wire x1="152.4" y1="12.7" x2="162.56" y2="12.7" width="0.1524" layer="91"/> +<junction x="162.56" y="12.7"/> <pinref part="U$4" gate="A" pin="B1"/> -<wire x1="162.56" y1="35.56" x2="172.72" y2="35.56" width="0.1524" layer="91"/> -<wire x1="172.72" y1="35.56" x2="172.72" y2="27.94" width="0.1524" layer="91"/> -<junction x="172.72" y="27.94"/> +<wire x1="152.4" y1="33.02" x2="162.56" y2="33.02" width="0.1524" layer="91"/> +<wire x1="162.56" y1="33.02" x2="162.56" y2="25.4" width="0.1524" layer="91"/> +<junction x="162.56" y="25.4"/> </segment> <segment> <pinref part="JP6" gate="G$1" pin="3"/> @@ -41940,13 +42238,13 @@ to "emulate" having a battery present.</text> <net name="AVR_LED1" class="0"> <segment> <wire x1="132.08" y1="-78.74" x2="127" y2="-78.74" width="0.1524" layer="91"/> -<label x="127" y="-78.74" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="127" y="-78.74" size="1.27" layer="95" rot="R180"/> <pinref part="R7" gate="A" pin="5"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT7/ADC7)_PA7"/> <wire x1="-99.06" y1="12.7" x2="-101.6" y2="12.7" width="0.1524" layer="91"/> -<label x="-101.6" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="12.7" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="N$5" class="0"> @@ -41959,13 +42257,13 @@ to "emulate" having a battery present.</text> <net name="AVR_LED2" class="0"> <segment> <wire x1="132.08" y1="-81.28" x2="127" y2="-81.28" width="0.1524" layer="91"/> -<label x="127" y="-81.28" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="127" y="-81.28" size="1.27" layer="95" rot="R180"/> <pinref part="R7" gate="A" pin="6"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT6/ADC6)_PA6"/> <wire x1="-99.06" y1="15.24" x2="-101.6" y2="15.24" width="0.1524" layer="91"/> -<label x="-101.6" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="15.24" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="N$15" class="0"> @@ -41978,13 +42276,13 @@ to "emulate" having a battery present.</text> <net name="AVR_LED3" class="0"> <segment> <wire x1="132.08" y1="-83.82" x2="127" y2="-83.82" width="0.1524" layer="91"/> -<label x="127" y="-83.82" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="127" y="-83.82" size="1.27" layer="95" rot="R180"/> <pinref part="R7" gate="A" pin="7"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PC!INT5/ADC5)_PA5"/> <wire x1="-99.06" y1="17.78" x2="-101.6" y2="17.78" width="0.1524" layer="91"/> -<label x="-101.6" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="17.78" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="N$16" class="0"> @@ -41997,120 +42295,121 @@ to "emulate" having a battery present.</text> <net name="AVR_LED4" class="0"> <segment> <wire x1="132.08" y1="-86.36" x2="127" y2="-86.36" width="0.1524" layer="91"/> -<label x="127" y="-86.36" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="127" y="-86.36" size="1.27" layer="95" rot="R180"/> <pinref part="R7" gate="A" pin="8"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT4/ADC4)_PA4"/> <wire x1="-99.06" y1="20.32" x2="-101.6" y2="20.32" width="0.1524" layer="91"/> -<label x="-101.6" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="20.32" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="AVR_GPIO_1" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="2"/> <wire x1="154.94" y1="-25.4" x2="149.86" y2="-25.4" width="0.1524" layer="91"/> -<label x="149.86" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-25.4" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT18/ADC18/TOCC2/RXD/INT1)_PC2"/> <wire x1="12.7" y1="33.02" x2="17.78" y2="33.02" width="0.1524" layer="91"/> -<label x="17.78" y="33.02" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="33.02" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_2" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="3"/> <wire x1="154.94" y1="-27.94" x2="149.86" y2="-27.94" width="0.1524" layer="91"/> -<label x="149.86" y="-27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-27.94" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT19/ADC19/TOCC3/TXD)_PC3"/> <wire x1="12.7" y1="30.48" x2="17.78" y2="30.48" width="0.1524" layer="91"/> -<label x="17.78" y="30.48" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="30.48" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_3" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="4"/> <wire x1="154.94" y1="-30.48" x2="149.86" y2="-30.48" width="0.1524" layer="91"/> -<label x="149.86" y="-30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-30.48" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT20/ADC20/TOCC4)_PC4"/> <wire x1="12.7" y1="27.94" x2="17.78" y2="27.94" width="0.1524" layer="91"/> -<label x="17.78" y="27.94" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="27.94" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_4" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="5"/> <wire x1="154.94" y1="-33.02" x2="149.86" y2="-33.02" width="0.1524" layer="91"/> -<label x="149.86" y="-33.02" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-33.02" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT21/ADC21/TOCC5/ICP1/T0)_PC5"/> <wire x1="12.7" y1="25.4" x2="17.78" y2="25.4" width="0.1524" layer="91"/> -<label x="17.78" y="25.4" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="25.4" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_5" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="6"/> <wire x1="154.94" y1="-35.56" x2="149.86" y2="-35.56" width="0.1524" layer="91"/> -<label x="149.86" y="-35.56" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-35.56" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT22/ADC22/CLKI/TOCC6)_PC6"/> <wire x1="12.7" y1="22.86" x2="17.78" y2="22.86" width="0.1524" layer="91"/> -<label x="17.78" y="22.86" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="22.86" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_6" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="7"/> <wire x1="154.94" y1="-38.1" x2="149.86" y2="-38.1" width="0.1524" layer="91"/> -<label x="149.86" y="-38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-38.1" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT23/ADC23/TOCC7/T1)_PC7"/> <wire x1="12.7" y1="20.32" x2="17.78" y2="20.32" width="0.1524" layer="91"/> -<label x="17.78" y="20.32" size="1.27" layer="95" xref="yes"/> +<label x="17.78" y="20.32" size="1.27" layer="95"/> </segment> </net> <net name="AVR_GPIO_7" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="8"/> <wire x1="154.94" y1="-40.64" x2="149.86" y2="-40.64" width="0.1524" layer="91"/> -<label x="149.86" y="-40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-40.64" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT0/ADC0)_PA0"/> <wire x1="-99.06" y1="30.48" x2="-101.6" y2="30.48" width="0.1524" layer="91"/> -<label x="-101.6" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="30.48" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="AVR_GPIO_8" class="0"> <segment> <pinref part="JP5" gate="G$1" pin="9"/> <wire x1="154.94" y1="-43.18" x2="149.86" y2="-43.18" width="0.1524" layer="91"/> -<label x="149.86" y="-43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="149.86" y="-43.18" size="1.27" layer="95" rot="R180"/> </segment> <segment> <pinref part="U3" gate="A" pin="(PCINT1/ADC1/AIN0)_PA1"/> <wire x1="-99.06" y1="27.94" x2="-101.6" y2="27.94" width="0.1524" layer="91"/> -<label x="-101.6" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="27.94" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="AVR_PANIC" class="0"> <segment> <pinref part="U3" gate="A" pin="(PCINT2/ADC2/AIN1)_PA2"/> <wire x1="-99.06" y1="25.4" x2="-101.6" y2="25.4" width="0.1524" layer="91"/> -<label x="-101.6" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="25.4" size="1.27" layer="95" rot="R180"/> +<label x="-101.6" y="25.4" size="1.27" layer="95" rot="R180"/> </segment> <segment> -<wire x1="147.32" y1="15.24" x2="142.24" y2="15.24" width="0.1524" layer="91"/> -<label x="142.24" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<wire x1="137.16" y1="12.7" x2="132.08" y2="12.7" width="0.1524" layer="91"/> +<label x="132.08" y="12.7" size="1.27" layer="95" rot="R180"/> <pinref part="U$4" gate="A" pin="A2"/> </segment> </net> @@ -42127,14 +42426,14 @@ to "emulate" having a battery present.</text> <segment> <pinref part="U3" gate="A" pin="PB2_(PCINT10/ADC10)"/> <wire x1="-99.06" y1="2.54" x2="-101.6" y2="2.54" width="0.1524" layer="91"/> -<label x="-101.6" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="2.54" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="AVR_GPIO_11" class="0"> <segment> <pinref part="U3" gate="A" pin="PB3_(PCINT11/ADC11)"/> <wire x1="-99.06" y1="0" x2="-101.6" y2="0" width="0.1524" layer="91"/> -<label x="-101.6" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="-101.6" y="0" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="FPGA_GPIO_TAMPER_0" class="0"> @@ -42168,41 +42467,43 @@ to "emulate" having a battery present.</text> <sheet> <description>Master Key Memory</description> <plain> -<text x="147.32" y="60.96" size="1.27" layer="91">CS pull-up to disable MKM by +<text x="162.56" y="60.96" size="1.27" layer="91">CS pull-up to disable MKM by default (allows programming of AVR)</text> <text x="17.78" y="27.94" size="1.27" layer="91">Pull-down CONTROL to enable 0 (AVR) by default</text> -<text x="114.3" y="106.68" size="2.54" layer="91">Master Key Memory</text> -<text x="55.88" y="106.68" size="2.54" layer="91">Analog switch</text> +<text x="129.54" y="106.68" size="2.54" layer="91">Master Key Memory</text> +<text x="-10.16" y="109.22" size="2.54" layer="91">Analog switch controlling access to the MKM. + +XXX suggest changing this chip to an 74AC244, +like the one used for the FPGA config memory.</text> <text x="2.54" y="35.56" size="1.27" layer="91" rot="R180">Make AVR unable to read the MKM by installing this jumper</text> -<text x="218.44" y="167.64" size="1.778" layer="91">XXX test this circuit</text> </plain> <instances> <instance part="U4" gate="A" x="78.74" y="50.8"/> -<instance part="U5" gate="A" x="132.08" y="60.96"/> -<instance part="SUPPLY46" gate="GND" x="111.76" y="35.56"/> -<instance part="P+21" gate="VCC" x="111.76" y="99.06" smashed="yes"/> -<instance part="R17" gate="G$1" x="104.14" y="50.8" rot="R90"/> +<instance part="U5" gate="A" x="147.32" y="60.96"/> +<instance part="SUPPLY46" gate="GND" x="127" y="35.56"/> +<instance part="P+21" gate="VCC" x="127" y="99.06" smashed="yes"/> +<instance part="R17" gate="G$1" x="119.38" y="50.8" rot="R90"/> <instance part="P+22" gate="VCC" x="55.88" y="99.06" smashed="yes"/> <instance part="SUPPLY47" gate="GND" x="55.88" y="12.7"/> -<instance part="R18" gate="G$1" x="106.68" y="73.66" rot="R90"/> +<instance part="R18" gate="G$1" x="121.92" y="73.66" rot="R90"/> <instance part="R19" gate="G$1" x="48.26" y="25.4" rot="R90"/> -<instance part="P+23" gate="VCC" x="99.06" y="58.42" smashed="yes"/> +<instance part="P+23" gate="VCC" x="111.76" y="58.42" smashed="yes"/> <instance part="C61" gate="G$1" x="50.8" y="86.36" smashed="yes"> <attribute name="NAME" x="40.64" y="83.82" size="1.27" layer="95" font="vector"/> <attribute name="VALUE" x="40.64" y="86.36" size="1.27" layer="96" font="vector"/> <attribute name="DIELECTRIC" x="50.8" y="86.36" size="1.778" layer="96" display="off"/> <attribute name="RATED_VOLTAGE" x="50.8" y="86.36" size="1.778" layer="96" display="off"/> </instance> -<instance part="C62" gate="G$1" x="116.84" y="91.44" smashed="yes"> -<attribute name="NAME" x="119.38" y="93.98" size="1.27" layer="95" font="vector"/> -<attribute name="VALUE" x="119.38" y="91.44" size="1.27" layer="96" font="vector"/> -<attribute name="DIELECTRIC" x="116.84" y="91.44" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="116.84" y="91.44" size="1.778" layer="96" display="off"/> +<instance part="C62" gate="G$1" x="132.08" y="91.44" smashed="yes"> +<attribute name="NAME" x="134.62" y="93.98" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="134.62" y="91.44" size="1.27" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="132.08" y="91.44" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="132.08" y="91.44" size="1.778" layer="96" display="off"/> </instance> -<instance part="SUPPLY48" gate="GND" x="116.84" y="81.28"/> +<instance part="SUPPLY48" gate="GND" x="132.08" y="81.28"/> <instance part="SUPPLY49" gate="GND" x="50.8" y="76.2"/> <instance part="JP4" gate="A" x="10.16" y="35.56"/> <instance part="SUPPLY51" gate="GND" x="10.16" y="22.86"/> @@ -42214,9 +42515,9 @@ MKM by installing this jumper</text> <net name="GND" class="1"> <segment> <pinref part="SUPPLY46" gate="GND" pin="GND"/> -<wire x1="111.76" y1="48.26" x2="111.76" y2="38.1" width="0.1524" layer="91"/> +<wire x1="127" y1="48.26" x2="127" y2="38.1" width="0.1524" layer="91"/> <pinref part="U5" gate="A" pin="VSS"/> -<wire x1="111.76" y1="48.26" x2="114.3" y2="48.26" width="0.1524" layer="91"/> +<wire x1="127" y1="48.26" x2="129.54" y2="48.26" width="0.1524" layer="91"/> </segment> <segment> <pinref part="U4" gate="A" pin="VSS"/> @@ -42236,7 +42537,7 @@ MKM by installing this jumper</text> <segment> <pinref part="C62" gate="G$1" pin="2"/> <pinref part="SUPPLY48" gate="GND" pin="GND"/> -<wire x1="116.84" y1="86.36" x2="116.84" y2="83.82" width="0.1524" layer="91"/> +<wire x1="132.08" y1="86.36" x2="132.08" y2="83.82" width="0.1524" layer="91"/> </segment> <segment> <pinref part="C61" gate="G$1" pin="2"/> @@ -42253,33 +42554,33 @@ MKM by installing this jumper</text> <segment> <pinref part="U5" gate="A" pin="!HOLD"/> <pinref part="R17" gate="G$1" pin="2"/> -<wire x1="114.3" y1="58.42" x2="104.14" y2="58.42" width="0.1524" layer="91"/> -<wire x1="104.14" y1="58.42" x2="104.14" y2="55.88" width="0.1524" layer="91"/> +<wire x1="129.54" y1="58.42" x2="119.38" y2="58.42" width="0.1524" layer="91"/> +<wire x1="119.38" y1="58.42" x2="119.38" y2="55.88" width="0.1524" layer="91"/> </segment> </net> <net name="MKM_SCK" class="0"> <segment> <pinref part="U5" gate="A" pin="SCK"/> <pinref part="U4" gate="A" pin="Z"/> -<wire x1="114.3" y1="60.96" x2="96.52" y2="60.96" width="0.1524" layer="91"/> +<wire x1="129.54" y1="60.96" x2="96.52" y2="60.96" width="0.1524" layer="91"/> </segment> </net> <net name="MKM_MOSI" class="0"> <segment> <pinref part="U4" gate="A" pin="Y"/> <pinref part="U5" gate="A" pin="SI"/> -<wire x1="96.52" y1="63.5" x2="114.3" y2="63.5" width="0.1524" layer="91"/> +<wire x1="96.52" y1="63.5" x2="129.54" y2="63.5" width="0.1524" layer="91"/> </segment> </net> <net name="MKM_CS_N" class="0"> <segment> <pinref part="U5" gate="A" pin="!CS"/> <pinref part="U4" gate="A" pin="X"/> -<wire x1="114.3" y1="66.04" x2="106.68" y2="66.04" width="0.1524" layer="91"/> +<wire x1="129.54" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/> <pinref part="R18" gate="G$1" pin="1"/> -<wire x1="106.68" y1="66.04" x2="96.52" y2="66.04" width="0.1524" layer="91"/> -<wire x1="106.68" y1="68.58" x2="106.68" y2="66.04" width="0.1524" layer="91"/> -<junction x="106.68" y="66.04"/> +<wire x1="121.92" y1="66.04" x2="96.52" y2="66.04" width="0.1524" layer="91"/> +<wire x1="121.92" y1="68.58" x2="121.92" y2="66.04" width="0.1524" layer="91"/> +<junction x="121.92" y="66.04"/> </segment> </net> <net name="MKM_MISO" class="0"> @@ -42287,28 +42588,28 @@ MKM by installing this jumper</text> <pinref part="U4" gate="A" pin="W"/> <wire x1="96.52" y1="68.58" x2="99.06" y2="68.58" width="0.1524" layer="91"/> <wire x1="99.06" y1="68.58" x2="99.06" y2="101.6" width="0.1524" layer="91"/> -<wire x1="99.06" y1="101.6" x2="152.4" y2="101.6" width="0.1524" layer="91"/> -<wire x1="152.4" y1="101.6" x2="152.4" y2="71.12" width="0.1524" layer="91"/> +<wire x1="99.06" y1="101.6" x2="167.64" y2="101.6" width="0.1524" layer="91"/> +<wire x1="167.64" y1="101.6" x2="167.64" y2="71.12" width="0.1524" layer="91"/> <pinref part="U5" gate="A" pin="SO"/> -<wire x1="152.4" y1="71.12" x2="149.86" y2="71.12" width="0.1524" layer="91"/> +<wire x1="167.64" y1="71.12" x2="165.1" y2="71.12" width="0.1524" layer="91"/> </segment> </net> <net name="3V3_BATT" class="0"> <segment> <pinref part="U5" gate="A" pin="VCC"/> <pinref part="P+21" gate="VCC" pin="VCC"/> -<wire x1="114.3" y1="71.12" x2="111.76" y2="71.12" width="0.1524" layer="91"/> -<wire x1="111.76" y1="71.12" x2="111.76" y2="83.82" width="0.1524" layer="91"/> +<wire x1="129.54" y1="71.12" x2="127" y2="71.12" width="0.1524" layer="91"/> +<wire x1="127" y1="71.12" x2="127" y2="83.82" width="0.1524" layer="91"/> <pinref part="R18" gate="G$1" pin="2"/> -<wire x1="111.76" y1="83.82" x2="111.76" y2="93.98" width="0.1524" layer="91"/> -<wire x1="111.76" y1="93.98" x2="111.76" y2="96.52" width="0.1524" layer="91"/> -<wire x1="106.68" y1="78.74" x2="106.68" y2="83.82" width="0.1524" layer="91"/> -<wire x1="106.68" y1="83.82" x2="111.76" y2="83.82" width="0.1524" layer="91"/> -<junction x="111.76" y="83.82"/> +<wire x1="127" y1="83.82" x2="127" y2="93.98" width="0.1524" layer="91"/> +<wire x1="127" y1="93.98" x2="127" y2="96.52" width="0.1524" layer="91"/> +<wire x1="121.92" y1="78.74" x2="121.92" y2="83.82" width="0.1524" layer="91"/> +<wire x1="121.92" y1="83.82" x2="127" y2="83.82" width="0.1524" layer="91"/> +<junction x="127" y="83.82"/> <pinref part="C62" gate="G$1" pin="1"/> -<wire x1="116.84" y1="93.98" x2="111.76" y2="93.98" width="0.1524" layer="91"/> -<junction x="111.76" y="93.98"/> -<label x="114.3" y="99.06" size="1.27" layer="95"/> +<wire x1="132.08" y1="93.98" x2="127" y2="93.98" width="0.1524" layer="91"/> +<junction x="127" y="93.98"/> +<label x="129.54" y="99.06" size="1.27" layer="95"/> </segment> <segment> <pinref part="U4" gate="A" pin="VDD"/> @@ -42324,9 +42625,9 @@ MKM by installing this jumper</text> <segment> <pinref part="R17" gate="G$1" pin="1"/> <pinref part="P+23" gate="VCC" pin="VCC"/> -<wire x1="104.14" y1="45.72" x2="99.06" y2="45.72" width="0.1524" layer="91"/> -<wire x1="99.06" y1="45.72" x2="99.06" y2="55.88" width="0.1524" layer="91"/> -<label x="96.52" y="48.26" size="1.27" layer="95" rot="R90"/> +<wire x1="119.38" y1="45.72" x2="111.76" y2="45.72" width="0.1524" layer="91"/> +<wire x1="111.76" y1="45.72" x2="111.76" y2="55.88" width="0.1524" layer="91"/> +<label x="109.22" y="48.26" size="1.27" layer="95" rot="R90"/> </segment> </net> <net name="MKM_CONTROL" class="0"> @@ -42415,7 +42716,6 @@ MKM by installing this jumper</text> *) INIT_B is bi-directional open-drain, must be driven with MOSFET to ground</text> <text x="-63.5" y="20.32" size="1.778" layer="91">*) "Not DONE" LED, should be of red color</text> -<text x="27.94" y="162.56" size="1.778" layer="91">XXX check with Joachim if it is enough that STM32 can rewrite FPGA config memory</text> </plain> <instances> <instance part="U7" gate="B0" x="-111.76" y="132.08"/> @@ -42578,7 +42878,6 @@ MKM by installing this jumper</text> <junction x="38.1" y="55.88"/> <label x="40.64" y="58.42" size="1.778" layer="95"/> <pinref part="C133" gate="G$1" pin="1"/> -<wire x1="81.28" y1="55.88" x2="78.74" y2="55.88" width="0.1524" layer="91"/> <pinref part="P+29" gate="VCC" pin="VCC"/> </segment> <segment> @@ -42626,12 +42925,12 @@ MKM by installing this jumper</text> <segment> <pinref part="U7" gate="B0" pin="TCK_0"/> <wire x1="-106.68" y1="121.92" x2="-71.12" y2="121.92" width="0.1524" layer="91"/> -<label x="-71.12" y="121.92" size="1.27" layer="95" xref="yes"/> +<label x="-71.12" y="121.92" size="1.27" layer="95"/> </segment> <segment> <pinref part="SV3" gate="1" pin="2"/> <wire x1="78.74" y1="53.34" x2="71.12" y2="53.34" width="0.1524" layer="91"/> -<label x="63.5" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="63.5" y="53.34" size="1.27" layer="95" rot="R180"/> <pinref part="R37" gate="G$1" pin="1"/> <wire x1="71.12" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/> <wire x1="71.12" y1="60.96" x2="71.12" y2="53.34" width="0.1524" layer="91"/> @@ -42642,12 +42941,12 @@ MKM by installing this jumper</text> <segment> <pinref part="U7" gate="B0" pin="TDI_0"/> <wire x1="-106.68" y1="119.38" x2="-71.12" y2="119.38" width="0.1524" layer="91"/> -<label x="-71.12" y="119.38" size="1.27" layer="95" xref="yes"/> +<label x="-71.12" y="119.38" size="1.27" layer="95"/> </segment> <segment> <pinref part="SV3" gate="1" pin="4"/> <wire x1="78.74" y1="48.26" x2="66.04" y2="48.26" width="0.1524" layer="91"/> -<label x="63.5" y="48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="63.5" y="48.26" size="1.27" layer="95" rot="R180"/> <pinref part="R35" gate="G$1" pin="1"/> <wire x1="66.04" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/> <wire x1="66.04" y1="60.96" x2="66.04" y2="48.26" width="0.1524" layer="91"/> @@ -42658,24 +42957,24 @@ MKM by installing this jumper</text> <segment> <pinref part="U7" gate="B0" pin="TDO_0"/> <wire x1="-106.68" y1="116.84" x2="-71.12" y2="116.84" width="0.1524" layer="91"/> -<label x="-71.12" y="116.84" size="1.27" layer="95" xref="yes"/> +<label x="-71.12" y="116.84" size="1.27" layer="95"/> </segment> <segment> <pinref part="SV3" gate="1" pin="5"/> <wire x1="78.74" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/> -<label x="63.5" y="45.72" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="63.5" y="45.72" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="FPGA_JTAG_TMS" class="0"> <segment> <pinref part="U7" gate="B0" pin="TMS_0"/> <wire x1="-106.68" y1="114.3" x2="-71.12" y2="114.3" width="0.1524" layer="91"/> -<label x="-71.12" y="114.3" size="1.27" layer="95" xref="yes"/> +<label x="-71.12" y="114.3" size="1.27" layer="95"/> </segment> <segment> <pinref part="SV3" gate="1" pin="3"/> <wire x1="78.74" y1="50.8" x2="68.58" y2="50.8" width="0.1524" layer="91"/> -<label x="63.5" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/> +<label x="63.5" y="50.8" size="1.27" layer="95" rot="R180"/> <pinref part="R36" gate="G$1" pin="1"/> <wire x1="68.58" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/> <wire x1="68.58" y1="60.96" x2="68.58" y2="50.8" width="0.1524" layer="91"/> @@ -42862,66 +43161,72 @@ MKM by installing this jumper</text> <sheet> <description>FPGA supporting components</description> <plain> -<text x="81.28" y="27.94" size="1.778" layer="91">*) HOLD feature not used +<text x="38.1" y="58.42" size="1.778" layer="91">*) HOLD feature not used *) PROM is write-protected by default, to disable write protection (such as during firmware update), jumper must be inserted</text> -<text x="-71.12" y="-66.04" size="2.54" layer="91">FPGA clock</text> -<text x="22.86" y="55.88" size="2.54" layer="91">FPGA config memory</text> -<text x="-134.62" y="-12.7" size="1.27" layer="91">Pull-down CONTROL to -enable 0 (PROM) by default</text> -<text x="-149.86" y="81.28" size="2.54" layer="91">Analog switch to boot FPGA from config memory, or from ARM - -XXX this probably needs more HW support. FPGA is SPI master when booting from config memory, -but should be SPI slave when being fed a bitstream from the ARM.</text> -<text x="-152.4" y="-2.54" size="1.27" layer="91">Install this jumper to allow +<text x="-20.32" y="-35.56" size="2.54" layer="91">FPGA clock</text> +<text x="38.1" y="76.2" size="2.54" layer="91">FPGA config memory, 128 Mbit</text> +<text x="-119.38" y="73.66" size="2.54" layer="91">SPI mux to let ARM override access to +FPGA config memory (to reprogram FPGA)</text> +<text x="-111.76" y="12.7" size="1.27" layer="91">Install this jumper to allow +ARM to configure the FPGA</text> +<text x="-96.52" y="43.18" size="1.27" layer="91">ARM access default +disabled through pull-up</text> +<text x="-96.52" y="-25.4" size="1.27" layer="91">FPGA access default +enabled through pull-down</text> +<text x="-111.76" y="-15.24" size="1.27" layer="91">Install this jumper to allow ARM to configure the FPGA</text> -<text x="-160.02" y="27.94" size="1.27" layer="91">XXX are jumpers on the ARM SPI -nets really needed, when CONTROL -defaults to the PROM?</text> </plain> <instances> -<instance part="IC3" gate="A" x="50.8" y="13.97"/> -<instance part="SUPPLY147" gate="GND" x="27.94" y="-7.62"/> -<instance part="R9" gate="G$1" x="27.94" y="30.48" rot="R90"> -<attribute name="TOLERANCE" x="27.94" y="30.48" size="1.778" layer="96" rot="R90" display="off"/> -</instance> -<instance part="JP7" gate="A" x="17.78" y="30.48"/> -<instance part="R20" gate="G$1" x="17.78" y="5.08" rot="R90"> -<attribute name="TOLERANCE" x="17.78" y="5.08" size="1.778" layer="96" rot="R90" display="off"/> -</instance> -<instance part="SUPPLY148" gate="GND" x="17.78" y="-7.62"/> -<instance part="SUPPLY149" gate="GND" x="101.6" y="-7.62"/> -<instance part="Q5" gate="G$1" x="-53.34" y="-91.44"/> -<instance part="C110" gate="G$1" x="-83.82" y="-93.98"> -<attribute name="DIELECTRIC" x="-83.82" y="-93.98" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="-83.82" y="-93.98" size="1.778" layer="96" display="off"/> -<attribute name="TOLERANCE" x="-83.82" y="-93.98" size="1.778" layer="96" display="off"/> -</instance> -<instance part="SUPPLY159" gate="GND" x="-68.58" y="-106.68"/> -<instance part="SUPPLY160" gate="GND" x="-83.82" y="-106.68"/> -<instance part="R28" gate="G$1" x="-53.34" y="-76.2" rot="R180"/> -<instance part="C134" gate="G$1" x="101.6" y="7.62"> -<attribute name="DIELECTRIC" x="101.6" y="7.62" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="101.6" y="7.62" size="1.778" layer="96" display="off"/> -<attribute name="TOLERANCE" x="101.6" y="7.62" size="1.778" layer="96" display="off"/> -</instance> -<instance part="P+34" gate="VCC" x="17.78" y="50.8" smashed="yes"/> -<instance part="P+35" gate="VCC" x="-83.82" y="-73.66" smashed="yes"/> -<instance part="U1" gate="A" x="-81.28" y="22.86"/> -<instance part="P+57" gate="VCC" x="-104.14" y="71.12" smashed="yes"/> -<instance part="SUPPLY13" gate="GND" x="-104.14" y="-15.24"/> -<instance part="R32" gate="G$1" x="-111.76" y="-2.54" rot="R90"/> -<instance part="C8" gate="G$1" x="-109.22" y="58.42" smashed="yes"> -<attribute name="NAME" x="-119.38" y="55.88" size="1.27" layer="95" font="vector"/> -<attribute name="VALUE" x="-119.38" y="58.42" size="1.27" layer="96" font="vector"/> -<attribute name="DIELECTRIC" x="-109.22" y="58.42" size="1.778" layer="96" display="off"/> -<attribute name="RATED_VOLTAGE" x="-109.22" y="58.42" size="1.778" layer="96" display="off"/> -</instance> -<instance part="SUPPLY14" gate="GND" x="-109.22" y="48.26"/> -<instance part="FRAME10" gate="G$1" x="-210.82" y="-132.08"/> -<instance part="JP8" gate="A" x="-121.92" y="5.08" rot="R90"/> +<instance part="IC3" gate="A" x="71.12" y="16.51"/> +<instance part="SUPPLY147" gate="GND" x="50.8" y="-5.08"/> +<instance part="R9" gate="G$1" x="50.8" y="33.02" rot="R90"> +<attribute name="TOLERANCE" x="50.8" y="33.02" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="JP7" gate="A" x="27.94" y="33.02"/> +<instance part="R20" gate="G$1" x="27.94" y="7.62" rot="R90"> +<attribute name="TOLERANCE" x="27.94" y="7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY148" gate="GND" x="27.94" y="-5.08"/> +<instance part="SUPPLY149" gate="GND" x="111.76" y="-5.08"/> +<instance part="Q5" gate="G$1" x="0" y="-58.42"/> +<instance part="C110" gate="G$1" x="-30.48" y="-60.96"> +<attribute name="DIELECTRIC" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY159" gate="GND" x="-15.24" y="-73.66"/> +<instance part="SUPPLY160" gate="GND" x="-30.48" y="-73.66"/> +<instance part="R28" gate="G$1" x="0" y="-43.18" rot="R180"/> +<instance part="C134" gate="G$1" x="111.76" y="10.16" smashed="yes"> +<attribute name="DIELECTRIC" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="103.124" y="5.461" size="1.778" layer="95"/> +<attribute name="VALUE" x="100.584" y="2.921" size="1.778" layer="96"/> +</instance> +<instance part="P+34" gate="VCC" x="27.94" y="53.34" smashed="yes"/> +<instance part="P+35" gate="VCC" x="-30.48" y="-40.64" smashed="yes"/> +<instance part="JP8" gate="A" x="-73.66" y="17.78" rot="R90"/> +<instance part="IC5" gate="A" x="-45.72" y="25.4"/> +<instance part="IC5" gate="B" x="-45.72" y="-2.54"/> +<instance part="IC5" gate="P" x="-109.22" y="43.18"/> +<instance part="P+5" gate="VCC" x="-109.22" y="58.42" smashed="yes"/> +<instance part="C214" gate="G$1" x="-119.38" y="43.18" smashed="yes"> +<attribute name="NAME" x="-117.856" y="43.561" size="1.778" layer="95"/> +<attribute name="VALUE" x="-117.856" y="38.481" size="1.778" layer="96"/> +</instance> +<instance part="R77" gate="G$1" x="-30.48" y="40.64" rot="R90"/> +<instance part="P+6" gate="VCC" x="-30.48" y="53.34" smashed="yes"/> +<instance part="SUPPLY20" gate="GND" x="-109.22" y="27.94"/> +<instance part="R80" gate="G$1" x="-66.04" y="40.64" rot="R90"/> +<instance part="P+12" gate="VCC" x="-66.04" y="53.34" smashed="yes"/> +<instance part="R81" gate="G$1" x="-66.04" y="-20.32" rot="R270"/> +<instance part="SUPPLY14" gate="GND" x="-66.04" y="-30.48"/> +<instance part="JP9" gate="A" x="-73.66" y="-10.16" rot="R90"/> +<instance part="FRAME10" gate="G$1" x="-134.62" y="-88.9"/> </instances> <busses> </busses> @@ -42929,257 +43234,301 @@ defaults to the PROM?</text> <net name="GND" class="1"> <segment> <pinref part="SUPPLY147" gate="GND" pin="GND"/> -<wire x1="27.94" y1="-5.08" x2="27.94" y2="12.7" width="0.1524" layer="91"/> +<wire x1="50.8" y1="-2.54" x2="50.8" y2="15.24" width="0.1524" layer="91"/> <pinref part="IC3" gate="A" pin="VSS"/> -<wire x1="27.94" y1="12.7" x2="33.02" y2="12.7" width="0.1524" layer="91"/> +<wire x1="50.8" y1="15.24" x2="53.34" y2="15.24" width="0.1524" layer="91"/> </segment> <segment> <pinref part="SUPPLY148" gate="GND" pin="GND"/> <pinref part="R20" gate="G$1" pin="1"/> -<wire x1="17.78" y1="-5.08" x2="17.78" y2="0" width="0.1524" layer="91"/> +<wire x1="27.94" y1="-2.54" x2="27.94" y2="2.54" width="0.1524" layer="91"/> </segment> <segment> <pinref part="SUPPLY149" gate="GND" pin="GND"/> -<wire x1="101.6" y1="-5.08" x2="101.6" y2="2.54" width="0.1524" layer="91"/> +<wire x1="111.76" y1="-2.54" x2="111.76" y2="5.08" width="0.1524" layer="91"/> <pinref part="C134" gate="G$1" pin="2"/> </segment> <segment> <pinref part="SUPPLY159" gate="GND" pin="GND"/> -<wire x1="-68.58" y1="-104.14" x2="-68.58" y2="-96.52" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-71.12" x2="-15.24" y2="-63.5" width="0.1524" layer="91"/> <pinref part="Q5" gate="G$1" pin="GND"/> -<wire x1="-68.58" y1="-96.52" x2="-66.04" y2="-96.52" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-63.5" x2="-12.7" y2="-63.5" width="0.1524" layer="91"/> </segment> <segment> <pinref part="C110" gate="G$1" pin="2"/> <pinref part="SUPPLY160" gate="GND" pin="GND"/> -<wire x1="-83.82" y1="-99.06" x2="-83.82" y2="-104.14" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-66.04" x2="-30.48" y2="-71.12" width="0.1524" layer="91"/> </segment> <segment> -<pinref part="U1" gate="A" pin="VSS"/> -<pinref part="SUPPLY13" gate="GND" pin="GND"/> -<wire x1="-99.06" y1="-2.54" x2="-104.14" y2="-2.54" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="-2.54" x2="-104.14" y2="-10.16" width="0.1524" layer="91"/> -<pinref part="U1" gate="A" pin="VEE"/> -<wire x1="-104.14" y1="-10.16" x2="-104.14" y2="-12.7" width="0.1524" layer="91"/> -<wire x1="-99.06" y1="0" x2="-104.14" y2="0" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="0" x2="-104.14" y2="-2.54" width="0.1524" layer="91"/> -<junction x="-104.14" y="-2.54"/> -<pinref part="R32" gate="G$1" pin="1"/> -<wire x1="-111.76" y1="-7.62" x2="-111.76" y2="-10.16" width="0.1524" layer="91"/> -<wire x1="-111.76" y1="-10.16" x2="-104.14" y2="-10.16" width="0.1524" layer="91"/> -<junction x="-104.14" y="-10.16"/> +<pinref part="IC5" gate="P" pin="GND"/> +<wire x1="-109.22" y1="30.48" x2="-109.22" y2="33.02" width="0.1524" layer="91"/> +<pinref part="C214" gate="G$1" pin="2"/> +<wire x1="-109.22" y1="33.02" x2="-109.22" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="38.1" x2="-119.38" y2="33.02" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="33.02" x2="-109.22" y2="33.02" width="0.1524" layer="91"/> +<junction x="-109.22" y="33.02"/> +<pinref part="SUPPLY20" gate="GND" pin="GND"/> </segment> <segment> -<pinref part="C8" gate="G$1" pin="2"/> +<pinref part="R81" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="-25.4" x2="-66.04" y2="-27.94" width="0.1524" layer="91"/> <pinref part="SUPPLY14" gate="GND" pin="GND"/> -<wire x1="-109.22" y1="53.34" x2="-109.22" y2="50.8" width="0.1524" layer="91"/> </segment> </net> <net name="VCCO_3V3" class="0"> <segment> <pinref part="R9" gate="G$1" pin="2"/> -<wire x1="27.94" y1="35.56" x2="27.94" y2="40.64" width="0.1524" layer="91"/> -<wire x1="27.94" y1="40.64" x2="17.78" y2="40.64" width="0.1524" layer="91"/> -<label x="20.32" y="48.26" size="1.778" layer="95"/> +<wire x1="50.8" y1="38.1" x2="50.8" y2="43.18" width="0.1524" layer="91"/> +<wire x1="50.8" y1="43.18" x2="27.94" y2="43.18" width="0.1524" layer="91"/> +<label x="30.48" y="50.8" size="1.778" layer="95"/> <pinref part="IC3" gate="A" pin="VCC"/> -<wire x1="17.78" y1="40.64" x2="17.78" y2="48.26" width="0.1524" layer="91"/> -<wire x1="69.85" y1="20.32" x2="76.2" y2="20.32" width="0.1524" layer="91"/> -<wire x1="76.2" y1="20.32" x2="76.2" y2="40.64" width="0.1524" layer="91"/> -<wire x1="76.2" y1="40.64" x2="27.94" y2="40.64" width="0.1524" layer="91"/> -<junction x="27.94" y="40.64"/> +<wire x1="27.94" y1="43.18" x2="27.94" y2="50.8" width="0.1524" layer="91"/> +<wire x1="90.17" y1="22.86" x2="96.52" y2="22.86" width="0.1524" layer="91"/> +<wire x1="96.52" y1="22.86" x2="96.52" y2="43.18" width="0.1524" layer="91"/> +<wire x1="96.52" y1="43.18" x2="50.8" y2="43.18" width="0.1524" layer="91"/> +<junction x="50.8" y="43.18"/> <pinref part="IC3" gate="A" pin="!HOLD!/DQ3"/> -<wire x1="69.85" y1="17.78" x2="76.2" y2="17.78" width="0.1524" layer="91"/> -<wire x1="76.2" y1="17.78" x2="76.2" y2="20.32" width="0.1524" layer="91"/> -<junction x="76.2" y="20.32"/> +<wire x1="90.17" y1="20.32" x2="96.52" y2="20.32" width="0.1524" layer="91"/> +<wire x1="96.52" y1="20.32" x2="96.52" y2="22.86" width="0.1524" layer="91"/> +<junction x="96.52" y="22.86"/> <pinref part="JP7" gate="A" pin="2"/> -<wire x1="17.78" y1="38.1" x2="17.78" y2="40.64" width="0.1524" layer="91"/> -<junction x="17.78" y="40.64"/> -<wire x1="101.6" y1="17.78" x2="101.6" y2="10.16" width="0.1524" layer="91"/> -<wire x1="76.2" y1="17.78" x2="101.6" y2="17.78" width="0.1524" layer="91"/> -<junction x="76.2" y="17.78"/> +<wire x1="27.94" y1="40.64" x2="27.94" y2="43.18" width="0.1524" layer="91"/> +<junction x="27.94" y="43.18"/> +<wire x1="111.76" y1="20.32" x2="111.76" y2="12.7" width="0.1524" layer="91"/> +<wire x1="96.52" y1="20.32" x2="111.76" y2="20.32" width="0.1524" layer="91"/> +<junction x="96.52" y="20.32"/> <pinref part="C134" gate="G$1" pin="1"/> <pinref part="P+34" gate="VCC" pin="VCC"/> </segment> <segment> <pinref part="C110" gate="G$1" pin="1"/> -<wire x1="-83.82" y1="-91.44" x2="-83.82" y2="-86.36" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-58.42" x2="-30.48" y2="-53.34" width="0.1524" layer="91"/> <pinref part="Q5" gate="G$1" pin="VCC"/> -<wire x1="-83.82" y1="-86.36" x2="-68.58" y2="-86.36" width="0.1524" layer="91"/> -<wire x1="-68.58" y1="-86.36" x2="-66.04" y2="-86.36" width="0.1524" layer="91"/> -<wire x1="-83.82" y1="-86.36" x2="-83.82" y2="-76.2" width="0.1524" layer="91"/> -<junction x="-83.82" y="-86.36"/> -<label x="-99.06" y="-76.2" size="1.778" layer="95"/> +<wire x1="-30.48" y1="-53.34" x2="-15.24" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-53.34" x2="-12.7" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-53.34" x2="-30.48" y2="-43.18" width="0.1524" layer="91"/> +<junction x="-30.48" y="-53.34"/> +<label x="-45.72" y="-48.26" size="1.778" layer="95"/> <pinref part="R28" gate="G$1" pin="2"/> -<wire x1="-58.42" y1="-76.2" x2="-68.58" y2="-76.2" width="0.1524" layer="91"/> -<wire x1="-68.58" y1="-76.2" x2="-68.58" y2="-86.36" width="0.1524" layer="91"/> -<junction x="-68.58" y="-86.36"/> +<wire x1="-5.08" y1="-43.18" x2="-15.24" y2="-43.18" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-43.18" x2="-15.24" y2="-53.34" width="0.1524" layer="91"/> +<junction x="-15.24" y="-53.34"/> <pinref part="P+35" gate="VCC" pin="VCC"/> </segment> +<segment> +<pinref part="IC5" gate="P" pin="VCC"/> +<pinref part="P+5" gate="VCC" pin="VCC"/> +<wire x1="-109.22" y1="50.8" x2="-109.22" y2="53.34" width="0.1524" layer="91"/> +<pinref part="C214" gate="G$1" pin="1"/> +<wire x1="-109.22" y1="53.34" x2="-109.22" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="45.72" x2="-119.38" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="53.34" x2="-109.22" y2="53.34" width="0.1524" layer="91"/> +<junction x="-109.22" y="53.34"/> +<label x="-106.68" y="58.42" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+6" gate="VCC" pin="VCC"/> +<pinref part="R77" gate="G$1" pin="2"/> +<wire x1="-30.48" y1="50.8" x2="-30.48" y2="45.72" width="0.1524" layer="91"/> +<label x="-27.94" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+12" gate="VCC" pin="VCC"/> +<pinref part="R80" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="50.8" x2="-66.04" y2="45.72" width="0.1524" layer="91"/> +<label x="-63.5" y="53.34" size="1.778" layer="95"/> +</segment> </net> <net name="FPGA_PROM_SCLK" class="0"> <segment> <pinref part="IC3" gate="A" pin="C"/> -<wire x1="69.85" y1="15.24" x2="73.66" y2="15.24" width="0.1524" layer="91"/> -<label x="73.66" y="15.24" size="1.27" layer="95"/> +<wire x1="90.17" y1="17.78" x2="93.98" y2="17.78" width="0.1524" layer="91"/> +<label x="93.98" y="17.78" size="1.27" layer="95"/> </segment> <segment> -<wire x1="-99.06" y1="12.7" x2="-119.38" y2="12.7" width="0.1524" layer="91"/> -<label x="-104.14" y="15.24" size="1.27" layer="95" rot="R180"/> -<pinref part="U1" gate="A" pin="Z0"/> +<pinref part="IC5" gate="A" pin="Y2"/> +<wire x1="-33.02" y1="27.94" x2="-27.94" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="27.94" x2="-27.94" y2="0" width="0.1524" layer="91"/> +<pinref part="IC5" gate="B" pin="Y2"/> +<wire x1="-27.94" y1="0" x2="-33.02" y2="0" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="27.94" x2="-20.32" y2="27.94" width="0.1524" layer="91"/> +<junction x="-27.94" y="27.94"/> +<label x="-20.32" y="27.94" size="1.27" layer="95"/> </segment> </net> <net name="FPGA_PROM_MOSI" class="0"> <segment> <pinref part="IC3" gate="A" pin="DQ0"/> -<wire x1="69.85" y1="12.7" x2="73.66" y2="12.7" width="0.1524" layer="91"/> -<label x="73.66" y="12.7" size="1.27" layer="95"/> +<wire x1="90.17" y1="15.24" x2="93.98" y2="15.24" width="0.1524" layer="91"/> +<label x="93.98" y="15.24" size="1.27" layer="95"/> </segment> <segment> -<wire x1="-99.06" y1="27.94" x2="-119.38" y2="27.94" width="0.1524" layer="91"/> -<label x="-104.14" y="30.48" size="1.27" layer="95" rot="R180"/> -<pinref part="U1" gate="A" pin="Y0"/> +<pinref part="IC5" gate="B" pin="Y3"/> +<wire x1="-33.02" y1="-2.54" x2="-25.4" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="-2.54" x2="-25.4" y2="25.4" width="0.1524" layer="91"/> +<pinref part="IC5" gate="A" pin="Y3"/> +<wire x1="-33.02" y1="25.4" x2="-25.4" y2="25.4" width="0.1524" layer="91"/> +<junction x="-25.4" y="25.4"/> +<wire x1="-25.4" y1="25.4" x2="-20.32" y2="25.4" width="0.1524" layer="91"/> +<label x="-20.32" y="25.4" size="1.27" layer="95"/> </segment> </net> -<net name="KSM_PROM_CS_N" class="0"> +<net name="FPGA_PROM_CS_N" class="0"> <segment> <pinref part="IC3" gate="A" pin="!S"/> -<wire x1="33.02" y1="20.32" x2="27.94" y2="20.32" width="0.1524" layer="91"/> -<label x="0" y="20.32" size="1.27" layer="95"/> +<wire x1="53.34" y1="22.86" x2="50.8" y2="22.86" width="0.1524" layer="91"/> <pinref part="R9" gate="G$1" pin="1"/> -<wire x1="27.94" y1="20.32" x2="0" y2="20.32" width="0.1524" layer="91"/> -<wire x1="27.94" y1="20.32" x2="27.94" y2="25.4" width="0.1524" layer="91"/> -<junction x="27.94" y="20.32"/> +<wire x1="50.8" y1="22.86" x2="50.8" y2="27.94" width="0.1524" layer="91"/> +<label x="33.02" y="22.86" size="1.27" layer="95"/> +<wire x1="50.8" y1="22.86" x2="33.02" y2="22.86" width="0.1524" layer="91"/> +<junction x="50.8" y="22.86"/> </segment> <segment> -<wire x1="-99.06" y1="35.56" x2="-119.38" y2="35.56" width="0.1524" layer="91"/> -<label x="-104.14" y="38.1" size="1.27" layer="95" rot="R180"/> -<pinref part="U1" gate="A" pin="X0"/> +<pinref part="IC5" gate="B" pin="Y1"/> +<wire x1="-33.02" y1="2.54" x2="-30.48" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="2.54" x2="-30.48" y2="30.48" width="0.1524" layer="91"/> +<pinref part="IC5" gate="A" pin="Y1"/> +<wire x1="-30.48" y1="30.48" x2="-33.02" y2="30.48" width="0.1524" layer="91"/> +<junction x="-30.48" y="30.48"/> +<label x="-20.32" y="30.48" size="1.27" layer="95"/> +<pinref part="R77" gate="G$1" pin="1"/> +<wire x1="-30.48" y1="30.48" x2="-20.32" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="35.56" x2="-30.48" y2="30.48" width="0.1524" layer="91"/> +<junction x="-30.48" y="30.48"/> </segment> </net> <net name="FPGA_PROM_MISO" class="0"> <segment> <pinref part="IC3" gate="A" pin="DQ1"/> -<wire x1="33.02" y1="17.78" x2="0" y2="17.78" width="0.1524" layer="91"/> -<label x="0" y="17.78" size="1.27" layer="95"/> +<wire x1="53.34" y1="20.32" x2="33.02" y2="20.32" width="0.1524" layer="91"/> +<label x="33.02" y="20.32" size="1.27" layer="95"/> </segment> <segment> -<wire x1="-99.06" y1="20.32" x2="-119.38" y2="20.32" width="0.1524" layer="91"/> -<label x="-104.14" y="22.86" size="1.27" layer="95" rot="R180"/> -<pinref part="U1" gate="A" pin="W0"/> +<pinref part="IC5" gate="A" pin="A4"/> +<wire x1="-58.42" y1="22.86" x2="-60.96" y2="22.86" width="0.1524" layer="91"/> +<pinref part="IC5" gate="B" pin="A4"/> +<wire x1="-60.96" y1="22.86" x2="-71.12" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-58.42" y1="-5.08" x2="-60.96" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="-5.08" x2="-60.96" y2="22.86" width="0.1524" layer="91"/> +<junction x="-60.96" y="22.86"/> +<label x="-71.12" y="22.86" size="1.27" layer="95" rot="R180"/> </segment> </net> <net name="FPGA_PROM_W_N" class="0"> <segment> <pinref part="IC3" gate="A" pin="!W!/VPP/DQ2"/> -<wire x1="33.02" y1="15.24" x2="17.78" y2="15.24" width="0.1524" layer="91"/> +<wire x1="53.34" y1="17.78" x2="27.94" y2="17.78" width="0.1524" layer="91"/> <pinref part="R20" gate="G$1" pin="2"/> -<wire x1="17.78" y1="10.16" x2="17.78" y2="15.24" width="0.1524" layer="91"/> -<junction x="17.78" y="15.24"/> +<wire x1="27.94" y1="12.7" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +<junction x="27.94" y="17.78"/> <pinref part="JP7" gate="A" pin="1"/> -<wire x1="17.78" y1="22.86" x2="17.78" y2="15.24" width="0.1524" layer="91"/> +<wire x1="27.94" y1="25.4" x2="27.94" y2="17.78" width="0.1524" layer="91"/> </segment> </net> <net name="FPGA_GCLK" class="0"> <segment> -<wire x1="-40.64" y1="-91.44" x2="-25.4" y2="-91.44" width="0.1524" layer="91"/> -<label x="-25.4" y="-91.44" size="1.778" layer="95" xref="yes"/> +<wire x1="12.7" y1="-58.42" x2="20.32" y2="-58.42" width="0.1524" layer="91"/> +<label x="20.32" y="-58.42" size="1.778" layer="95" xref="yes"/> <pinref part="Q5" gate="G$1" pin="FO"/> </segment> </net> <net name="N$33" class="0"> <segment> <pinref part="Q5" gate="G$1" pin="OE"/> -<wire x1="-40.64" y1="-86.36" x2="-38.1" y2="-86.36" width="0.1524" layer="91"/> -<wire x1="-38.1" y1="-86.36" x2="-38.1" y2="-76.2" width="0.1524" layer="91"/> +<wire x1="12.7" y1="-53.34" x2="15.24" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="15.24" y1="-53.34" x2="15.24" y2="-43.18" width="0.1524" layer="91"/> <pinref part="R28" gate="G$1" pin="1"/> -<wire x1="-38.1" y1="-76.2" x2="-48.26" y2="-76.2" width="0.1524" layer="91"/> +<wire x1="15.24" y1="-43.18" x2="5.08" y2="-43.18" width="0.1524" layer="91"/> </segment> </net> <net name="FPGA_CFG_SCLK" class="0"> <segment> -<pinref part="U1" gate="A" pin="Z"/> -<wire x1="-60.96" y1="33.02" x2="-63.5" y2="33.02" width="0.1524" layer="91"/> -<label x="-60.96" y="33.02" size="1.27" layer="95" xref="yes"/> +<pinref part="IC5" gate="B" pin="A2"/> +<wire x1="-58.42" y1="0" x2="-71.12" y2="0" width="0.1524" layer="91"/> +<label x="-71.12" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FPGA_CFG_MOSI" class="0"> <segment> -<pinref part="U1" gate="A" pin="Y"/> -<wire x1="-63.5" y1="35.56" x2="-60.96" y2="35.56" width="0.1524" layer="91"/> -<label x="-60.96" y="35.56" size="1.27" layer="95" xref="yes"/> +<pinref part="IC5" gate="B" pin="A3"/> +<wire x1="-58.42" y1="-2.54" x2="-71.12" y2="-2.54" width="0.1524" layer="91"/> +<label x="-71.12" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FPGA_CFG_CS_N" class="0"> <segment> -<pinref part="U1" gate="A" pin="X"/> -<wire x1="-60.96" y1="38.1" x2="-63.5" y2="38.1" width="0.1524" layer="91"/> -<label x="-60.96" y="38.1" size="1.27" layer="95" xref="yes"/> +<pinref part="IC5" gate="B" pin="A1"/> +<wire x1="-58.42" y1="2.54" x2="-71.12" y2="2.54" width="0.1524" layer="91"/> +<label x="-71.12" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="FPGA_CFG_MISO" class="0"> <segment> -<pinref part="U1" gate="A" pin="W"/> -<wire x1="-63.5" y1="40.64" x2="-60.96" y2="40.64" width="0.1524" layer="91"/> -<label x="-60.96" y="40.64" size="1.27" layer="95" xref="yes"/> -</segment> -</net> -<net name="3V3_BATT" class="0"> -<segment> -<pinref part="U1" gate="A" pin="VDD"/> -<pinref part="P+57" gate="VCC" pin="VCC"/> -<wire x1="-99.06" y1="40.64" x2="-104.14" y2="40.64" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="40.64" x2="-104.14" y2="60.96" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="60.96" x2="-104.14" y2="68.58" width="0.1524" layer="91"/> -<wire x1="-104.14" y1="60.96" x2="-109.22" y2="60.96" width="0.1524" layer="91"/> -<junction x="-104.14" y="60.96"/> -<pinref part="C8" gate="G$1" pin="1"/> -<label x="-101.6" y="71.12" size="1.27" layer="95"/> +<pinref part="IC5" gate="B" pin="Y4"/> +<wire x1="-33.02" y1="-5.08" x2="-20.32" y2="-5.08" width="0.1524" layer="91"/> +<label x="-20.32" y="-5.08" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="ARM_FPGA_CFG_CS_N" class="0"> <segment> -<wire x1="-99.06" y1="33.02" x2="-104.14" y2="33.02" width="0.1524" layer="91"/> -<label x="-104.14" y="33.02" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U1" gate="A" pin="X1"/> +<pinref part="IC5" gate="A" pin="A1"/> +<wire x1="-58.42" y1="30.48" x2="-71.12" y2="30.48" width="0.1524" layer="91"/> +<label x="-71.12" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="ARM_FPGA_CFG_MOSI" class="0"> <segment> -<wire x1="-99.06" y1="25.4" x2="-104.14" y2="25.4" width="0.1524" layer="91"/> -<label x="-104.14" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U1" gate="A" pin="Y1"/> +<pinref part="IC5" gate="A" pin="A3"/> +<wire x1="-58.42" y1="25.4" x2="-71.12" y2="25.4" width="0.1524" layer="91"/> +<label x="-71.12" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> <net name="ARM_FPGA_CFG_MISO" class="0"> <segment> -<wire x1="-99.06" y1="17.78" x2="-104.14" y2="17.78" width="0.1524" layer="91"/> -<label x="-104.14" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> -<pinref part="U1" gate="A" pin="W1"/> +<pinref part="IC5" gate="A" pin="Y4"/> +<wire x1="-33.02" y1="22.86" x2="-20.32" y2="22.86" width="0.1524" layer="91"/> +<label x="-20.32" y="22.86" size="1.27" layer="95" xref="yes"/> </segment> </net> <net name="ARM_FPGA_CFG_SCLK" class="0"> <segment> -<pinref part="U1" gate="A" pin="Z1"/> -<wire x1="-99.06" y1="10.16" x2="-104.14" y2="10.16" width="0.1524" layer="91"/> -<label x="-104.14" y="10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="IC5" gate="A" pin="A2"/> +<wire x1="-58.42" y1="27.94" x2="-71.12" y2="27.94" width="0.1524" layer="91"/> +<label x="-71.12" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_ARM_ENA" class="0"> +<segment> +<pinref part="JP8" gate="A" pin="2"/> +<wire x1="-81.28" y1="17.78" x2="-83.82" y2="17.78" width="0.1524" layer="91"/> +<label x="-83.82" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> -<net name="N$3" class="0"> +<net name="SPI_A_TRISTATE" class="0"> <segment> -<pinref part="U1" gate="A" pin="CONTROL"/> -<pinref part="R32" gate="G$1" pin="2"/> -<wire x1="-99.06" y1="5.08" x2="-111.76" y2="5.08" width="0.1524" layer="91"/> -<wire x1="-111.76" y1="5.08" x2="-111.76" y2="2.54" width="0.1524" layer="91"/> -<wire x1="-111.76" y1="5.08" x2="-114.3" y2="5.08" width="0.1524" layer="91"/> -<junction x="-111.76" y="5.08"/> +<pinref part="IC5" gate="A" pin="G"/> +<wire x1="-58.42" y1="17.78" x2="-66.04" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R80" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="35.56" x2="-66.04" y2="17.78" width="0.1524" layer="91"/> +<junction x="-66.04" y="17.78"/> <pinref part="JP8" gate="A" pin="1"/> </segment> </net> -<net name="ARM_FPGA_CFG_CONTROL" class="0"> +<net name="SPI_B_TRISTATE" class="0"> <segment> -<pinref part="JP8" gate="A" pin="2"/> -<wire x1="-129.54" y1="5.08" x2="-132.08" y2="5.08" width="0.1524" layer="91"/> -<label x="-132.08" y="5.08" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="IC5" gate="B" pin="G"/> +<wire x1="-58.42" y1="-10.16" x2="-66.04" y2="-10.16" width="0.1524" layer="91"/> +<pinref part="R81" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="-10.16" x2="-66.04" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-66.04" y="-10.16"/> +<pinref part="JP9" gate="A" pin="1"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_FPGA_DIS" class="0"> +<segment> +<pinref part="JP9" gate="A" pin="2"/> +<wire x1="-81.28" y1="-10.16" x2="-83.82" y2="-10.16" width="0.1524" layer="91"/> +<label x="-83.82" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> </segment> </net> </nets> @@ -47146,40 +47495,6 @@ should be tweaked after experiments </nets> </sheet> </sheets> -<errors> -<approved hash="102,4,226.06,222.25,VCC,3V3,,,,"/> -<approved hash="102,4,226.06,67.31,VCC,3V3,,,,"/> -<approved hash="102,4,375.92,156.21,VCC,3V3,,,,"/> -<approved hash="102,4,274.32,217.17,VCC,3V3,,,,"/> -<approved hash="102,4,101.6,72.39,VCC,3V3,,,,"/> -<approved hash="102,4,104.14,163.83,VCC,3V3,,,,"/> -<approved hash="102,10,124.46,60.96,VCC,FT_VCC3V3,,,,"/> -<approved hash="104,4,213.36,99.06,U$1G$3,VSS,GND,,,"/> -<approved hash="104,4,218.44,99.06,U$1G$3,VSS,GND,,,"/> -<approved hash="104,4,233.68,99.06,U$1G$3,VSS,GND,,,"/> -<approved hash="104,4,238.76,99.06,U$1G$3,VSS,GND,,,"/> -<approved hash="104,4,205.74,58.42,U$1G$4,VDD,3V3,,,"/> -<approved hash="104,4,218.44,-50.8,U$1G$4,VSS,GND,,,"/> -<approved hash="104,4,210.82,58.42,U$1G$4,VDD,3V3,,,"/> -<approved hash="104,4,233.68,-50.8,U$1G$4,VSS,GND,,,"/> -<approved hash="104,4,241.3,58.42,U$1G$4,VDD,3V3,,,"/> -<approved hash="104,4,238.76,-50.8,U$1G$4,VSS,GND,,,"/> -<approved hash="104,4,246.38,58.42,U$1G$4,VDD,3V3,,,"/> -<approved hash="104,4,436.88,43.18,U$2,VCC,3V3,,,"/> -<approved hash="104,10,45.72,73.66,U$3,VREGIN,FT_VREGIN,,,"/> -<approved hash="104,10,45.72,68.58,U$3,VCCD,FT_VCC3V3,,,"/> -<approved hash="104,10,45.72,66.04,U$3,VCCORE,FT_VCCORE,,,"/> -<approved hash="104,10,45.72,63.5,U$3,VCCA,FT_VCCA,,,"/> -<approved hash="104,10,63.5,5.08,U$3,AGND,GND,,,"/> -<approved hash="104,10,66.04,5.08,U$3,AGND,GND,,,"/> -<approved hash="104,10,68.58,5.08,U$3,AGND,GND,,,"/> -<approved hash="208,4,226.06,67.31,3V3,sup,,,,"/> -<approved hash="208,4,226.06,222.25,3V3,sup,,,,"/> -<approved hash="208,4,274.32,217.17,3V3,sup,,,,"/> -<approved hash="208,4,101.6,72.39,3V3,sup,,,,"/> -<approved hash="208,4,104.14,163.83,3V3,sup,,,,"/> -<approved hash="208,4,375.92,156.21,3V3,sup,,,,"/> -</errors> </schematic> </drawing> <compatibility> |