diff options
| author | Fredrik Thulin <fredrik@thulin.net> | 2016-07-21 10:32:24 +0200 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2016-07-21 10:32:24 +0200 |
| commit | 4686ce499992b012d318e4c37a08632fafb58545 (patch) | |
| tree | 6f5a7ee278053998c1c1011ecca4b1d532e6dcc0 /cad/rev02/alpha | |
| parent | 8ae0e55fabfd752f4476e0afef8b69fe920c6f67 (diff) | |
reorganize
Diffstat (limited to 'cad/rev02/alpha')
| -rw-r--r-- | cad/rev02/alpha/rev02/rev02-bom.csv | 95 | ||||
| -rw-r--r-- | cad/rev02/alpha/rev02/rev02.brd | 11624 | ||||
| -rw-r--r-- | cad/rev02/alpha/rev02/rev02.sch | 47974 |
3 files changed, 59693 insertions, 0 deletions
diff --git a/cad/rev02/alpha/rev02/rev02-bom.csv b/cad/rev02/alpha/rev02/rev02-bom.csv new file mode 100644 index 0000000..5c13b14 --- /dev/null +++ b/cad/rev02/alpha/rev02/rev02-bom.csv @@ -0,0 +1,95 @@ +"Qty";"Value";"Device";"Package";"Parts";"Description";"DIELECTRIC";"MF";"MFR";"MPN";"OC_DIGIKEY";"OC_FARNELL";"OC_NEWARK";"PACKAGE";"POWERRATING";"PRICE100_DIGIKEY";"PRICE100_FARNELL";"PROD_ID";"RATED_VOLTAGE";"SF_ID";"SUPPLIER";"TOLERANCE";"TP_SIGNAL_NAME";"VALUE"; +"5";"";"JP1Q";"JP1";"JP2, JP6, JP7, JP8, JP9";"JUMPER";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";""; +"1";"";"M03LOCK";"1X03_LOCK";"JP4";"Header 3";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";""; +"2";"";"M03X2NO_SILK";"2X3-NS";"J2, J3";"2x3 .1" header.";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";""; +"1";"";"M10LOCK";"1X10_LOCK";"JP5";"Header 10";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";""; +"1";"";"MA08-1";"MA08-1";"SV1";"PIN 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y="79.2988" size="0.8128" layer="21" rot="R180">SWD</text> +<text x="52.578" y="18.6944" size="0.8128" layer="21">KILL MISO</text> +<text x="112.1664" y="1.9304" size="1.27" layer="2" font="vector" ratio="18">2 PWR</text> +<text x="112.1664" y="1.9304" size="1.27" layer="15" font="vector" ratio="18">15 GND</text> +<text x="93.5736" y="77.1652" size="0.8128" layer="21" rot="R180">NRST</text> +<text x="88.392" y="77.1652" size="0.8128" layer="21" rot="R180">CLK</text> +<text x="85.344" y="77.1652" size="0.8128" layer="21" rot="R180">IO</text> +<text x="83.2104" y="77.1652" size="0.8128" layer="21" rot="R180">GND</text> +<text x="80.772" y="77.1652" size="0.8128" layer="21" rot="R180">3V3</text> +</plain> +<libraries> +<library name="resistor"> +<description><b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<map name="nav_main"> +<area shape="rect" coords="0,1,140,23" href="../military_specs.asp" title=""> +<area shape="rect" coords="0,24,140,51" href="../about.asp" title=""> +<area shape="rect" coords="1,52,140,77" href="../rfq.asp" title=""> +<area shape="rect" coords="0,78,139,103" href="../products.asp" title=""> +<area shape="rect" coords="1,102,138,128" href="../excess_inventory.asp" title=""> +<area shape="rect" coords="1,129,138,150" href="../edge.asp" title=""> +<area shape="rect" coords="1,151,139,178" href="../industry_links.asp" title=""> +<area shape="rect" coords="0,179,139,201" href="../comments.asp" title=""> +<area shape="rect" coords="1,203,138,231" href="../directory.asp" title=""> +<area shape="default" nohref> +</map> + +<html> + +<title></title> + + <LINK REL="StyleSheet" TYPE="text/css" HREF="style-sheet.css"> + +<body bgcolor="#ffffff" text="#000000" marginwidth="0" marginheight="0" topmargin="0" leftmargin="0"> +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0 height="55%"> +<tr valign="top"> + +</td> +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> + </B> + </TD><TD>&nbsp;</TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > + 3005P<BR> + 3006P<BR> + 3006W<BR> + 3006Y<BR> + 3009P<BR> + 3009W<BR> + 3009Y<BR> + 3057J<BR> + 3057L<BR> + 3057P<BR> + 3057Y<BR> + 3059J<BR> + 3059L<BR> + 3059P<BR> + 3059Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 89P<BR> + 89W<BR> + 89X<BR> + 89PH<BR> + 76P<BR> + 89XH<BR> + 78SLT<BR> + 78L&nbsp;ALT<BR> + 56P&nbsp;ALT<BR> + 78P&nbsp;ALT<BR> + T8S<BR> + 78L<BR> + 56P<BR> + 78P<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + T18/784<BR> + 783<BR> + 781<BR> + -<BR> + -<BR> + -<BR> + 2199<BR> + 1697/1897<BR> + 1680/1880<BR> + 2187<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 8035EKP/CT20/RJ-20P<BR> + -<BR> + RJ-20X<BR> + -<BR> + -<BR> + -<BR> + 1211L<BR> + 8012EKQ&nbsp;ALT<BR> + 8012EKR&nbsp;ALT<BR> + 1211P<BR> + 8012EKJ<BR> + 8012EKL<BR> + 8012EKQ<BR> + 8012EKR<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 2101P<BR> + 2101W<BR> + 2101Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 2102L<BR> + 2102S<BR> + 2102Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVMCOG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 43P<BR> + 43W<BR> + 43Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 40L<BR> + 40P<BR> + 40Y<BR> + 70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 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non-functional items- supply symbols, logos, notations, frame blocks, etc.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ +<br><br> +You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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This is the same library that we use internally, and it is regularly updated. The newest version can always be found at <b>www.microBuilder.eu</b>. If you find this library useful, please feel free to purchase something from our online store. Please also note that all holes are optimised for metric drill bits!</p> + +<h3>Obligatory Warning</h3> +<p>While it probably goes without saying, there are no guarantees that the footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for information puposes only, and are used at your own discretion. While we make every effort to produce accurate footprints, and many of the items found in this library have be proven in production, we can't make any promises of suitability for a specific purpose. If you do find any errors, though, please feel free to contact us at www.microbuilder.eu to let us know about it so that we can update the library accordingly!</p> + +<h3>License</h3> +<p>This work is placed in the public domain, and may be freely used for commercial and non-commercial work with the following conditions:</p> +<p>THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +</p></description> +<packages> +<package name="_0603MP"> +<description><b>0603 MicroPitch</b></description> +<wire x1="-0.432" y1="-0.306" x2="0.432" y2="-0.306" width="0.1016" layer="51"/> +<wire x1="0.432" y1="0.306" x2="-0.432" y2="0.306" width="0.1016" layer="51"/> +<wire x1="0" y1="0.254" x2="0" y2="-0.254" width="0.2032" layer="21"/> +<smd name="1" x="-0.762" y="0" dx="0.8" dy="0.8" layer="1"/> +<smd name="2" x="0.762" y="0" dx="0.8" dy="0.8" layer="1"/> +<text x="-0.9525" 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If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ +<br><br> +You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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name="rc-master"> +<description><b>R/C MASTER! - v1.07 (07/03/2007)</b><p> +<p>This library is a collection of SMD and through hole resistors and capacitors by various manufacturers. Some of these include types from Panasonic, Kemet, BC Components and others. Many of the packages were adapted from <b>rcl.lbr</b> and <b>cap-pan40.lbr</b> and have been renamed and grouped in a more logical form.</p><p>Silkscreen elements are a minimum of 8 mils in width with larger components using 10 mil widths. Most of the SMD components have text sizes of 0 .04" and thru-hole components are 0.05" in size. A text ratio of 14 is used in both cases. Where practical, the elements are aligned on a 12.5 mil or 6.25 mil grid depending on the pad size and spacing.</p> +<p><h4>All capacitors are grouped by the following naming conventions:</h4></p> +<table width="380" border="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><div align="center"><strong>Prefix</strong></div></td> + <td width="289" bgcolor="#33CCFF"><div align="center"><strong>Description</strong></div></td> + </tr> + <tr> + <td><div align="center">CBP_</div></td> + <td><div align="center">Bipolar Electrolytic Types</div></td> + </tr> + <tr> + <td><div align="center">CCA_</div></td> + <td><div align="center">Chip Cap Array Types</div></td> + </tr> + <tr> + <td><div align="center">CP_</div></td> + <td><div align="center">Polarized Electrolytic/Tantalum Types</div></td> + </tr> + <tr> + <td><div align="center">C_</div></td> + <td><div align="center">Non-Polarized Film / Chip Types</div></td> + </tr> + <tr> + <td><div align="center">FB_</div></td> + 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name="rlMinPadInner" value="10mil"/> +<param name="rlMaxPadInner" value="20mil"/> +<param name="rlMinPadBottom" value="10mil"/> +<param name="rlMaxPadBottom" value="20mil"/> +<param name="rlMinViaOuter" value="6mil"/> +<param name="rlMaxViaOuter" value="20mil"/> +<param name="rlMinViaInner" value="6mil"/> +<param name="rlMaxViaInner" value="20mil"/> +<param name="rlMinMicroViaOuter" value="4mil"/> +<param name="rlMaxMicroViaOuter" value="20mil"/> +<param name="rlMinMicroViaInner" value="4mil"/> +<param name="rlMaxMicroViaInner" value="20mil"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="0"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="1"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="2mil"/> +<param name="mlMaxStopFrame" value="2mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="25mil"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="10mil"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="0"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="AutoGrid" value="1"/> +<param name="Efforts" value="0"/> +<param name="TopRouterVariant" value="1"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="|"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="-"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="LOGO1" library="SparkFun-Aesthetics" package="OSHW-LOGO-L_COPPER" value="OSHW-LOGOL-COPPER" x="105.3263" y="66.6385" smashed="yes"/> +<element name="C16" library="resistor" package="C0603" value="0.1 uF" x="26.9836" y="39.7692" smashed="yes" rot="R180"> +<attribute name="NAME" x="24.977" y="40.2264" size="0.8128" layer="25" font="vector" rot="R180"/> +<attribute name="VALUE" x="24.977" y="39.0326" size="0.4064" layer="27" rot="R180"/> +<attribute name="DIELECTRIC" value="X7R" x="26.9836" y="39.7692" size="1.778" layer="27" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" value="50V" x="26.9836" y="39.7692" size="1.778" layer="27" rot="R180" display="off"/> +<attribute name="TOLERANCE" value="10%" x="26.9836" y="39.7692" size="1.778" layer="27" rot="R180" display="off"/> +</element> +<element name="Q2" library="transistor-npn" package="SOT23-BEC" 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+Please keep in mind, that these devices are necessary for the +automatic wiring of the supply signals.<p> +The pin name defined in the symbol is identical to the net which is to be wired automatically.<p> +In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.<p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +</packages> +<symbols> +<symbol name="GND"> +<wire x1="-1.27" y1="0" x2="1.27" y2="0" width="0.254" layer="94"/> +<wire x1="1.27" y1="0" x2="0" y2="-1.27" width="0.254" layer="94"/> +<wire x1="0" y1="-1.27" x2="-1.27" y2="0" width="0.254" layer="94"/> +<text x="-1.905" y="-3.175" size="1.778" layer="96">>VALUE</text> +<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="GND" prefix="SUPPLY"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="GND" symbol="GND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="resistor"> +<description><b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<map name="nav_main"> +<area shape="rect" coords="0,1,140,23" href="../military_specs.asp" title=""> +<area shape="rect" coords="0,24,140,51" href="../about.asp" title=""> +<area shape="rect" coords="1,52,140,77" href="../rfq.asp" title=""> +<area shape="rect" coords="0,78,139,103" href="../products.asp" title=""> +<area shape="rect" coords="1,102,138,128" href="../excess_inventory.asp" title=""> +<area shape="rect" coords="1,129,138,150" href="../edge.asp" title=""> +<area shape="rect" coords="1,151,139,178" href="../industry_links.asp" title=""> +<area shape="rect" coords="0,179,139,201" href="../comments.asp" title=""> +<area shape="rect" coords="1,203,138,231" href="../directory.asp" title=""> +<area shape="default" nohref> +</map> + +<html> + +<title></title> + + <LINK REL="StyleSheet" TYPE="text/css" HREF="style-sheet.css"> + +<body bgcolor="#ffffff" text="#000000" marginwidth="0" marginheight="0" topmargin="0" leftmargin="0"> +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0 height="55%"> +<tr valign="top"> + +</td> +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> + </B> + </TD><TD>&nbsp;</TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > + 3005P<BR> + 3006P<BR> + 3006W<BR> + 3006Y<BR> + 3009P<BR> + 3009W<BR> + 3009Y<BR> + 3057J<BR> + 3057L<BR> + 3057P<BR> + 3057Y<BR> + 3059J<BR> + 3059L<BR> + 3059P<BR> + 3059Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 89P<BR> + 89W<BR> + 89X<BR> + 89PH<BR> + 76P<BR> + 89XH<BR> + 78SLT<BR> + 78L&nbsp;ALT<BR> + 56P&nbsp;ALT<BR> + 78P&nbsp;ALT<BR> + T8S<BR> + 78L<BR> + 56P<BR> + 78P<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + T18/784<BR> + 783<BR> + 781<BR> + -<BR> + -<BR> + -<BR> + 2199<BR> + 1697/1897<BR> + 1680/1880<BR> + 2187<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 8035EKP/CT20/RJ-20P<BR> + -<BR> + RJ-20X<BR> + -<BR> + -<BR> + -<BR> + 1211L<BR> + 8012EKQ&nbsp;ALT<BR> + 8012EKR&nbsp;ALT<BR> + 1211P<BR> + 8012EKJ<BR> + 8012EKL<BR> + 8012EKQ<BR> + 8012EKR<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 2101P<BR> + 2101W<BR> + 2101Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 2102L<BR> + 2102S<BR> + 2102Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVMCOG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 43P<BR> + 43W<BR> + 43Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 40L<BR> + 40P<BR> + 40Y<BR> + 70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST63Z<BR> + ST63Y<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST5P<BR> + ST5W<BR> + ST5X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 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Chip Capacitor KEMET 1825 reflow solder</b><p> +Metric Code Size 4564</description> +<wire x1="-1.525" y1="3.125" x2="1.525" y2="3.125" width="0.1016" layer="51"/> +<wire x1="1.525" y1="-3.125" x2="-1.525" y2="-3.125" width="0.1016" layer="51"/> +<smd name="1" x="-1.5" y="0" dx="1.8" dy="6.9" layer="1"/> +<smd name="2" x="1.5" y="0" dx="1.8" dy="6.9" layer="1"/> +<text x="-1.6" y="3.55" size="1.016" layer="25">>NAME</text> +<text x="-1.6" y="-4.625" size="1.016" layer="27">>VALUE</text> +<rectangle x1="-1.6" y1="-3.2" x2="-1.1" y2="3.2" layer="51"/> +<rectangle x1="1.1" y1="-3.2" x2="1.6" y2="3.2" layer="51"/> +</package> +<package name="C2220K"> +<description><b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650</description> +<wire x1="-2.725" y1="2.425" x2="2.725" y2="2.425" width="0.1016" layer="51"/> +<wire x1="2.725" y1="-2.425" x2="-2.725" y2="-2.425" width="0.1016" layer="51"/> +<smd name="1" x="-2.55" y="0" dx="1.85" dy="5.5" layer="1"/> +<smd name="2" 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+<package name="HPC0201"> +<description><b> </b><p> +Source: http://www.vishay.com/docs/10129/hpc0201a.pdf</description> +<smd name="1" x="-0.18" y="0" dx="0.2" dy="0.35" layer="1"/> +<smd name="2" x="0.18" y="0" dx="0.2" dy="0.35" layer="1"/> +<text x="-0.75" y="0.74" size="1.27" layer="25">>NAME</text> +<text x="-0.785" y="-1.865" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-0.305" y1="-0.15" x2="0.305" y2="0.15" layer="51"/> +</package> +<package name="C1808"> +<description><b>CAPACITOR</b><p> +Source: AVX .. aphvc.pdf</description> +<wire x1="-1.4732" y1="0.9502" x2="1.4732" y2="0.9502" width="0.1016" layer="51"/> +<wire x1="-1.4478" y1="-0.9502" x2="1.4732" y2="-0.9502" width="0.1016" layer="51"/> +<smd name="1" x="-1.95" y="0" dx="1.6" dy="2.2" layer="1"/> +<smd name="2" x="1.95" y="0" dx="1.6" dy="2.2" layer="1"/> +<text x="-2.233" y="1.827" size="1.27" layer="25">>NAME</text> +<text x="-2.233" y="-2.842" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-2.275" 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pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C4532" package="C4532"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="C4564" package="C4564"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-024X044" package="C025-024X044"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-025X050" package="C025-025X050"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="025-030X050" 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pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="050-055X075" package="C050-055X075"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="050-075X075" package="C050-075X075"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="050H075X075" package="C050H075X075"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="075-032X103" package="C075-032X103"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="075-042X103" package="C075-042X103"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="075-052X106" package="C075-052X106"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102-043X133" package="C102-043X133"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102-054X133" package="C102-054X133"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102-064X133" package="C102-064X133"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="102_152-062X184" package="C102_152-062X184"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="150-054X183" package="C150-054X183"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="150-064X183" package="C150-064X183"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="150-072X183" package="C150-072X183"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology 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If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ +<br><br> +You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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+<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP19R" package="TP19R"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP20R" package="TP20R"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP13SQ" package="TP13SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP14SQ" package="TP14SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP15SQ" package="TP15SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP16SQ" package="TP16SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP17SQ" package="TP17SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP18SQ" package="TP18SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP19SQ" package="TP19SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +<device name="TP20SQ" package="TP20SQ"> +<connects> +<connect gate="G$1" pin="TP" pad="TP"/> +</connects> +<technologies> +<technology name=""> +<attribute name="TP_SIGNAL_NAME" value="" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="transistor"> +<description><b>Transistors</b><p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="SOT23"> +<description><b>SOT-23</b></description> +<wire x1="1.4224" y1="0.6604" x2="1.4224" y2="-0.6604" width="0.1524" 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length="short" direction="pas" swaplevel="3" rot="R90"/> +<pin name="C" x="2.54" y="5.08" visible="off" length="short" direction="pas" swaplevel="2" rot="R270"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="BC847" prefix="T"> +<description><b>NPN TRANSISTOR</b></description> +<gates> +<gate name="G$1" symbol="NPN" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT23"> +<connects> +<connect gate="G$1" pin="B" pad="1"/> +<connect gate="G$1" pin="C" pad="3"/> +<connect gate="G$1" pin="E" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="microbuilder"> +<description><h2><b>microBuilder.eu</b> Eagle Footprint Library</h2> + +<p>Footprints for common components used in our projects and products. This is the same library that we use internally, and it is regularly updated. The newest version can always be found at <b>www.microBuilder.eu</b>. If you find this library useful, please feel free to purchase something from our online store. Please also note that all holes are optimised for metric drill bits!</p> + +<h3>Obligatory Warning</h3> +<p>While it probably goes without saying, there are no guarantees that the footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for information puposes only, and are used at your own discretion. While we make every effort to produce accurate footprints, and many of the items found in this library have be proven in production, we can't make any promises of suitability for a specific purpose. If you do find any errors, though, please feel free to contact us at www.microbuilder.eu to let us know about it so that we can update the library accordingly!</p> + +<h3>License</h3> +<p>This work is placed in the public domain, and may be freely used for commercial and non-commercial work with the following conditions:</p> +<p>THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +</p></description> +<packages> +<package name="0805"> +<description>0805 (2012 Metric)</description> +<wire x1="-1.873" y1="0.883" x2="1.873" y2="0.883" width="0.0508" layer="39"/> +<wire x1="1.873" y1="-0.883" x2="-1.873" y2="-0.883" width="0.0508" layer="39"/> +<wire x1="-1.873" y1="-0.883" x2="-1.873" y2="0.883" width="0.0508" layer="39"/> +<wire x1="-0.381" y1="0.66" x2="0.381" y2="0.66" width="0.1016" layer="51"/> +<wire x1="-0.356" y1="-0.66" x2="0.381" y2="-0.66" width="0.1016" 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ratio="10">>VALUE</text> +</package> +<package name="CRYSTAL_2.5X2"> +<smd name="1" x="-0.825" y="-0.625" dx="0.9" dy="0.8" layer="1"/> +<smd name="2" x="0.825" y="-0.625" dx="0.9" dy="0.8" layer="1"/> +<smd name="3" x="0.825" y="0.625" dx="0.9" dy="0.8" layer="1"/> +<smd name="4" x="-0.825" y="0.625" dx="0.9" dy="0.8" layer="1"/> +<wire x1="-1.25" y1="1" x2="1.25" y2="1" width="0.127" layer="51"/> +<wire x1="1.25" y1="1" x2="1.25" y2="-1" width="0.127" layer="51"/> +<wire x1="1.25" y1="-1" x2="-1.25" y2="-1" width="0.127" layer="51"/> +<wire x1="-1.25" y1="-1" x2="-1.25" y2="1" width="0.127" layer="51"/> +<wire x1="-1.5" y1="1.25" x2="1.5" y2="1.25" width="0.127" layer="21"/> +<wire x1="1.5" y1="1.25" x2="1.5" y2="-1.25" width="0.127" layer="21"/> +<wire x1="1.5" y1="-1.25" x2="-1.5" y2="-1.25" width="0.127" layer="21"/> +<wire x1="-1.5" y1="-1.25" x2="-1.5" y2="1.25" width="0.127" layer="21"/> +<text x="-1.532" y="1.528" size="0.8128" layer="25" ratio="18">>NAME</text> +<text x="-1.405" y="-1.909" size="0.4064" layer="27" ratio="10">>VALUE</text> +</package> +</packages> +<symbols> +<symbol name="FERRITE"> +<text x="-1.27" y="1.905" size="1.27" layer="95">>NAME</text> +<text x="-1.27" y="-3.175" size="1.27" layer="95">>VALUE</text> +<pin name="P$1" x="-2.54" y="0" visible="off" length="short" direction="pas"/> +<pin name="P$2" x="2.54" y="0" visible="off" length="short" direction="pas" rot="R180"/> +<wire x1="-1.27" y1="0.9525" x2="1.27" y2="0.9525" width="0.4064" layer="94"/> +<wire x1="1.27" y1="0.9525" x2="1.27" y2="-0.9525" width="0.4064" layer="94"/> +<wire x1="1.27" y1="-0.9525" x2="-1.27" y2="-0.9525" width="0.4064" layer="94"/> +<wire x1="-1.27" y1="-0.9525" x2="-1.27" y2="0.9525" width="0.4064" layer="94"/> +</symbol> +<symbol name="CRYSTAL"> +<wire x1="-0.381" y1="1.524" x2="-0.381" y2="-1.524" width="0.254" layer="94"/> +<wire x1="-0.381" y1="-1.524" x2="0.381" y2="-1.524" width="0.254" layer="94"/> +<wire x1="0.381" y1="-1.524" x2="0.381" y2="1.524" width="0.254" layer="94"/> +<wire x1="0.381" y1="1.524" x2="-0.381" y2="1.524" width="0.254" layer="94"/> +<wire x1="-1.016" y1="1.778" x2="-1.016" y2="0" width="0.254" layer="94"/> +<wire x1="-1.016" y1="0" x2="-1.016" y2="-1.778" width="0.254" layer="94"/> +<wire x1="1.016" y1="1.778" x2="1.016" y2="0" width="0.254" layer="94"/> +<wire x1="1.016" y1="0" x2="1.016" y2="-1.778" width="0.254" layer="94"/> +<wire x1="-2.54" y1="0" x2="-1.016" y2="0" width="0.254" layer="94"/> +<wire x1="2.54" y1="0" x2="1.016" y2="0" width="0.254" layer="94"/> +<text x="-2.54" y="2.54" size="1.27" layer="95">>NAME</text> +<text x="-2.54" y="-3.81" size="1.27" layer="96">>VALUE</text> +<pin name="1" x="-2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1"/> +<pin name="2" x="2.54" y="0" visible="off" length="point" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="FERRITE" prefix="FB" uservalue="yes"> +<description><p><b>Ferrite Bead</b></p> +<p>0603</p> +<ul> +<li>MMZ1608B121C - 120 Ohm @ 100MHz, 600mA, 0.15 Ohm DC Resistance - Digikey: 445-2164-1-ND</li> +<li>BK1608HW121-T - 120 Ohm, 600mA Ferrite Chip - Digikey: 587-1876-2-ND</li> +</ul> +<p>0805</p> +<ul> +<li>HZ0805B272R-10 - 2.7K Ohm @ 100MHz, 200mA, 0.8 Ohm DC Resistance - Digikey: 240-2504-1-ND (see also Murata BLM21BD272SN1L)</li> +<li>MMZ2012Y152B - 1.5K Ohm @ 100MHz, 500mA, 0.4 Ohm DC Resistance - Digikey: 445-1560-1-ND - Mainly for high frequency (80-400MHz)</li> +<li>MMZ2012R102A - 1K Ohm @ 100MHz, 500mA, 0.3 Ohm DC Resistance - Digikey: 445-1555-2-ND - More general purpose (10-200MHz)</li> +</ul></description> +<gates> +<gate name="G$1" symbol="FERRITE" x="0" y="0"/> +</gates> +<devices> +<device name="" package="0603"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402" package="_0402"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402MP" package="_0402MP"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603" package="_0603"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603MP" package="_0603MP"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805" package="_0805"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805MP" package="_0805MP"> +<connects> +<connect gate="G$1" pin="P$1" pad="1"/> +<connect gate="G$1" pin="P$2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="CRYSTAL" prefix="Y" uservalue="yes"> +<description><p><b>Crystals</b></p> + +<p><b>HC49UP</b> - Surface Mount Crystal +<ul> +<li>4.0MHz 18pF +/-30ppm Surface Mount Crystal [Digikey: 535-9857-1-ND]</li> +<li>12.0 MHz Surface Mount Crystal [Digikey: 535-9869-6-ND]</li> +<li>25.0 MHz Surface Mount Crystal [Digikey: 535-9078-1-ND]</li> +</ul> + +<p><b>2.5 x 2.0mm</b> - MEMs SMT Crystal +<ul> +<li>16.0 MHz 10pF 20ppm 2.5 x 2.0mm Crystal [Digikey -40-85°C: 535-10923-1-ND]</li> +</ul> + +<p><b>3.2 x 2.5mm</b> - MEMs SMT Crystal +<ul> +<li>12.0 MHz 8pF 15ppm 3.2 x 2.5mm Crystal [Digikey: <b>-10-70°C</b>: 644-1047-1-ND <b>-40-125°C</b>: 644-1128-1-ND]</li> +<li>16.0 MHz 8pF 15ppm 3.2 x 2.5mm Crystal [Digikey: <b>-10-70°C</b>: 644-1049-1-ND <b>-40-125°C</b>: 644-1129-2-ND]</li> +<li>16.0 MHz 10pF 10ppm 3.2 x 2.5mm Crystal [Digikey: 644-1100-1-ND]</li> +<li>27.12 MHz 18pF 30ppm 3.2 x 2.5mm Crystal [Digikey: 887-1424-1-ND]</li> +<li>27.12MHz 10pF 10ppm 3.2 x 2.5mm Crystal [Digikey: 887-1329-1-ND]</li> +</ul> + +<p><b>4.9 x 1.8mm</b> - MEMs SMT Crystal +<ul> +<li>32.768 KHz 12.5pF 20ppm 4.9 x 1.8mm Crystal [Digikey: SE2415CT-ND]</li> +</ul> + +<p><b>8.0 x 3.8mm</b></p> - Surface Mount Crystal +<ul> +<li>32.768kHz 12.5pF 20ppm -40°C-85°C [Digikey: 535-9166-2-ND]</li> +</ul> + +<p><b>Cylinder</b> +<ul> +<li>32.768KHz Cylinder Crystal (2x6mm body) [Ex. Digikey: 300-8341-2-ND]</li> +</ul> +</p> + +</p></description> +<gates> +<gate name="G$1" symbol="CRYSTAL" x="0" y="0"/> +</gates> +<devices> +<device name="SMD" package="HC49UP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="32.768" package="CRYSTAL_CYL_2X6MM_SMT"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="THIN" package="CRYSTAL_3.2X2.5"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="THIN32K" package="CRYSTAL_4.9X1.8"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="8X3.8SMT" package="CRYSTAL_8X3.8"> +<connects> +<connect gate="G$1" pin="1" pad="P$1"/> +<connect gate="G$1" pin="2" pad="P$4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="2.5X2.0MM" package="CRYSTAL_2.5X2"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="transistor-npn"> +<description><b>NPN Transistors</b><p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="SOT23-BEC"> +<description>TO-236 ITT Intermetall</description> +<wire x1="1.4224" y1="0.6604" x2="1.4224" y2="-0.6604" width="0.127" layer="51"/> +<wire x1="1.4224" y1="-0.6604" x2="-1.4224" y2="-0.6604" width="0.127" layer="51"/> +<wire x1="-1.4224" y1="-0.6604" x2="-1.4224" y2="0.6604" width="0.127" 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name="OC_FARNELL" value="1909661" constant="no"/> +<attribute name="OC_NEWARK" value="58T2488" constant="no"/> +<attribute name="PACKAGE" value="Frame_THT" constant="no"/> +<attribute name="SUPPLIER" value="Wuerth Elektronik" constant="no"/> +</technology> +</technologies> +</device> +<device name="_36503305" package="WE-SHC_36503305"> +<connects> +<connect gate="G$1" pin="GND" pad="1"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="36503305" constant="no"/> +<attribute name="OC_FARNELL" value="1909664" constant="no"/> +<attribute name="OC_NEWARK" value="58T2489" constant="no"/> +<attribute name="PACKAGE" value="Frame_THT" constant="no"/> +<attribute name="SUPPLIER" value="Wuerth Elektronik" constant="no"/> +</technology> +</technologies> +</device> +<device name="_36503505" package="WE-SHC_36503505"> +<connects> +<connect gate="G$1" pin="GND" pad="1"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="36503505" constant="no"/> +<attribute name="OC_FARNELL" value="1909668" constant="no"/> +<attribute name="OC_NEWARK" value="58T2490" constant="no"/> +<attribute name="PACKAGE" value="Frame_THT" constant="no"/> +<attribute name="SUPPLIER" value="Wuerth Elektronik" constant="no"/> +</technology> +</technologies> +</device> +<device name="_36503605" package="WE-SHC_36503605"> +<connects> +<connect gate="G$1" pin="GND" pad="1"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="36503605" constant="no"/> +<attribute name="OC_FARNELL" value="1909671" constant="no"/> +<attribute name="OC_NEWARK" value="58T2491" constant="no"/> +<attribute name="PACKAGE" value="Frame_THT" constant="no"/> +<attribute name="SUPPLIER" value="Wuerth Elektronik" constant="no"/> +</technology> +</technologies> +</device> +<device name="" package="WE-SHC_36103205_NO_CREAM"> +<connects> +<connect gate="G$1" pin="GND" pad="1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16"/> +</connects> +<technologies> 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BAT54.pdf</description> +<gates> +<gate name="G$1" symbol="SCHOTTKY" x="0" y="0"/> +</gates> +<devices> +<device name="" package="SOT23"> +<connects> +<connect gate="G$1" pin="A" pad="1"/> +<connect gate="G$1" pin="C" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="SparkFun-Connectors"> +<description><h3>SparkFun Electronics' preferred foot prints</h3> +In this library you'll find connectors and sockets- basically anything that can be plugged into or onto.<br><br> +We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. +<br><br> +<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ +<br><br> +You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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Because they are alternating, it causes a "brace" +to hold the component in place. 0.005 has proven to be the perfect amount of "off-center" position when using our standard breakaway headers. +Although looks a little odd when you look at the bare footprint, once you have a header in there, the alteration is very hard to notice. Also, +if you push a header all the way into place, it is covered up entirely on the bottom side. This idea of altering the position of holes to aid alignment +will be further integrated into the Sparkfun Library for other footprints. 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swaplevel="1" rot="R180"/> +</symbol> +<symbol name="POWERJACK"> +<wire x1="-10.16" y1="2.54" x2="-7.62" y2="5.08" width="0.1524" layer="94"/> +<wire x1="-7.62" y1="5.08" x2="-5.08" y2="2.54" width="0.1524" layer="94"/> +<wire x1="-5.08" y1="2.54" x2="-2.54" y2="2.54" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="2.54" x2="0" y2="2.54" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="2.54" x2="-2.54" y2="5.08" width="0.1524" layer="94"/> +<wire x1="-2.54" y1="5.08" x2="0" y2="5.08" width="0.1524" layer="94"/> +<text x="-10.16" y="10.16" size="1.778" layer="96">>Value</text> +<text x="-10.16" y="0" size="1.778" layer="95">>Name</text> +<rectangle x1="-10.16" y1="6.858" x2="0" y2="8.382" layer="94"/> +<pin name="GNDBREAK" x="2.54" y="5.08" visible="off" length="short" rot="R180"/> +<pin name="GND" x="2.54" y="2.54" visible="off" length="short" rot="R180"/> +<pin name="PWR" x="2.54" y="7.62" visible="off" length="short" rot="R180"/> +</symbol> +<symbol name="M03X2"> +<wire x1="-5.08" y1="5.08" x2="5.08" y2="5.08" width="0.254" layer="94"/> +<wire x1="5.08" y1="5.08" x2="5.08" y2="2.54" width="0.254" layer="94"/> +<wire x1="5.08" y1="2.54" x2="5.08" y2="0" width="0.254" layer="94"/> +<wire x1="5.08" y1="0" x2="5.08" y2="-2.54" width="0.254" layer="94"/> +<wire x1="5.08" y1="-2.54" x2="5.08" y2="-5.08" width="0.254" layer="94"/> +<wire x1="5.08" y1="-5.08" x2="-5.08" y2="-5.08" width="0.254" layer="94"/> +<wire x1="-5.08" y1="-5.08" x2="-5.08" y2="-2.54" width="0.254" layer="94"/> +<pin name="1" x="-7.62" y="2.54" visible="off" length="short"/> +<pin name="3" x="-7.62" y="0" visible="off" length="short"/> +<pin name="5" x="-7.62" y="-2.54" visible="off" length="short"/> +<pin name="6" x="7.62" y="-2.54" visible="off" length="short" rot="R180"/> +<pin name="4" x="7.62" y="0" visible="off" length="short" rot="R180"/> +<pin name="2" x="7.62" y="2.54" visible="off" length="short" rot="R180"/> +<text x="-5.08" y="5.588" size="1.27" layer="95">>NAME</text> +<text x="-5.08" y="-7.112" size="1.27" layer="96">>VALUE</text> +<circle x="-1.778" y="2.54" radius="1.016" width="0.1524" layer="94"/> +<circle x="1.778" y="2.54" radius="1.016" width="0.1524" layer="94"/> +<circle x="1.778" y="0" radius="1.016" width="0.1524" layer="94"/> +<circle x="1.778" y="-2.54" radius="1.016" width="0.1524" layer="94"/> +<circle x="-1.778" y="-2.54" radius="1.016" width="0.1524" layer="94"/> +<circle x="-1.778" y="0" radius="1.016" width="0.1524" layer="94"/> +<wire x1="-5.08" y1="-2.54" x2="-5.08" y2="0" width="0.254" layer="94"/> +<wire x1="-5.08" y1="0" x2="-5.08" y2="2.54" width="0.254" layer="94"/> +<wire x1="-5.08" y1="2.54" x2="-5.08" y2="5.08" width="0.254" layer="94"/> +<wire x1="-5.08" y1="2.54" x2="-2.794" y2="2.54" width="0.1524" layer="94"/> +<wire x1="-5.08" y1="0" x2="-2.794" y2="0" width="0.1524" layer="94"/> +<wire x1="-5.08" y1="-2.54" x2="-2.794" y2="-2.54" width="0.1524" layer="94"/> +<wire x1="5.08" y1="-2.54" x2="2.794" y2="-2.54" width="0.1524" layer="94"/> +<wire x1="5.08" y1="0" x2="2.794" y2="0" width="0.1524" layer="94"/> +<wire x1="5.08" y1="2.54" x2="2.794" y2="2.54" width="0.1524" layer="94"/> +<text x="-4.318" y="2.794" size="1.4224" layer="95">1</text> +<text x="3.302" y="2.794" size="1.4224" layer="95">2</text> +<text x="-4.318" y="0.254" size="1.4224" layer="95">3</text> +<text x="3.302" y="0.254" size="1.4224" layer="95">4</text> +<text x="-4.318" y="-2.286" size="1.4224" layer="95">5</text> +<text x="3.302" y="-2.286" size="1.4224" layer="95">6</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="M03" prefix="J" uservalue="yes"> +<description><b>Header 3</b> +Standard 3-pin 0.1" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings.</description> +<gates> +<gate name="J$1" symbol="M03" x="-2.54" y="0"/> +</gates> +<devices> +<device name="PTH" package="1X03"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="POLAR" package="MOLEX-1X3"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SCREW" package="SCREWTERMINAL-3.5MM-3"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08288" constant="no"/> +</technology> +</technologies> +</device> +<device name="LOCK" package="1X03_LOCK"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LOCK_LONGPADS" package="1X03_LOCK_LONGPADS"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="POLAR_LOCK" package="MOLEX-1X3_LOCK"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SCREW_LOCK" package="SCREWTERMINAL-3.5MM-3_LOCK.007S"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08288" constant="no"/> +</technology> +</technologies> +</device> +<device name="1X03_NO_SILK" package="1X03_NO_SILK"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LONGPADS" package="1X03_LONGPADS"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="JST-PTH" package="JST-3-PTH"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="SKU" value="PRT-09915" constant="no"/> +</technology> +</technologies> +</device> +<device name="POGO_PIN_HOLES_ONLY" package="1X03_PP_HOLES_ONLY"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-SCREW-5MM" package="SCREWTERMINAL-5MM-3"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="STOREFRONT_ID" value="PRT-08433" constant="no"/> +</technology> +</technologies> +</device> +<device name="LOCK_NO_SILK" package="1X03_LOCK_NO_SILK"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="JST-SMD" package="JST-3-SMD"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-12591" constant="no"/> +<attribute name="VALUE" value="3-PIN SMD" constant="no"/> +</technology> +</technologies> +</device> +<device name="SMD" package="1X03-1MM-RA"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD_RA_FEMALE" package="1X03_SMD_RA_FEMALE"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-10926"/> +<attribute name="VALUE" value="1x3 RA Female .1""/> +</technology> +</technologies> +</device> +<device name="SMD_RA_MALE" package="1X03_SMD_RA_MALE"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-10925"/> +</technology> +</technologies> +</device> +<device name="SMD_RA_MALE_POST" package="1X03_SMD_RA_MALE_POST"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="JST-PTH-VERT" package="JST-3-PTH-VERT"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1X03_SMD_RA_MALE_POST_SMALLER" package="1X03_SMD_RA_MALE_POST_SMALLER"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1X03_SMD_RA_MALE_POST_SMALLEST" package="1X03_SMD_RA_MALE_POST_SMALLEST"> +<connects> +<connect gate="J$1" pin="1" pad="1"/> +<connect gate="J$1" pin="2" pad="2"/> +<connect gate="J$1" pin="3" pad="3"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="AVR_SPI_PRG_6" prefix="J"> +<description><b>AVR ISP 6 Pin</b> +This is the reduced ISP connector for AVR programming. Common on Arduino. This footprint will take up less PCB space and can be used with a 10-pin to 6-pin adapter such as SKU: BOB-08508 + +<b>**Special note about "TEST_POINT" package.</b> The stop mask is on the top side, so if you want your programming test points to be on the bottom of your board, make sure to place this package on the bottom side of the board. This also ensure that the orientation to program from the bottom side will be correct.</description> +<gates> +<gate name="G$1" symbol="AVR_SPI_PROGRAMMER_6" x="0" y="0"/> +</gates> +<devices> +<device name="PTH" package="2X3"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="NS" package="2X3-NS"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="OFFSET_PADS" package="2X3_OFFSET"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="2X3_LOCK" package="2X3_LOCK"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="TESTPOINTS" package="2X3_TEST_POINTS"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="M10" prefix="J" uservalue="yes"> +<description><b>Header 10</b> +Standard 10-pin 0.1" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115).</description> +<gates> +<gate name="G$1" symbol="M10" x="0" y="7.62"/> +</gates> +<devices> +<device name="SILK_FEMALE_PTH" package="1X10"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11563"/> +</technology> +</technologies> +</device> +<device name="2MM" package="1X10-2MM"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="2MMSMD" package="1X10-2MM-SMD"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LOCK" package="1X10_LOCK"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LOCK_LONGPADS" package="1X10_LOCK_LONGPADS"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMD_COMBO-FEMALE" package="1X10_SMD_COMBINED"> +<connects> +<connect gate="G$1" pin="1" pad="1A 1B"/> +<connect gate="G$1" pin="10" pad="10A 10B"/> +<connect gate="G$1" pin="2" pad="2A 2B"/> +<connect gate="G$1" pin="3" pad="3A 3B"/> +<connect gate="G$1" pin="4" pad="4A 4B"/> +<connect gate="G$1" pin="5" pad="5A 5B"/> +<connect gate="G$1" pin="6" pad="6A 6B"/> +<connect gate="G$1" pin="7" pad="7A 7B"/> +<connect gate="G$1" pin="8" pad="8A 8B"/> +<connect gate="G$1" pin="9" pad="9A 9B"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11219"/> +</technology> +</technologies> +</device> +<device name="SMD_MALE" package="1X10_SMD_MALE"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11291"/> +</technology> +</technologies> +</device> +<device name="NO_SILK_PTH_FEMALE" package="1X10_NO_SILK"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="10" pad="10"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +<connect gate="G$1" pin="7" pad="7"/> +<connect gate="G$1" pin="8" pad="8"/> +<connect gate="G$1" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11563"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="POWER_JACK" prefix="J"> +<description><b>Power Jack</b> +This is the standard 5.5mm barrel jack for power.<br> +The PTH is the most common, proven, reliable, footprint.<br> +The Slot footprint only works if the mill layer is transmitted to the PCB fab house so be warned.<br> + +Mating wall wart : TOL-00298 (and others)</description> +<gates> +<gate name="G$1" symbol="POWERJACK" x="7.62" y="-2.54"/> +</gates> +<devices> +<device name="SMD" package="POWER_JACK_SMD"> +<connects> +<connect gate="G$1" pin="GND" pad="P$4"/> +<connect gate="G$1" pin="GNDBREAK" pad="GND"/> +<connect gate="G$1" pin="PWR" pad="VIN0"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08106"/> +<attribute name="SF_ID" value="PRT-12748" constant="no"/> +<attribute name="VALUE" value="5.5x2.1mm Barrel" constant="no"/> +</technology> +</technologies> +</device> +<device name="SLT" package="POWER_JACK_SLOT"> +<connects> +<connect gate="G$1" pin="GND" pad="GND@2"/> +<connect gate="G$1" pin="GNDBREAK" pad="GND@1"/> +<connect gate="G$1" pin="PWR" pad="PWR"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="PRT-00119" constant="no"/> +</technology> +</technologies> +</device> +<device name="PTH" package="POWER_JACK_PTH"> +<connects> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="GNDBREAK" pad="GNDBREAK"/> +<connect gate="G$1" pin="PWR" pad="PWR"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08197"/> +</technology> +</technologies> +</device> +<device name="COMBO" package="POWER_JACK_COMBO"> +<connects> +<connect gate="G$1" pin="GND" pad="GND@1"/> +<connect gate="G$1" pin="GNDBREAK" pad="GND"/> +<connect gate="G$1" pin="PWR" pad="POWER"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="PTH_LOCK" package="POWER_JACK_PTH_LOCK"> +<connects> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="GNDBREAK" pad="GNDBREAK"/> +<connect gate="G$1" pin="PWR" pad="PWR"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08197" constant="no"/> +<attribute name="SF_ID" value="PRT-00119" constant="no"/> +</technology> +</technologies> +</device> +<device name="1" package="POWER_JACK_SMD_OVERPASTE_REDBOARD_0603"> +<connects> +<connect gate="G$1" pin="GND" pad="P$4"/> +<connect gate="G$1" pin="GNDBREAK" pad="GND"/> +<connect gate="G$1" pin="PWR" pad="VIN0"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="TOE" package="POWER_JACK_SMD_OVERPASTE_TOE"> +<connects> +<connect gate="G$1" pin="GND" pad="P$4"/> +<connect gate="G$1" pin="GNDBREAK" pad="GND"/> +<connect gate="G$1" pin="PWR" pad="VIN0"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-08106" constant="no"/> +<attribute name="SF_ID" value="PRT-12748" constant="no"/> +</technology> +</technologies> +</device> +<device name="PTH_BREAD" package="POWER_JACK_PTH_BREAD"> +<connects> +<connect gate="G$1" pin="GND" pad="GND"/> +<connect gate="G$1" pin="GNDBREAK" pad="GNDBREAK"/> +<connect gate="G$1" pin="PWR" pad="PWR"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="PRT-10811" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="M03X2" prefix="J" uservalue="yes"> +<description>2x3 .1" header.<br> +Shrouded, with keying- CONN-10681<br> +SMT- CONN-11415<br> +Pogo pins- HW-11044</description> +<gates> +<gate name="G$1" symbol="M03X2" x="0" y="0"/> +</gates> +<devices> +<device name="SHROUD" package="2X3-SHROUDED"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-10681"/> +</technology> +</technologies> +</device> +<device name="SMT" package="2X3_SMT_POSTS"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11415"/> +</technology> +</technologies> +</device> +<device name="POGO_PINS" package="2X3_POGO"> +<connects> +<connect gate="G$1" pin="1" pad="P$1"/> +<connect gate="G$1" pin="2" pad="P$2"/> +<connect gate="G$1" pin="3" pad="P$3"/> +<connect gate="G$1" pin="4" pad="P$4"/> +<connect gate="G$1" pin="5" pad="P$5"/> +<connect gate="G$1" pin="6" pad="P$6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="HW-11044"/> +</technology> +</technologies> +</device> +<device name="2X3_SILK_MALE_PTH" package="2X3"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-09701"/> +</technology> +</technologies> +</device> +<device name="NO_SILK" package="2X3-NS"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="FEMALE_SMD" package="2X3_SMD"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11290"/> +</technology> +</technologies> +</device> +<device name="" package="2X3_SMD"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11290" constant="no"/> +</technology> +</technologies> +</device> +<device name="FEMALE" package="2X3"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +<connect gate="G$1" pin="3" pad="3"/> +<connect gate="G$1" pin="4" pad="4"/> +<connect gate="G$1" pin="5" pad="5"/> +<connect gate="G$1" pin="6" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="PROD_ID" value="CONN-11566"/> +<attribute name="VALUE" value="FEMALE 2x3"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="Panasonic-EXB-ERJ"> +<description><b> Developed By element14 </b><p> + +For feedback and Technical support please contact reach from below: +<br> Tech Support e-mail : <a href="mailto:CAD_Tech@element14.com">CAD_Tech@element14.com</a> +<br>Community website: <a href=http://www.element14.com/community/community/knode/cad_tools/cadsoft_eagle/eagle_cad_libraries> +EAGLE CAD Libraries on element14</a></description> +<packages> +<package name="RESCAXE80P320X160X60-8N"> +<smd name="1" x="-0.762" y="1.524" dx="0.8636" dy="0.9652" layer="1"/> +<smd name="2" x="-0.762" y="0.4318" dx="0.8636" dy="0.4572" layer="1"/> +<smd name="3" x="-0.762" y="-0.4318" dx="0.8636" dy="0.4572" layer="1"/> +<smd name="4" x="-0.762" y="-1.524" dx="0.8636" dy="0.9652" layer="1"/> +<smd name="5" x="0.762" y="-1.524" dx="0.8636" dy="0.9652" layer="1"/> +<smd name="6" x="0.762" y="-0.4318" dx="0.8636" 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rot="R180"/> +<pin name="GND@71" x="5.08" y="-15.24" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@72" x="5.08" y="-17.78" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@73" x="5.08" y="-20.32" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@74" x="5.08" y="-22.86" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@75" x="5.08" y="-25.4" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@76" x="5.08" y="-27.94" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@77" x="5.08" y="-30.48" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@78" x="5.08" y="-33.02" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@79" x="5.08" y="-35.56" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@80" x="5.08" y="-38.1" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@81" x="5.08" y="-40.64" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@82" x="5.08" y="-43.18" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@83" x="5.08" y="-45.72" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@84" x="5.08" y="-48.26" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@85" x="5.08" y="-50.8" length="middle" direction="pwr" rot="R180"/> +<pin name="GND@86" x="5.08" y="-53.34" length="middle" direction="pwr" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_MGTAVCC"> +<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/> +<wire x1="0" y1="7.62" x2="0" y2="-7.62" width="0.254" layer="94"/> +<wire x1="0" y1="-7.62" x2="-10.16" y2="-7.62" width="0.254" layer="94"/> +<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-10.16" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="MGTAVCC@0" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/> +<pin name="MGTAVCC@1" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/> +<pin name="MGTAVCC@2" x="5.08" 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x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/> +<pin name="MGTAVTT@5" x="5.08" y="-7.62" length="middle" direction="in" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_TDIODE"> +<wire x1="-10.16" y1="2.54" x2="0" y2="2.54" width="0.254" layer="94"/> +<wire x1="0" y1="2.54" x2="0" y2="-5.08" width="0.254" layer="94"/> +<wire x1="0" y1="-5.08" x2="-10.16" y2="-5.08" width="0.254" layer="94"/> +<text x="0" y="3.302" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-7.62" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="DXP_0" x="5.08" y="0" length="middle" rot="R180"/> +<pin name="DXN_0" x="5.08" y="-2.54" length="middle" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_VCCAUX"> +<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/> +<wire x1="0" y1="7.62" x2="0" y2="-7.62" width="0.254" layer="94"/> +<wire x1="0" y1="-7.62" x2="-10.16" y2="-7.62" width="0.254" layer="94"/> +<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-10.16" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="VCCAUX@0" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/> +<pin name="VCCAUX@1" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/> +<pin name="VCCAUX@2" x="5.08" y="0" length="middle" direction="in" rot="R180"/> +<pin name="VCCAUX@3" x="5.08" y="-2.54" length="middle" direction="in" rot="R180"/> +<pin name="VCCAUX@4" x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_VCCBRAM"> +<wire x1="-10.16" y1="5.08" x2="0" y2="5.08" width="0.254" layer="94"/> +<wire x1="0" y1="5.08" x2="0" y2="-5.08" width="0.254" layer="94"/> +<wire x1="0" y1="-5.08" x2="-10.16" y2="-5.08" width="0.254" layer="94"/> +<text x="0" y="5.842" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-7.62" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="VCCBRAM@0" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/> +<pin name="VCCBRAM@1" x="5.08" y="0" length="middle" direction="in" rot="R180"/> +<pin name="VCCBRAM@2" x="5.08" y="-2.54" length="middle" direction="in" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_VCCINT"> +<wire x1="-10.16" y1="17.78" x2="0" y2="17.78" width="0.254" layer="94"/> +<wire x1="0" y1="17.78" x2="0" y2="-20.32" width="0.254" layer="94"/> +<wire x1="0" y1="-20.32" x2="-10.16" y2="-20.32" width="0.254" layer="94"/> +<text x="0" y="18.542" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-22.86" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="VCCINT@0" x="5.08" y="15.24" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@1" x="5.08" y="12.7" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@2" x="5.08" y="10.16" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@3" x="5.08" y="7.62" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@4" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@5" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@6" x="5.08" y="0" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@7" x="5.08" y="-2.54" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@8" x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@9" x="5.08" y="-7.62" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@10" x="5.08" y="-10.16" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@11" x="5.08" y="-12.7" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@12" x="5.08" y="-15.24" length="middle" direction="in" rot="R180"/> +<pin name="VCCINT@13" x="5.08" y="-17.78" length="middle" direction="in" rot="R180"/> +</symbol> +<symbol name="XC7A200TFBG484_XADC"> +<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/> +<wire x1="0" y1="7.62" x2="0" y2="-10.16" width="0.254" layer="94"/> +<wire x1="0" y1="-10.16" x2="-10.16" y2="-10.16" width="0.254" layer="94"/> +<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">>NAME</text> +<text x="0" y="-12.7" size="1.778" layer="96" rot="MR0">>VALUE</text> +<pin name="VCCADC_0" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/> +<pin name="VP_0" x="5.08" y="2.54" length="middle" rot="R180"/> +<pin name="VN_0" x="5.08" y="0" length="middle" rot="R180"/> +<pin name="VREFP_0" x="5.08" y="-2.54" length="middle" rot="R180"/> +<pin name="VREFN_0" x="5.08" y="-5.08" length="middle" rot="R180"/> +<pin name="GNDADC_0" x="5.08" y="-7.62" length="middle" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="XC7A200TFBG484" prefix="U"> +<description>Xilinx FPGA: XC7A200TFBG484</description> +<gates> +<gate name="B0" symbol="XC7A200TFBG484_0" x="0" y="0"/> +<gate name="B13" symbol="XC7A200TFBG484_13" x="45.72" y="0"/> +<gate name="B14" symbol="XC7A200TFBG484_14" x="91.44" y="0"/> +<gate name="B15" symbol="XC7A200TFBG484_15" x="137.16" y="0"/> +<gate name="B16" symbol="XC7A200TFBG484_16" x="182.88" y="0"/> +<gate name="B34" symbol="XC7A200TFBG484_34" x="228.6" y="0"/> +<gate name="B35" symbol="XC7A200TFBG484_35" x="274.32" y="0"/> +<gate name="B216" symbol="XC7A200TFBG484_216" x="320.04" y="0"/> +<gate name="BGNDA" symbol="XC7A200TFBG484_GNDA" x="365.76" y="0"/> +<gate name="BGNDB" symbol="XC7A200TFBG484_GNDB" x="411.48" y="0"/> +<gate name="BMGTAVCC" symbol="XC7A200TFBG484_MGTAVCC" x="457.2" y="0"/> +<gate name="BMGTAVTT" symbol="XC7A200TFBG484_MGTAVTT" x="502.92" y="0"/> +<gate name="BTDIODE" symbol="XC7A200TFBG484_TDIODE" x="548.64" y="0"/> +<gate name="BVCCAUX" symbol="XC7A200TFBG484_VCCAUX" x="594.36" y="0"/> +<gate name="BVCCBRAM" symbol="XC7A200TFBG484_VCCBRAM" x="640.08" y="0"/> +<gate name="BVCCINT" symbol="XC7A200TFBG484_VCCINT" x="685.8" y="0"/> +<gate name="BXADC" symbol="XC7A200TFBG484_XADC" x="731.52" y="0"/> +</gates> +<devices> +<device name="" package="FF484"> +<connects> +<connect gate="B0" pin="CCLK_0" pad="L12"/> +<connect gate="B0" pin="CFGBVS_0" pad="U8"/> +<connect gate="B0" pin="DONE_0" pad="G11"/> +<connect gate="B0" pin="INIT_B_0" pad="U12"/> +<connect gate="B0" pin="M0_0" pad="U11"/> +<connect gate="B0" pin="M1_0" pad="U10"/> +<connect gate="B0" pin="M2_0" pad="U9"/> +<connect gate="B0" pin="PROGRAM_B_0" pad="N12"/> +<connect gate="B0" pin="TCK_0" pad="V12"/> +<connect gate="B0" pin="TDI_0" pad="R13"/> +<connect gate="B0" pin="TDO_0" pad="U13"/> +<connect gate="B0" pin="TMS_0" pad="T13"/> +<connect gate="B0" pin="VCCBATT_0" pad="E12"/> +<connect gate="B0" pin="VCCO_0@0" pad="F12"/> +<connect gate="B0" pin="VCCO_0@1" pad="T12"/> +<connect gate="B13" pin="IO_0_13" pad="Y17"/> +<connect gate="B13" pin="IO_L10N_T1_13" pad="W10"/> +<connect gate="B13" pin="IO_L10P_T1_13" pad="V10"/> +<connect gate="B13" pin="IO_L11N_T1_SRCC_13" pad="Y12"/> +<connect gate="B13" pin="IO_L11P_T1_SRCC_13" pad="Y11"/> +<connect gate="B13" pin="IO_L12N_T1_MRCC_13" pad="W12"/> +<connect gate="B13" pin="IO_L12P_T1_MRCC_13" pad="W11"/> +<connect gate="B13" pin="IO_L13N_T2_MRCC_13" pad="V14"/> +<connect gate="B13" pin="IO_L13P_T2_MRCC_13" pad="V13"/> +<connect gate="B13" pin="IO_L14N_T2_SRCC_13" pad="V15"/> +<connect gate="B13" pin="IO_L14P_T2_SRCC_13" pad="U15"/> +<connect gate="B13" pin="IO_L15N_T2_DQS_13" pad="T15"/> +<connect gate="B13" pin="IO_L15P_T2_DQS_13" pad="T14"/> +<connect gate="B13" pin="IO_L16N_T2_13" pad="W16"/> +<connect gate="B13" pin="IO_L16P_T2_13" pad="W15"/> +<connect gate="B13" pin="IO_L17N_T2_13" pad="U16"/> +<connect gate="B13" pin="IO_L17P_T2_13" pad="T16"/> +<connect gate="B13" pin="IO_L1N_T0_13" pad="AA16"/> +<connect gate="B13" pin="IO_L1P_T0_13" pad="Y16"/> +<connect gate="B13" pin="IO_L2N_T0_13" pad="AB17"/> +<connect gate="B13" pin="IO_L2P_T0_13" pad="AB16"/> +<connect gate="B13" pin="IO_L3N_T0_DQS_13" pad="AB13"/> +<connect gate="B13" pin="IO_L3P_T0_DQS_13" pad="AA13"/> +<connect gate="B13" pin="IO_L4N_T0_13" pad="AB15"/> +<connect gate="B13" pin="IO_L4P_T0_13" pad="AA15"/> +<connect gate="B13" pin="IO_L5N_T0_13" pad="AA14"/> +<connect gate="B13" pin="IO_L5P_T0_13" pad="Y13"/> +<connect gate="B13" pin="IO_L6N_T0_VREF_13" pad="Y14"/> +<connect gate="B13" pin="IO_L6P_T0_13" pad="W14"/> +<connect gate="B13" pin="IO_L7N_T1_13" pad="AB12"/> +<connect gate="B13" pin="IO_L7P_T1_13" pad="AB11"/> +<connect gate="B13" pin="IO_L8N_T1_13" pad="AB10"/> +<connect gate="B13" pin="IO_L8P_T1_13" pad="AA9"/> +<connect gate="B13" pin="IO_L9N_T1_DQS_13" pad="AA11"/> +<connect gate="B13" pin="IO_L9P_T1_DQS_13" pad="AA10"/> +<connect gate="B13" pin="VCCO_13@0" pad="V16"/> +<connect gate="B13" pin="VCCO_13@1" pad="W13"/> +<connect gate="B13" pin="VCCO_13@2" pad="Y10"/> +<connect gate="B13" pin="VCCO_13@3" pad="AA17"/> +<connect gate="B13" pin="VCCO_13@4" pad="AB14"/> +<connect gate="B14" pin="IO_0_14" pad="P20"/> +<connect gate="B14" pin="IO_25_14" pad="N15"/> +<connect gate="B14" pin="IO_L10N_T1_D15_14" pad="AB22"/> +<connect gate="B14" pin="IO_L10P_T1_D14_14" pad="AB21"/> +<connect gate="B14" pin="IO_L11N_T1_SRCC_14" pad="V20"/> +<connect gate="B14" pin="IO_L11P_T1_SRCC_14" pad="U20"/> +<connect gate="B14" pin="IO_L12N_T1_MRCC_14" pad="W20"/> +<connect gate="B14" pin="IO_L12P_T1_MRCC_14" pad="W19"/> +<connect gate="B14" pin="IO_L13N_T2_MRCC_14" pad="Y19"/> +<connect gate="B14" pin="IO_L13P_T2_MRCC_14" pad="Y18"/> +<connect gate="B14" pin="IO_L14N_T2_SRCC_14" pad="V19"/> +<connect gate="B14" pin="IO_L14P_T2_SRCC_14" pad="V18"/> +<connect gate="B14" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/> +<connect gate="B14" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/> +<connect gate="B14" pin="IO_L16N_T2_A15_D31_14" pad="W17"/> +<connect gate="B14" pin="IO_L16P_T2_CSI_B_14" pad="V17"/> +<connect gate="B14" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/> +<connect gate="B14" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/> +<connect gate="B14" pin="IO_L18N_T2_A11_D27_14" pad="U18"/> +<connect gate="B14" pin="IO_L18P_T2_A12_D28_14" pad="U17"/> +<connect gate="B14" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/> +<connect gate="B14" pin="IO_L19P_T3_A10_D26_14" pad="P14"/> +<connect gate="B14" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/> +<connect gate="B14" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/> +<connect gate="B14" pin="IO_L20N_T3_A07_D23_14" pad="T18"/> +<connect gate="B14" pin="IO_L20P_T3_A08_D24_14" pad="R18"/> +<connect gate="B14" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/> +<connect gate="B14" pin="IO_L21P_T3_DQS_14" pad="N17"/> +<connect gate="B14" pin="IO_L22N_T3_A04_D20_14" pad="R16"/> +<connect gate="B14" pin="IO_L22P_T3_A05_D21_14" pad="P15"/> +<connect gate="B14" pin="IO_L23N_T3_A02_D18_14" pad="N14"/> +<connect gate="B14" pin="IO_L23P_T3_A03_D19_14" pad="N13"/> +<connect gate="B14" pin="IO_L24N_T3_A00_D16_14" pad="R17"/> +<connect gate="B14" pin="IO_L24P_T3_A01_D17_14" pad="P16"/> +<connect gate="B14" pin="IO_L2N_T0_D03_14" pad="R21"/> +<connect gate="B14" pin="IO_L2P_T0_D02_14" pad="P21"/> +<connect gate="B14" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/> +<connect gate="B14" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/> +<connect gate="B14" pin="IO_L4N_T0_D05_14" pad="U21"/> +<connect gate="B14" pin="IO_L4P_T0_D04_14" pad="T21"/> +<connect gate="B14" pin="IO_L5N_T0_D07_14" pad="R19"/> +<connect gate="B14" pin="IO_L5P_T0_D06_14" pad="P19"/> +<connect gate="B14" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/> +<connect gate="B14" pin="IO_L6P_T0_FCS_B_14" pad="T19"/> +<connect gate="B14" pin="IO_L7N_T1_D10_14" pad="W22"/> +<connect gate="B14" pin="IO_L7P_T1_D09_14" pad="W21"/> +<connect gate="B14" pin="IO_L8N_T1_D12_14" pad="AA21"/> +<connect gate="B14" pin="IO_L8P_T1_D11_14" pad="AA20"/> +<connect gate="B14" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/> +<connect gate="B14" pin="IO_L9P_T1_DQS_14" pad="Y21"/> +<connect gate="B14" pin="VCCO_14@0" pad="M14"/> +<connect gate="B14" pin="VCCO_14@1" pad="P18"/> +<connect gate="B14" pin="VCCO_14@2" pad="R15"/> +<connect gate="B14" pin="VCCO_14@3" pad="T22"/> +<connect gate="B14" pin="VCCO_14@4" pad="U19"/> +<connect gate="B14" pin="VCCO_14@5" pad="Y20"/> +<connect gate="B15" pin="IO_0_15" pad="J16"/> +<connect gate="B15" pin="IO_25_15" pad="M17"/> +<connect gate="B15" pin="IO_L10N_T1_AD11N_15" pad="L21"/> +<connect gate="B15" pin="IO_L10P_T1_AD11P_15" pad="M21"/> +<connect gate="B15" pin="IO_L11N_T1_SRCC_15" pad="J21"/> +<connect gate="B15" pin="IO_L11P_T1_SRCC_15" pad="J20"/> +<connect gate="B15" pin="IO_L12N_T1_MRCC_15" pad="H19"/> +<connect gate="B15" pin="IO_L12P_T1_MRCC_15" pad="J19"/> +<connect gate="B15" pin="IO_L13N_T2_MRCC_15" pad="K19"/> +<connect gate="B15" pin="IO_L13P_T2_MRCC_15" pad="K18"/> +<connect gate="B15" pin="IO_L14N_T2_SRCC_15" pad="L20"/> +<connect gate="B15" pin="IO_L14P_T2_SRCC_15" pad="L19"/> +<connect gate="B15" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/> +<connect gate="B15" pin="IO_L15P_T2_DQS_15" pad="N22"/> +<connect gate="B15" pin="IO_L16N_T2_A27_15" pad="L18"/> +<connect gate="B15" pin="IO_L16P_T2_A28_15" pad="M18"/> +<connect gate="B15" pin="IO_L17N_T2_A25_15" pad="N19"/> +<connect gate="B15" pin="IO_L17P_T2_A26_15" pad="N18"/> +<connect gate="B15" pin="IO_L18N_T2_A23_15" pad="M20"/> +<connect gate="B15" pin="IO_L18P_T2_A24_15" pad="N20"/> +<connect gate="B15" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/> +<connect gate="B15" pin="IO_L19P_T3_A22_15" pad="K13"/> +<connect gate="B15" pin="IO_L1N_T0_AD0N_15" pad="G13"/> +<connect gate="B15" pin="IO_L1P_T0_AD0P_15" pad="H13"/> +<connect gate="B15" pin="IO_L20N_T3_A19_15" pad="L13"/> +<connect gate="B15" pin="IO_L20P_T3_A20_15" pad="M13"/> +<connect gate="B15" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/> +<connect gate="B15" pin="IO_L21P_T3_DQS_15" pad="K17"/> +<connect gate="B15" pin="IO_L22N_T3_A16_15" pad="L15"/> +<connect gate="B15" pin="IO_L22P_T3_A17_15" pad="L14"/> +<connect gate="B15" pin="IO_L23N_T3_FWE_B_15" pad="K16"/> +<connect gate="B15" pin="IO_L23P_T3_FOE_B_15" pad="L16"/> +<connect gate="B15" pin="IO_L24N_T3_RS0_15" pad="M16"/> +<connect gate="B15" pin="IO_L24P_T3_RS1_15" pad="M15"/> +<connect gate="B15" pin="IO_L2N_T0_AD8N_15" pad="G16"/> +<connect gate="B15" pin="IO_L2P_T0_AD8P_15" pad="G15"/> +<connect gate="B15" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/> +<connect gate="B15" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/> +<connect gate="B15" pin="IO_L4N_T0_15" pad="G18"/> +<connect gate="B15" pin="IO_L4P_T0_15" pad="G17"/> +<connect gate="B15" pin="IO_L5N_T0_AD9N_15" pad="H15"/> +<connect gate="B15" pin="IO_L5P_T0_AD9P_15" pad="J15"/> +<connect gate="B15" pin="IO_L6N_T0_VREF_15" pad="H18"/> +<connect gate="B15" pin="IO_L6P_T0_15" pad="H17"/> +<connect gate="B15" pin="IO_L7N_T1_AD2N_15" pad="H22"/> +<connect gate="B15" pin="IO_L7P_T1_AD2P_15" pad="J22"/> +<connect gate="B15" pin="IO_L8N_T1_AD10N_15" pad="G20"/> +<connect gate="B15" pin="IO_L8P_T1_AD10P_15" pad="H20"/> +<connect gate="B15" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/> +<connect gate="B15" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/> +<connect gate="B15" pin="VCCO_15@0" pad="G19"/> +<connect gate="B15" pin="VCCO_15@1" pad="H16"/> +<connect gate="B15" pin="VCCO_15@2" pad="J13"/> +<connect gate="B15" pin="VCCO_15@3" pad="K20"/> +<connect gate="B15" pin="VCCO_15@4" pad="L17"/> +<connect gate="B15" pin="VCCO_15@5" pad="N21"/> +<connect gate="B16" pin="IO_0_16" pad="F15"/> +<connect gate="B16" pin="IO_25_16" pad="F21"/> +<connect gate="B16" pin="IO_L10N_T1_16" pad="A14"/> +<connect gate="B16" pin="IO_L10P_T1_16" pad="A13"/> +<connect gate="B16" pin="IO_L11N_T1_SRCC_16" pad="B18"/> +<connect gate="B16" pin="IO_L11P_T1_SRCC_16" pad="B17"/> +<connect gate="B16" pin="IO_L12N_T1_MRCC_16" pad="C17"/> +<connect gate="B16" pin="IO_L12P_T1_MRCC_16" pad="D17"/> +<connect gate="B16" pin="IO_L13N_T2_MRCC_16" pad="C19"/> +<connect gate="B16" pin="IO_L13P_T2_MRCC_16" pad="C18"/> +<connect gate="B16" pin="IO_L14N_T2_SRCC_16" pad="D19"/> +<connect gate="B16" pin="IO_L14P_T2_SRCC_16" pad="E19"/> +<connect gate="B16" pin="IO_L15N_T2_DQS_16" pad="E18"/> +<connect gate="B16" pin="IO_L15P_T2_DQS_16" pad="F18"/> +<connect gate="B16" pin="IO_L16N_T2_16" pad="A20"/> +<connect gate="B16" pin="IO_L16P_T2_16" pad="B20"/> +<connect gate="B16" pin="IO_L17N_T2_16" pad="A19"/> +<connect gate="B16" pin="IO_L17P_T2_16" pad="A18"/> +<connect gate="B16" pin="IO_L18N_T2_16" pad="F20"/> +<connect gate="B16" pin="IO_L18P_T2_16" pad="F19"/> +<connect gate="B16" pin="IO_L19N_T3_VREF_16" pad="C20"/> +<connect gate="B16" pin="IO_L19P_T3_16" pad="D20"/> +<connect gate="B16" pin="IO_L1N_T0_16" pad="F14"/> +<connect gate="B16" pin="IO_L1P_T0_16" pad="F13"/> +<connect gate="B16" pin="IO_L20N_T3_16" pad="B22"/> +<connect gate="B16" pin="IO_L20P_T3_16" pad="C22"/> +<connect gate="B16" pin="IO_L21N_T3_DQS_16" pad="A21"/> +<connect gate="B16" pin="IO_L21P_T3_DQS_16" pad="B21"/> +<connect gate="B16" pin="IO_L22N_T3_16" pad="D22"/> +<connect gate="B16" pin="IO_L22P_T3_16" pad="E22"/> +<connect gate="B16" pin="IO_L23N_T3_16" pad="D21"/> +<connect gate="B16" pin="IO_L23P_T3_16" pad="E21"/> +<connect gate="B16" pin="IO_L24N_T3_16" pad="G22"/> +<connect gate="B16" pin="IO_L24P_T3_16" pad="G21"/> +<connect gate="B16" pin="IO_L2N_T0_16" pad="E17"/> +<connect gate="B16" pin="IO_L2P_T0_16" pad="F16"/> +<connect gate="B16" pin="IO_L3N_T0_DQS_16" pad="C15"/> +<connect gate="B16" pin="IO_L3P_T0_DQS_16" pad="C14"/> +<connect gate="B16" pin="IO_L4N_T0_16" pad="E14"/> +<connect gate="B16" pin="IO_L4P_T0_16" pad="E13"/> +<connect gate="B16" pin="IO_L5N_T0_16" pad="D16"/> +<connect gate="B16" pin="IO_L5P_T0_16" pad="E16"/> +<connect gate="B16" pin="IO_L6N_T0_VREF_16" pad="D15"/> +<connect gate="B16" pin="IO_L6P_T0_16" pad="D14"/> +<connect gate="B16" pin="IO_L7N_T1_16" pad="B16"/> +<connect gate="B16" pin="IO_L7P_T1_16" pad="B15"/> +<connect gate="B16" pin="IO_L8N_T1_16" pad="B13"/> +<connect gate="B16" pin="IO_L8P_T1_16" pad="C13"/> +<connect gate="B16" pin="IO_L9N_T1_DQS_16" pad="A16"/> +<connect gate="B16" pin="IO_L9P_T1_DQS_16" pad="A15"/> +<connect gate="B16" pin="VCCO_16@0" pad="A17"/> +<connect gate="B16" pin="VCCO_16@1" pad="B14"/> +<connect gate="B16" pin="VCCO_16@2" pad="C21"/> +<connect gate="B16" pin="VCCO_16@3" pad="D18"/> +<connect gate="B16" pin="VCCO_16@4" pad="E15"/> +<connect gate="B16" pin="VCCO_16@5" pad="F22"/> +<connect gate="B216" pin="MGTPRXN0_216" pad="C11"/> +<connect gate="B216" pin="MGTPRXN1_216" pad="A10"/> +<connect gate="B216" pin="MGTPRXN2_216" pad="C9"/> +<connect gate="B216" pin="MGTPRXN3_216" pad="A8"/> +<connect gate="B216" pin="MGTPRXP0_216" pad="D11"/> +<connect gate="B216" pin="MGTPRXP1_216" pad="B10"/> +<connect gate="B216" pin="MGTPRXP2_216" pad="D9"/> +<connect gate="B216" pin="MGTPRXP3_216" pad="B8"/> +<connect gate="B216" pin="MGTPTXN0_216" pad="C7"/> +<connect gate="B216" pin="MGTPTXN1_216" pad="A6"/> +<connect gate="B216" pin="MGTPTXN2_216" pad="C5"/> +<connect gate="B216" pin="MGTPTXN3_216" pad="A4"/> +<connect gate="B216" pin="MGTPTXP0_216" pad="D7"/> +<connect gate="B216" pin="MGTPTXP1_216" pad="B6"/> +<connect gate="B216" pin="MGTPTXP2_216" pad="D5"/> +<connect gate="B216" pin="MGTPTXP3_216" pad="B4"/> +<connect gate="B216" pin="MGTREFCLK0N_216" pad="E10"/> +<connect gate="B216" pin="MGTREFCLK0P_216" pad="F10"/> +<connect gate="B216" pin="MGTREFCLK1N_216" pad="E6"/> +<connect gate="B216" pin="MGTREFCLK1P_216" pad="F6"/> +<connect gate="B216" pin="MGTRREF_216" pad="F8"/> +<connect gate="B34" pin="IO_0_34" pad="T3"/> +<connect gate="B34" pin="IO_25_34" pad="U7"/> +<connect gate="B34" pin="IO_L10N_T1_34" pad="AB5"/> +<connect gate="B34" pin="IO_L10P_T1_34" pad="AA5"/> +<connect gate="B34" pin="IO_L11N_T1_SRCC_34" pad="AA4"/> +<connect gate="B34" pin="IO_L11P_T1_SRCC_34" pad="Y4"/> +<connect gate="B34" pin="IO_L12N_T1_MRCC_34" pad="W4"/> +<connect gate="B34" pin="IO_L12P_T1_MRCC_34" pad="V4"/> +<connect gate="B34" pin="IO_L13N_T2_MRCC_34" pad="T4"/> +<connect gate="B34" pin="IO_L13P_T2_MRCC_34" pad="R4"/> +<connect gate="B34" pin="IO_L14N_T2_SRCC_34" pad="U5"/> +<connect gate="B34" pin="IO_L14P_T2_SRCC_34" pad="T5"/> +<connect gate="B34" pin="IO_L15N_T2_DQS_34" pad="W5"/> +<connect gate="B34" pin="IO_L15P_T2_DQS_34" pad="W6"/> +<connect gate="B34" pin="IO_L16N_T2_34" pad="V5"/> +<connect gate="B34" pin="IO_L16P_T2_34" pad="U6"/> +<connect gate="B34" pin="IO_L17N_T2_34" pad="T6"/> +<connect gate="B34" pin="IO_L17P_T2_34" pad="R6"/> +<connect gate="B34" pin="IO_L18N_T2_34" pad="AA6"/> +<connect gate="B34" pin="IO_L18P_T2_34" pad="Y6"/> +<connect gate="B34" pin="IO_L19N_T3_VREF_34" pad="W7"/> +<connect gate="B34" pin="IO_L19P_T3_34" pad="V7"/> +<connect gate="B34" pin="IO_L1N_T0_34" pad="U1"/> +<connect gate="B34" pin="IO_L1P_T0_34" pad="T1"/> +<connect gate="B34" pin="IO_L20N_T3_34" pad="AB6"/> +<connect gate="B34" pin="IO_L20P_T3_34" pad="AB7"/> +<connect gate="B34" pin="IO_L21N_T3_DQS_34" pad="V8"/> +<connect gate="B34" pin="IO_L21P_T3_DQS_34" pad="V9"/> +<connect gate="B34" pin="IO_L22N_T3_34" pad="AB8"/> +<connect gate="B34" pin="IO_L22P_T3_34" pad="AA8"/> +<connect gate="B34" pin="IO_L23N_T3_34" pad="Y7"/> +<connect gate="B34" pin="IO_L23P_T3_34" pad="Y8"/> +<connect gate="B34" pin="IO_L24N_T3_34" pad="Y9"/> +<connect gate="B34" pin="IO_L24P_T3_34" pad="W9"/> +<connect gate="B34" pin="IO_L2N_T0_34" pad="V2"/> +<connect gate="B34" pin="IO_L2P_T0_34" pad="U2"/> +<connect gate="B34" pin="IO_L3N_T0_DQS_34" pad="R2"/> +<connect gate="B34" pin="IO_L3P_T0_DQS_34" pad="R3"/> +<connect gate="B34" pin="IO_L4N_T0_34" pad="Y2"/> +<connect gate="B34" pin="IO_L4P_T0_34" pad="W2"/> +<connect gate="B34" pin="IO_L5N_T0_34" pad="Y1"/> +<connect gate="B34" pin="IO_L5P_T0_34" pad="W1"/> +<connect gate="B34" pin="IO_L6N_T0_VREF_34" pad="V3"/> +<connect gate="B34" pin="IO_L6P_T0_34" pad="U3"/> +<connect gate="B34" pin="IO_L7N_T1_34" pad="AB1"/> +<connect gate="B34" pin="IO_L7P_T1_34" pad="AA1"/> +<connect gate="B34" pin="IO_L8N_T1_34" pad="AB2"/> +<connect gate="B34" pin="IO_L8P_T1_34" pad="AB3"/> +<connect gate="B34" pin="IO_L9N_T1_DQS_34" pad="AA3"/> +<connect gate="B34" pin="IO_L9P_T1_DQS_34" pad="Y3"/> +<connect gate="B34" pin="VCCO_34@0" pad="R5"/> +<connect gate="B34" pin="VCCO_34@1" pad="T2"/> +<connect gate="B34" pin="VCCO_34@2" pad="V6"/> +<connect gate="B34" pin="VCCO_34@3" pad="W3"/> +<connect gate="B34" pin="VCCO_34@4" pad="AA7"/> +<connect gate="B34" pin="VCCO_34@5" pad="AB4"/> +<connect gate="B35" pin="IO_0_35" pad="F4"/> +<connect gate="B35" pin="IO_25_35" pad="L6"/> +<connect gate="B35" pin="IO_L10N_T1_AD15N_35" pad="H5"/> +<connect gate="B35" pin="IO_L10P_T1_AD15P_35" pad="J5"/> +<connect gate="B35" pin="IO_L11N_T1_SRCC_35" pad="G3"/> +<connect gate="B35" pin="IO_L11P_T1_SRCC_35" pad="H3"/> +<connect gate="B35" pin="IO_L12N_T1_MRCC_35" pad="G4"/> +<connect gate="B35" pin="IO_L12P_T1_MRCC_35" pad="H4"/> +<connect gate="B35" pin="IO_L13N_T2_MRCC_35" pad="J4"/> +<connect gate="B35" pin="IO_L13P_T2_MRCC_35" pad="K4"/> +<connect gate="B35" pin="IO_L14N_T2_SRCC_35" pad="K3"/> +<connect gate="B35" pin="IO_L14P_T2_SRCC_35" pad="L3"/> +<connect gate="B35" pin="IO_L15N_T2_DQS_35" pad="L1"/> +<connect gate="B35" pin="IO_L15P_T2_DQS_35" pad="M1"/> +<connect gate="B35" pin="IO_L16N_T2_35" pad="M2"/> +<connect gate="B35" pin="IO_L16P_T2_35" pad="M3"/> +<connect gate="B35" pin="IO_L17N_T2_35" pad="J6"/> +<connect gate="B35" pin="IO_L17P_T2_35" pad="K6"/> +<connect gate="B35" pin="IO_L18N_T2_35" pad="L4"/> +<connect gate="B35" pin="IO_L18P_T2_35" pad="L5"/> +<connect gate="B35" pin="IO_L19N_T3_VREF_35" pad="N3"/> +<connect gate="B35" pin="IO_L19P_T3_35" pad="N4"/> +<connect gate="B35" pin="IO_L1N_T0_AD4N_35" pad="A1"/> +<connect gate="B35" pin="IO_L1P_T0_AD4P_35" pad="B1"/> +<connect gate="B35" pin="IO_L20N_T3_35" pad="P1"/> +<connect gate="B35" pin="IO_L20P_T3_35" pad="R1"/> +<connect gate="B35" pin="IO_L21N_T3_DQS_35" pad="P4"/> +<connect gate="B35" pin="IO_L21P_T3_DQS_35" pad="P5"/> +<connect gate="B35" pin="IO_L22N_T3_35" pad="N2"/> +<connect gate="B35" pin="IO_L22P_T3_35" pad="P2"/> +<connect gate="B35" pin="IO_L23N_T3_35" pad="M5"/> +<connect gate="B35" pin="IO_L23P_T3_35" pad="M6"/> +<connect gate="B35" pin="IO_L24N_T3_35" pad="N5"/> +<connect gate="B35" pin="IO_L24P_T3_35" pad="P6"/> +<connect gate="B35" pin="IO_L2N_T0_AD12N_35" pad="B2"/> +<connect gate="B35" pin="IO_L2P_T0_AD12P_35" pad="C2"/> +<connect gate="B35" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/> +<connect gate="B35" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/> +<connect gate="B35" pin="IO_L4N_T0_35" pad="D2"/> +<connect gate="B35" pin="IO_L4P_T0_35" pad="E2"/> +<connect gate="B35" pin="IO_L5N_T0_AD13N_35" pad="F1"/> +<connect gate="B35" pin="IO_L5P_T0_AD13P_35" pad="G1"/> +<connect gate="B35" pin="IO_L6N_T0_VREF_35" pad="E3"/> +<connect gate="B35" pin="IO_L6P_T0_35" pad="F3"/> +<connect gate="B35" pin="IO_L7N_T1_AD6N_35" pad="J1"/> +<connect gate="B35" pin="IO_L7P_T1_AD6P_35" pad="K1"/> +<connect gate="B35" pin="IO_L8N_T1_AD14N_35" pad="G2"/> +<connect gate="B35" pin="IO_L8P_T1_AD14P_35" pad="H2"/> +<connect gate="B35" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/> +<connect gate="B35" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/> +<connect gate="B35" pin="VCCO_35@0" pad="C1"/> +<connect gate="B35" pin="VCCO_35@1" pad="F2"/> +<connect gate="B35" pin="VCCO_35@2" pad="H6"/> +<connect gate="B35" pin="VCCO_35@3" pad="J3"/> +<connect gate="B35" pin="VCCO_35@4" pad="M4"/> +<connect gate="B35" pin="VCCO_35@5" pad="N1"/> +<connect gate="BGNDA" pin="GND@0" pad="A2"/> +<connect gate="BGNDA" pin="GND@1" pad="A3"/> +<connect gate="BGNDA" pin="GND@10" pad="B19"/> +<connect gate="BGNDA" pin="GND@11" pad="C3"/> +<connect gate="BGNDA" pin="GND@12" pad="C6"/> +<connect gate="BGNDA" pin="GND@13" pad="C10"/> +<connect gate="BGNDA" pin="GND@14" pad="C12"/> +<connect gate="BGNDA" pin="GND@15" pad="C16"/> +<connect gate="BGNDA" pin="GND@16" pad="D3"/> +<connect gate="BGNDA" pin="GND@17" pad="D4"/> +<connect gate="BGNDA" pin="GND@18" pad="D8"/> +<connect gate="BGNDA" pin="GND@19" pad="D12"/> +<connect gate="BGNDA" pin="GND@2" pad="A5"/> +<connect gate="BGNDA" pin="GND@20" pad="D13"/> +<connect gate="BGNDA" pin="GND@21" pad="E4"/> +<connect gate="BGNDA" pin="GND@22" pad="E5"/> +<connect gate="BGNDA" pin="GND@23" pad="E7"/> +<connect gate="BGNDA" pin="GND@24" pad="E9"/> +<connect gate="BGNDA" pin="GND@25" pad="E11"/> +<connect gate="BGNDA" pin="GND@26" pad="E20"/> +<connect gate="BGNDA" pin="GND@27" pad="F5"/> +<connect gate="BGNDA" pin="GND@28" pad="F11"/> +<connect gate="BGNDA" pin="GND@29" pad="F17"/> +<connect gate="BGNDA" pin="GND@3" pad="A7"/> +<connect gate="BGNDA" pin="GND@30" pad="G5"/> +<connect gate="BGNDA" pin="GND@31" pad="G6"/> +<connect gate="BGNDA" pin="GND@32" pad="G7"/> +<connect gate="BGNDA" pin="GND@33" pad="G8"/> +<connect gate="BGNDA" pin="GND@34" pad="G9"/> +<connect gate="BGNDA" pin="GND@35" pad="G10"/> +<connect gate="BGNDA" pin="GND@36" pad="G12"/> +<connect gate="BGNDA" pin="GND@37" pad="G14"/> +<connect gate="BGNDA" pin="GND@38" pad="H1"/> +<connect gate="BGNDA" pin="GND@39" pad="H7"/> +<connect gate="BGNDA" pin="GND@4" pad="A9"/> +<connect gate="BGNDA" pin="GND@40" pad="H9"/> +<connect gate="BGNDA" pin="GND@41" pad="H11"/> +<connect gate="BGNDA" pin="GND@42" pad="H21"/> +<connect gate="BGNDA" pin="GND@43" pad="J8"/> +<connect gate="BGNDA" pin="GND@5" pad="A11"/> +<connect gate="BGNDA" pin="GND@6" pad="A12"/> +<connect gate="BGNDA" pin="GND@7" pad="A22"/> +<connect gate="BGNDA" pin="GND@8" pad="B3"/> +<connect gate="BGNDA" pin="GND@9" pad="B12"/> +<connect gate="BGNDB" pin="GND@44" pad="J10"/> +<connect gate="BGNDB" pin="GND@45" pad="J12"/> +<connect gate="BGNDB" pin="GND@46" pad="J18"/> +<connect gate="BGNDB" pin="GND@47" pad="K5"/> +<connect gate="BGNDB" pin="GND@48" pad="K7"/> +<connect gate="BGNDB" pin="GND@49" pad="K11"/> +<connect gate="BGNDB" pin="GND@50" pad="K15"/> +<connect gate="BGNDB" pin="GND@51" pad="L2"/> +<connect gate="BGNDB" pin="GND@52" pad="L8"/> +<connect gate="BGNDB" pin="GND@53" pad="L22"/> +<connect gate="BGNDB" pin="GND@54" pad="M7"/> +<connect gate="BGNDB" pin="GND@55" pad="M11"/> +<connect gate="BGNDB" pin="GND@56" pad="M19"/> +<connect gate="BGNDB" pin="GND@57" pad="N6"/> +<connect gate="BGNDB" pin="GND@58" pad="N8"/> +<connect gate="BGNDB" pin="GND@59" pad="N16"/> +<connect gate="BGNDB" pin="GND@60" pad="P3"/> +<connect gate="BGNDB" pin="GND@61" pad="P7"/> +<connect gate="BGNDB" pin="GND@62" pad="P9"/> +<connect gate="BGNDB" pin="GND@63" pad="P11"/> +<connect gate="BGNDB" pin="GND@64" pad="P13"/> +<connect gate="BGNDB" pin="GND@65" pad="R8"/> +<connect gate="BGNDB" pin="GND@66" pad="R10"/> +<connect gate="BGNDB" pin="GND@67" pad="R12"/> +<connect gate="BGNDB" pin="GND@68" pad="R20"/> +<connect gate="BGNDB" pin="GND@69" pad="T7"/> +<connect gate="BGNDB" pin="GND@70" pad="T9"/> +<connect gate="BGNDB" pin="GND@71" pad="T11"/> +<connect gate="BGNDB" pin="GND@72" pad="T17"/> +<connect gate="BGNDB" pin="GND@73" pad="U4"/> +<connect gate="BGNDB" pin="GND@74" pad="U14"/> +<connect gate="BGNDB" pin="GND@75" pad="V1"/> +<connect gate="BGNDB" pin="GND@76" pad="V11"/> +<connect gate="BGNDB" pin="GND@77" pad="V21"/> +<connect gate="BGNDB" pin="GND@78" pad="W8"/> +<connect gate="BGNDB" pin="GND@79" pad="W18"/> +<connect gate="BGNDB" pin="GND@80" pad="Y5"/> +<connect gate="BGNDB" pin="GND@81" pad="Y15"/> +<connect gate="BGNDB" pin="GND@82" pad="AA2"/> +<connect gate="BGNDB" pin="GND@83" pad="AA12"/> +<connect gate="BGNDB" pin="GND@84" pad="AA22"/> +<connect gate="BGNDB" pin="GND@85" pad="AB9"/> +<connect gate="BGNDB" pin="GND@86" pad="AB19"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@0" pad="D6"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@1" pad="D10"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@2" pad="E8"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@3" pad="F7"/> +<connect gate="BMGTAVCC" pin="MGTAVCC@4" pad="F9"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@0" pad="B5"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@1" pad="B7"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@2" pad="B9"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@3" pad="B11"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@4" pad="C4"/> +<connect gate="BMGTAVTT" pin="MGTAVTT@5" pad="C8"/> +<connect gate="BTDIODE" pin="DXN_0" pad="N9"/> +<connect gate="BTDIODE" pin="DXP_0" pad="N10"/> +<connect gate="BVCCAUX" pin="VCCAUX@0" pad="H12"/> +<connect gate="BVCCAUX" pin="VCCAUX@1" pad="K12"/> +<connect gate="BVCCAUX" pin="VCCAUX@2" pad="M12"/> +<connect gate="BVCCAUX" pin="VCCAUX@3" pad="P12"/> +<connect gate="BVCCAUX" pin="VCCAUX@4" pad="R11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@0" pad="J11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@1" pad="L11"/> +<connect gate="BVCCBRAM" pin="VCCBRAM@2" pad="N11"/> +<connect gate="BVCCINT" pin="VCCINT@0" pad="H8"/> +<connect gate="BVCCINT" pin="VCCINT@1" pad="H10"/> +<connect gate="BVCCINT" pin="VCCINT@10" pad="R7"/> +<connect gate="BVCCINT" pin="VCCINT@11" pad="R9"/> +<connect gate="BVCCINT" pin="VCCINT@12" pad="T8"/> +<connect gate="BVCCINT" pin="VCCINT@13" pad="T10"/> +<connect gate="BVCCINT" pin="VCCINT@2" pad="J7"/> +<connect gate="BVCCINT" pin="VCCINT@3" pad="J9"/> +<connect gate="BVCCINT" pin="VCCINT@4" pad="K8"/> +<connect gate="BVCCINT" pin="VCCINT@5" pad="L7"/> +<connect gate="BVCCINT" pin="VCCINT@6" pad="M8"/> +<connect gate="BVCCINT" pin="VCCINT@7" pad="N7"/> +<connect gate="BVCCINT" pin="VCCINT@8" pad="P8"/> +<connect gate="BVCCINT" pin="VCCINT@9" pad="P10"/> +<connect gate="BXADC" pin="GNDADC_0" pad="K9"/> +<connect gate="BXADC" pin="VCCADC_0" pad="K10"/> +<connect gate="BXADC" pin="VN_0" pad="M9"/> +<connect gate="BXADC" pin="VP_0" pad="L10"/> +<connect gate="BXADC" pin="VREFN_0" pad="L9"/> +<connect gate="BXADC" pin="VREFP_0" pad="M10"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="altera-configdevices"> +<packages> +<package name="SO08"> +<description><b>Small Outline Package</b></description> +<wire x1="2.159" y1="1.9558" x2="-2.159" y2="1.9558" width="0.1524" layer="21"/> +<wire x1="2.159" y1="-1.9558" x2="2.54" y2="-1.5748" width="0.1524" layer="21" curve="90"/> +<wire x1="-2.54" y1="1.5748" x2="-2.159" y2="1.9558" width="0.1524" layer="21" curve="-90"/> +<wire x1="2.159" y1="1.9558" x2="2.54" y2="1.5748" width="0.1524" layer="21" curve="-90"/> +<wire x1="-2.54" y1="-1.5748" x2="-2.159" y2="-1.9558" width="0.1524" layer="21" curve="90"/> +<wire x1="-2.159" y1="-1.9558" x2="2.159" y2="-1.9558" width="0.1524" layer="21"/> +<wire x1="2.54" y1="-1.5748" x2="2.54" y2="1.5748" width="0.1524" layer="21"/> +<wire x1="-2.54" y1="1.5748" x2="-2.54" y2="-1.5748" width="0.1524" layer="21"/> +<wire x1="-2.54" y1="0.508" x2="-2.54" y2="-0.508" width="0.1524" layer="21" curve="-180"/> +<wire x1="-2.54" y1="-1.6002" x2="2.54" y2="-1.6002" width="0.0508" layer="21"/> +<smd name="1" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="8" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="2" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="3" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="7" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="6" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="4" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/> +<smd name="5" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/> +<text x="3.937" y="-2.032" size="1.27" layer="27" ratio="10" rot="R90">>VALUE</text> +<text x="-2.921" y="-1.905" size="1.27" layer="25" ratio="10" rot="R90">>NAME</text> +<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/> +<rectangle x1="-2.159" y1="-3.0988" x2="-1.651" y2="-1.9558" layer="51"/> +<rectangle x1="-0.889" y1="-3.0988" x2="-0.381" y2="-1.9558" layer="51"/> +<rectangle x1="0.381" y1="-3.0734" x2="0.889" y2="-1.9304" layer="51"/> +<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/> +<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/> +<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/> +<rectangle x1="-2.159" y1="1.9558" x2="-1.651" y2="3.0988" layer="51"/> +</package> +<package name="DFN-S"> +<description><b>8-Lead Plastic Dual Flat No Lead Package (MF)</b> 6x5 mm Body (DFN-S)<p> +Source: http://www.microchip.com .. 41190c.pdf</description> +<wire x1="-2.94" y1="2.41" x2="2.94" y2="2.41" width="0.1016" layer="21"/> +<wire x1="2.94" y1="2.41" x2="2.94" y2="2.26" width="0.1016" layer="21"/> +<wire x1="-2.94" y1="2.41" x2="-2.94" y2="2.26" width="0.1016" layer="21"/> +<wire x1="2.94" y1="-2.41" x2="-2.94" y2="-2.41" width="0.1016" layer="21"/> +<wire x1="-2.94" y1="-2.41" x2="-2.94" y2="-2.26" width="0.1016" layer="21"/> +<wire x1="2.94" y1="-2.41" x2="2.94" y2="-2.26" width="0.1016" layer="21"/> +<wire x1="-2.94" y1="2.41" x2="-2.94" y2="-2.41" width="0.1016" layer="51"/> +<wire x1="2.94" y1="-2.41" x2="2.94" y2="2.41" width="0.1016" layer="51"/> +<circle x="-2.02" y="1.78" radius="0.22" width="0.1016" layer="21"/> +<smd name="1" x="-2.69" y="1.905" dx="0.4" dy="0.6" layer="1" rot="R90"/> +<smd name="2" x="-2.69" y="0.635" dx="0.4" dy="0.6" layer="1" rot="R90"/> +<smd name="3" x="-2.69" y="-0.635" dx="0.4" dy="0.6" layer="1" rot="R90"/> +<smd name="4" x="-2.69" y="-1.905" dx="0.4" dy="0.6" layer="1" rot="R90"/> +<smd name="5" x="2.69" y="-1.905" dx="0.4" dy="0.6" layer="1" rot="R270"/> +<smd name="6" x="2.69" y="-0.635" dx="0.4" dy="0.6" layer="1" rot="R270"/> +<smd name="7" x="2.69" y="0.635" dx="0.4" dy="0.6" layer="1" rot="R270"/> +<smd name="8" x="2.69" y="1.905" dx="0.4" dy="0.6" layer="1" rot="R270"/> +<text x="-2.54" y="3.175" size="1.27" layer="25">>NAME</text> +<text x="-2.54" y="-4.445" size="1.27" layer="27">>VALUE</text> +</package> +</packages> +<symbols> +<symbol name="ALTERA_EPCQ"> +<pin name="!S" x="-17.78" y="6.35" length="middle"/> +<pin name="DQ1" x="-17.78" y="3.81" length="middle"/> +<pin name="!W!/VPP/DQ2" x="-17.78" y="1.27" length="middle"/> +<pin name="VSS" x="-17.78" y="-1.27" length="middle"/> +<pin name="VCC" x="19.05" y="6.35" length="middle" rot="R180"/> +<pin name="!HOLD!/DQ3" x="19.05" y="3.81" length="middle" rot="R180"/> +<pin name="C" x="19.05" y="1.27" length="middle" rot="R180"/> +<pin name="DQ0" x="19.05" y="-1.27" length="middle" rot="R180"/> +<wire x1="-12.7" y1="8.89" x2="13.97" y2="8.89" width="0.127" layer="94"/> +<wire x1="13.97" y1="8.89" x2="13.97" y2="-3.81" width="0.127" layer="94"/> +<wire x1="13.97" y1="-3.81" x2="-12.7" y2="-3.81" width="0.127" layer="94"/> +<wire x1="-12.7" y1="-3.81" x2="-12.7" y2="8.89" width="0.127" layer="94"/> +<text x="-11.43" y="9.398" size="1" layer="95" font="vector">>Name</text> +<text x="1.524" y="9.398" size="1" layer="96" font="vector">>Value</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="N25Q128A13E" prefix="IC"> +<gates> +<gate name="A" symbol="ALTERA_EPCQ" x="0" y="-6.35"/> +</gates> +<devices> +<device name="S" package="SO08"> +<connects> +<connect gate="A" pin="!HOLD!/DQ3" pad="7"/> +<connect gate="A" pin="!S" pad="1"/> +<connect gate="A" pin="!W!/VPP/DQ2" pad="3"/> +<connect gate="A" pin="C" pad="6"/> +<connect gate="A" pin="DQ0" pad="5"/> +<connect gate="A" pin="DQ1" pad="2"/> +<connect gate="A" pin="VCC" pad="8"/> +<connect gate="A" pin="VSS" pad="4"/> +</connects> +<technologies> +<technology name=""> +<attribute name="OC_DIGIKEY" value="557-1562-ND"/> +<attribute name="OC_FARNELL" value="2253682"/> +<attribute name="PRICE100_DIGIKEY" value="1.30470" constant="no"/> +<attribute name="PRICE100_FARNELL" value="5.10" constant="no"/> +</technology> +</technologies> +</device> +<device name="F7" package="DFN-S"> +<connects> +<connect gate="A" pin="!HOLD!/DQ3" pad="7"/> +<connect gate="A" pin="!S" pad="1"/> +<connect gate="A" pin="!W!/VPP/DQ2" pad="3"/> +<connect gate="A" pin="C" pad="6"/> +<connect gate="A" pin="DQ0" pad="5"/> +<connect gate="A" pin="DQ1" pad="2"/> +<connect gate="A" pin="VCC" pad="8"/> +<connect gate="A" pin="VSS" pad="4"/> +</connects> +<technologies> +<technology name=""> +<attribute name="OC_DIGIKEY" value="N25Q128A13EF740F TR-ND"/> +<attribute name="PRICE100_DIGIKEY" value="" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="transistors_gaui"> +<description><b>2N7002T; N-channel TrenchMOS FET</b><p> +Produced by Philips. All information is found at:<br> +http://www.semiconductors.philips.com/pip/2N7002T.html<br> +</p> +<author>Created by gudjon@mc2.chalmers.se</author></description> +<packages> +<package name="SOT23"> +<description><b>SOT-23</b></description> +<wire x1="1.4224" y1="0.6604" x2="1.4224" y2="-0.6604" width="0.1524" layer="51"/> +<wire x1="1.4224" y1="-0.6604" x2="-1.4224" y2="-0.6604" width="0.1524" layer="51"/> +<wire x1="-1.4224" y1="-0.6604" x2="-1.4224" y2="0.6604" width="0.1524" layer="51"/> +<wire x1="-1.4224" y1="0.6604" x2="1.4224" y2="0.6604" width="0.1524" layer="51"/> +<smd name="3" x="0" y="1.1" dx="1" dy="1.4" layer="1"/> +<smd name="2" x="0.95" y="-1.1" dx="1" dy="1.4" layer="1"/> +<smd name="1" x="-0.95" y="-1.1" dx="1" dy="1.4" layer="1"/> +<text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text> +<text x="-1.905" y="-3.175" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-0.2286" y1="0.7112" x2="0.2286" y2="1.2954" layer="51"/> +<rectangle x1="0.7112" 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+</table> + +Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF</description> +<wire x1="-1.5" y1="0.5" x2="-1.5" y2="-0.5" width="0.2032" layer="51" curve="-180"/> +<wire x1="1.5" y1="-0.5" x2="1.5" y2="0.5" width="0.2032" layer="51" curve="-180"/> +<wire x1="-1.55" y1="0.75" x2="1.55" y2="0.75" width="0.1016" layer="51"/> +<wire x1="1.55" y1="-0.75" x2="-1.55" y2="-0.75" width="0.1016" layer="51"/> +<circle x="-0.725" y="0.525" radius="0.125" width="0" layer="21"/> +<smd name="C" x="-1.75" y="0" dx="1.5" dy="1.5" layer="1"/> +<smd name="A" x="1.75" y="0" dx="1.5" dy="1.5" layer="1"/> +<text x="-1.5" y="1" size="1.27" layer="25">>NAME</text> +<text x="-1.5" y="-2.5" size="1.27" layer="27">>VALUE</text> +<rectangle x1="-1.6" y1="0.4" x2="-1.15" y2="0.8" layer="51"/> +<rectangle x1="-1.6" y1="-0.8" x2="-1.15" y2="-0.4" layer="51"/> +<rectangle x1="-1.175" y1="-0.6" x2="-1" y2="-0.275" layer="51"/> +<rectangle x1="1.15" y1="-0.8" x2="1.6" y2="-0.4" layer="51" rot="R180"/> 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width="0.254" layer="94"/> +<wire x1="0" y1="-2.54" x2="-1.27" y2="-2.54" width="0.254" layer="94"/> +<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/> +<wire x1="0" y1="0" x2="0" y2="-2.54" width="0.1524" layer="94"/> +<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/> +<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/> +<text x="3.556" y="-4.572" size="1.778" layer="95" rot="R90">>NAME</text> +<text x="5.715" y="-4.572" size="1.778" layer="96" rot="R90">>VALUE</text> +<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/> +<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/> +<polygon width="0.1524" layer="94"> +<vertex x="-3.429" y="-2.159"/> +<vertex x="-3.048" y="-1.27"/> +<vertex x="-2.54" y="-1.778"/> +</polygon> +<polygon width="0.1524" layer="94"> +<vertex x="-3.302" y="-3.302"/> +<vertex x="-2.921" y="-2.413"/> +<vertex x="-2.413" y="-2.921"/> +</polygon> +</symbol> +</symbols> +<devicesets> +<deviceset name="LED" prefix="LED" uservalue="yes"> +<description><b>LED</b><p> +<u>OSRAM</u>:<br> + +- <u>CHIPLED</u><br> +LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971 +LH N974, LH R974<br> +LS Q976, LO Q976, LY Q976<br> +LO Q996<br> + +- <u>Hyper CHIPLED</u><br> +LW Q18S<br> +LB Q993, LB Q99A, LB R99A<br> + +- <u>SideLED</u><br> +LS A670, LO A670, LY A670, LG A670, LP A670<br> +LB A673, LV A673, LT A673, LW A673<br> +LH A674<br> +LY A675<br> +LS A676, LA A676, LO A676, LY A676, LW A676<br> +LS A679, LY A679, LG A679<br> + +- <u>Hyper Micro SIDELED®</u><br> +LS Y876, LA Y876, LO Y876, LY Y876<br> +LT Y87S<br> + +- <u>SmartLED</u><br> +LW L88C, LW L88S<br> +LB L89C, LB L89S, LG L890<br> +LS L89K, LO L89K, LY L89K<br> +LS L896, LA L896, LO L896, LY L896<br> + +- <u>TOPLED</u><br> +LS T670, LO T670, LY T670, LG T670, LP T670<br> +LSG T670, LSP T670, LSY T670, LOP T670, LYG T670<br> +LG T671, LOG T671, LSG T671<br> +LB T673, LV T673, LT T673, LW T673<br> +LH T674<br> +LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676<br> +LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C<br> +LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C<br> +LW T67C<br> +LS T679, LY T679, LG T679<br> +LS T770, LO T770, LY T770, LG T770, LP T770<br> +LB T773, LV T773, LT T773, LW T773<br> +LH T774<br> +LS E675, LA E675, LY E675, LS T675<br> +LS T776, LA T776, LO T776, LY T776, LB T776<br> +LHGB T686<br> +LT T68C, LB T68C<br> + +- <u>Hyper Mini TOPLED®</u><br> +LB M676<br> + +- <u>Mini TOPLED Santana®</u><br> +LG M470<br> +LS M47K, LO M47K, LY M47K +<p> +Source: http://www.osram.convergy.de<p> + +<u>LUXEON:</u><br> +- <u>LUMILED®</u><br> +LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00<br> +LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00<br> +LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00<br> +LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00<br> +LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00<br> +LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00<br> +LXK2-PH12-R00, LXK2-PH12-S00<br> +LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00 +<p> +Source: www.luxeon.com<p> + +<u>KINGBRIGHT:</U><p> +KA-3528ASYC<br> +Source: www.kingbright.com</description> +<gates> +<gate name="G$1" symbol="LED" x="0" y="0"/> +</gates> +<devices> +<device name="SMT1206" package="1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LD260" package="LD260"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SQR2X5" package="LED2X5"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="3MM" package="LED3MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="5MM" package="LED5MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LSU260" package="LSU260"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="LZR181" package="LZR181"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B152" package="Q62902-B152"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B153" package="Q62902-B153"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B155" package="Q62902-B155"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="B156" package="Q62902-B156"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SFH480" package="SFH480"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SFH482" package="SFH482"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SQR5.7X3.2" package="U57X32"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="IRL80A" package="IRL80A"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-2" package="P-LCC-2"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="MINI-TOP" package="OSRAM-MINI-TOP-LED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SIDELED" package="OSRAM-SIDELED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SMART-LED" package="SMART-LED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="B"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-2-BACK" package="P-LCC-2-TOPLED-RG"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="MICRO-SIDELED" package="MICRO-SIDELED"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="P-LCC-4" package="P-LCC-4"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C@4"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIP-LED0603" package="CHIP-LED0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIP-LED0805" package="CHIP-LED0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="TOPLED-SANTANA" package="MINI-TOPLED-SANTANA"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_0805" package="CHIPLED_0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_1206" package="CHIPLED_1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED_0603" package="CHIPLED_0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CHIPLED-0603-TTW" package="CHIPLED-0603-TTW"> +<connects> +<connect gate="G$1" pin="A" pad="A@1"/> +<connect gate="G$1" pin="C" pad="C@1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="" package="SMARTLED-TTW"> +<connects> +<connect gate="G$1" pin="A" pad="A@1"/> +<connect gate="G$1" pin="C" pad="C@1"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-LUMILED+" package="LUMILED+"> +<connects> +<connect gate="G$1" pin="A" pad="2+"/> +<connect gate="G$1" pin="C" pad="4-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-LUMILED" package="LUMILED"> +<connects> +<connect gate="G$1" pin="A" pad="2+"/> +<connect gate="G$1" pin="C" pad="4-"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="10MM" package="LED10MM"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="K"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="KA-3528ASYC" package="KA-3528ASYC"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML0805" package="SML0805"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML1206" package="SML1206"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="SML0603" package="SML0603"> +<connects> +<connect gate="G$1" pin="A" pad="A"/> +<connect gate="G$1" pin="C" pad="C"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="con-lstb"> +<description><b>Pin Headers</b><p> +Naming:<p> +MA = male<p> +# contacts - # rows<p> +W = angled<p> +<author>Created by librarian@cadsoft.de</author></description> +<packages> +<package name="MA08-2"> +<description><b>PIN HEADER</b></description> +<wire x1="-9.525" y1="2.54" x2="-8.255" y2="2.54" width="0.1524" layer="21"/> +<wire x1="-8.255" y1="2.54" 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y1="-10.16" x2="-10.16" y2="10.16" width="0.254" layer="94"/> +<pin name="REF/BYP" x="15.24" y="-7.62" length="middle" direction="in" rot="R180"/> +<pin name="ADJ" x="15.24" y="0" length="middle" direction="in" rot="R180"/> +<pin name="OUT" x="15.24" y="7.62" length="middle" direction="pwr" rot="R180"/> +<pin name="IN" x="-15.24" y="7.62" length="middle" direction="pwr"/> +<pin name="!SHDN" x="-15.24" y="0" length="middle" direction="in"/> +<pin name="GND" x="-15.24" y="-7.62" length="middle" direction="pwr"/> +<text x="-7.62" y="12.7" size="2.0828" layer="95">>NAME</text> +<text x="-12.7" y="-15.24" size="2.0828" layer="96">>VALUE</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="EN6347QI" prefix="U"> +<description>3A PowerSoC +Voltage Mode Synchronous PWM Buck with Integrated Inductor</description> +<gates> +<gate name="G$1" symbol="EN6337QI" x="0" y="0"/> +</gates> +<devices> +<device name="" package="QFN38_4X7X1.85"> +<connects> +<connect gate="G$1" pin="AGND" pad="32"/> +<connect gate="G$1" pin="AVIN" pad="33"/> +<connect gate="G$1" pin="ENABLE" pad="27"/> +<connect gate="G$1" pin="LLM/SYNC" pad="26"/> +<connect gate="G$1" pin="NC" pad="1 2 3 4 12 22 23 24 25 34 35 36 37 38"/> +<connect gate="G$1" pin="PGND" pad="13 14 15 16 17 18 P$39 P$40"/> +<connect gate="G$1" pin="POK" pad="28"/> +<connect gate="G$1" pin="PVIN" pad="19 20 21"/> +<connect gate="G$1" pin="RLLM" pad="29"/> +<connect gate="G$1" pin="SS" pad="30"/> +<connect gate="G$1" pin="VFB" pad="31"/> +<connect gate="G$1" pin="VOUT" pad="5 6 7 8 9 10 11"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="EN6347QI" constant="no"/> +<attribute name="OC_FARNELL" value="2081146" constant="no"/> +<attribute name="PACKAGE" value="QFN" constant="no"/> +<attribute name="SUPPLIER" value="ENPIRION" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="EN5364QI" prefix="U"> +<description>6A PowerSoC +Voltage Mode Synchronous Buck PWM DC-DC Converter +With Integrated Inductor</description> +<gates> +<gate name="G$1" symbol="EN5364QI" x="0" y="0"/> +</gates> +<devices> +<device name="" package="QFN68_8X11X1.85"> +<connects> +<connect gate="G$1" pin="AGND" pad="55"/> +<connect gate="G$1" pin="AVIN" pad="53"/> +<connect gate="G$1" pin="EAOUT" pad="57"/> +<connect gate="G$1" pin="ENABLE" pad="52"/> +<connect gate="G$1" pin="EN_PB" pad="51"/> +<connect gate="G$1" pin="M/S" pad="50"/> +<connect gate="G$1" pin="MAR1" pad="61"/> +<connect gate="G$1" pin="MAR2" pad="62"/> +<connect gate="G$1" pin="NC" pad="14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47"/> +<connect gate="G$1" pin="OCP_ADJ" pad="58"/> +<connect gate="G$1" pin="PGND" pad="1 2 3 4 27 28 29 30 31 32 33 64 65 66 67 68 P$69 P$70 P$71"/> +<connect gate="G$1" pin="POK" pad="54"/> +<connect gate="G$1" pin="PVIN" pad="34 35 36 37 38 39 40 41 42 43"/> +<connect gate="G$1" pin="SS" pad="59"/> +<connect gate="G$1" pin="S_DELAY" pad="60"/> +<connect gate="G$1" pin="S_IN" pad="49"/> +<connect gate="G$1" pin="S_OUT" pad="48"/> +<connect gate="G$1" pin="VFB" pad="56"/> +<connect gate="G$1" pin="VOUT" pad="5 6 7 8 9 10 11 12 13"/> +<connect gate="G$1" pin="VSENSE" pad="63"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="EN5364QI" constant="no"/> +<attribute name="OC_FARNELL" value="2081142" constant="no"/> +<attribute name="PACKAGE" value="QFN" constant="no"/> +<attribute name="SUPPLIER" value="ENPIRION" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LMZ13608" prefix="U"> +<description>LMZ13608 8-A SIMPLE SWITCHER +Power Module With 36-V Maximum Input Voltage + +http://www.ti.com/lit/ds/symlink/lmz13608.pdf</description> +<gates> +<gate name="G$1" symbol="LMZ13608" x="0" y="0"/> +</gates> +<devices> +<device name="" package="NDY"> +<connects> +<connect gate="G$1" pin="AGND" pad="3 5 6"/> +<connect gate="G$1" pin="EN" pad="4"/> +<connect gate="G$1" pin="FB" pad="7"/> +<connect gate="G$1" pin="NC" pad="9"/> +<connect gate="G$1" pin="PGND" pad="TP1"/> +<connect gate="G$1" pin="SS/TRK" pad="8"/> +<connect gate="G$1" pin="VIN" pad="1 2"/> +<connect gate="G$1" pin="VOUT" pad="10 11"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="LMZ13608TZ/NOPB" constant="no"/> +<attribute name="OC_FARNELL" value="2492265" constant="no"/> +<attribute name="PACKAGE" value="NDY (11)" constant="no"/> +<attribute name="SUPPLIER" value="Texas Instruments" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="LT3060?-*" prefix="U"> +<description>Micropower, Low Noise, 100mA LDO, Linear Regulator</description> +<gates> +<gate name="G$1" symbol="LT3060" x="0" y="0"/> +</gates> +<devices> +<device name="" package="TSOT-8-23"> +<connects> +<connect gate="G$1" pin="!SHDN" pad="1"/> +<connect gate="G$1" pin="ADJ" pad="7"/> +<connect gate="G$1" pin="GND" pad="2 3 4"/> +<connect gate="G$1" pin="IN" pad="5"/> +<connect gate="G$1" pin="OUT" pad="6"/> +<connect gate="G$1" pin="REF/BYP" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="LT3060ITS8-15#TRMPBF" constant="no"/> +<attribute name="OC_FARNELL" value="2471073" constant="no"/> +<attribute name="SUPPLIER" value="Linear Technology" constant="no"/> +</technology> +</technologies> +</device> +<device name="ITS8" package="TSOT-8-23"> +<connects> +<connect gate="G$1" pin="!SHDN" pad="1"/> +<connect gate="G$1" pin="ADJ" pad="7"/> +<connect gate="G$1" pin="GND" pad="2 3 4"/> +<connect gate="G$1" pin="IN" pad="5"/> +<connect gate="G$1" pin="OUT" pad="6"/> +<connect gate="G$1" pin="REF/BYP" pad="8"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="" constant="no"/> +<attribute name="OC_FARNELL" value="" constant="no"/> +<attribute name="SUPPLIER" value="Linear Technology" constant="no"/> +</technology> +<technology name="15"> +<attribute name="MPN" value="LT3060ITS8-15#TRMPBF" constant="no"/> +<attribute name="OC_FARNELL" value="2471073" constant="no"/> +<attribute name="SUPPLIER" value="" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="rc-master"> +<description><b>R/C MASTER! - v1.07 (07/03/2007)</b><p> +<p>This library is a collection of SMD and through hole resistors and capacitors by various manufacturers. Some of these include types from Panasonic, Kemet, BC Components and others. Many of the packages were adapted from <b>rcl.lbr</b> and <b>cap-pan40.lbr</b> and have been renamed and grouped in a more logical form.</p><p>Silkscreen elements are a minimum of 8 mils in width with larger components using 10 mil widths. Most of the SMD components have text sizes of 0 .04" and thru-hole components are 0.05" in size. A text ratio of 14 is used in both cases. Where practical, the elements are aligned on a 12.5 mil or 6.25 mil grid depending on the pad size and spacing.</p> +<p><h4>All capacitors are grouped by the following naming conventions:</h4></p> +<table width="380" border="1" bordercolor="#000000"> + <tr> + <td width="81" bgcolor="#33CCFF"><div align="center"><strong>Prefix</strong></div></td> + <td width="289" bgcolor="#33CCFF"><div align="center"><strong>Description</strong></div></td> + </tr> + <tr> + <td><div align="center">CBP_</div></td> + <td><div align="center">Bipolar Electrolytic Types</div></td> + </tr> + <tr> + <td><div align="center">CCA_</div></td> + <td><div align="center">Chip Cap Array Types</div></td> + </tr> + <tr> + <td><div align="center">CP_</div></td> + <td><div align="center">Polarized Electrolytic/Tantalum Types</div></td> + </tr> + <tr> + <td><div align="center">C_</div></td> + <td><div align="center">Non-Polarized Film / Chip Types</div></td> + </tr> + <tr> + <td><div align="center">FB_</div></td> + <td><div align="center">Simple Ferrite Bead Types</div></td> + </tr> + <tr> + <td><div align="center">L_</div></td> + <td><div align="center">Simple Chip Inductors</div></td> + </tr> + <tr> + <td><div align="center">R_</div></td> + <td><div align="center">Resistor Types</div></td> + </tr> +</table> +<p> +<p><author>THIS LIBRARY IS PROVIDED AS IS AND WITHOUT WARRANTY OF ANY KIND, EXPRESSED OR IMPLIED.<br>Copyright (C) 2007, Bob Starr<br> http://www.bobstarr.net<br> +</author></description> +<packages> +<package name="CE-010X030"> +<description><b>POLCAP RADIAL</b><p> +1.0 mm lead spacing, 3 mm diameter, grid 0.0125 inch</description> +<wire x1="-2.2225" y1="0.9525" x2="-1.5875" y2="0.9525" width="0.254" layer="21"/> +<wire x1="-1.905" y1="0.635" x2="-1.905" y2="1.27" width="0.254" layer="21"/> +<wire x1="-0.3587" y1="0" x2="-0.7" y2="0" width="0.2032" layer="51"/> +<wire x1="0.2764" y1="0" x2="0.7" y2="0" width="0.2032" layer="51"/> +<wire x1="0.2" y1="0" x2="0.4" y2="0.6" width="0.254" layer="51" curve="-37.877434" cap="flat"/> +<wire x1="0.4" y1="-0.6" x2="0.2" y2="0" width="0.254" layer="51" curve="-37.380842" cap="flat"/> +<wire x1="-0.2587" y1="-0.6349" x2="-0.2587" y2="0.635" width="0.254" layer="51"/> +<circle x="0" y="0" radius="1.506" width="0.2032" layer="21"/> +<pad name="+" x="-0.635" y="0" drill="0.6096" diameter="0.8128" shape="long" rot="R90"/> +<pad name="-" x="0.635" y="0" drill="0.6096" diameter="0.8128" shape="long" rot="R90"/> +<text x="1.5874" y="-1.905" size="0.8128" layer="27" ratio="10">>VALUE</text> +<text x="1.5874" y="0.635" size="1.016" layer="25" ratio="18">>NAME</text> +</package> +<package name="CE-020X050"> +<description><b>POLCAP RADIAL</b><p> +2.0 mm lead spacing, 5 mm diameter, grid 0.0125 inch</description> +<wire x1="-1.27" y1="1.905" x2="-0.635" y2="1.905" width="0.254" layer="21"/> +<wire x1="-0.9525" y1="1.5875" x2="-0.9525" y2="2.2225" width="0.254" layer="21"/> +<wire x1="-0.3175" y1="0" x2="-0.9525" y2="0" width="0.2032" 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y1="2.54" x2="-1.27" y2="1.5875" width="0.254" layer="21"/> +<wire x1="-0.3175" y1="0" x2="-1.27" y2="0" width="0.2032" layer="51"/> +<wire x1="0.3176" y1="0" x2="1.27" y2="0" width="0.2032" layer="51"/> +<wire x1="0.3176" y1="0" x2="0.6351" y2="1.1112" width="0.3048" layer="51" curve="-37.874253" cap="flat"/> +<wire x1="0.6351" y1="-1.1113" x2="0.3176" y2="0" width="0.3048" layer="51" curve="-37.379812" cap="flat"/> +<wire x1="-0.3175" y1="-1.1112" x2="-0.3175" y2="1.1113" width="0.3048" layer="51"/> +<circle x="0" y="0" radius="3.4342" width="0.2032" layer="21"/> +<pad name="+" x="-1.27" y="0" drill="0.8128" diameter="1.778"/> +<pad name="-" x="1.27" y="0" drill="0.8128" diameter="1.778" shape="octagon"/> +<text x="3.81" y="1.905" size="1.016" layer="25" ratio="18">>NAME</text> +<text x="3.81" y="-3.175" size="0.8128" layer="27" ratio="10">>VALUE</text> +</package> +<package name="CE-025X065"> +<description><b>POLCAP RADIAL</b><p> +2.5 mm lead spacing, 6.5 mm diameter, grid 0.0125 inch</description> +<wire x1="-1.7462" y1="2.0638" x2="-0.7937" y2="2.0638" width="0.254" layer="21"/> +<wire x1="-1.27" y1="2.54" x2="-1.27" y2="1.5875" width="0.254" layer="21"/> +<wire x1="-0.3175" y1="0" x2="-1.27" y2="0" width="0.2032" layer="51"/> +<wire x1="0.3176" y1="0" x2="1.27" y2="0" width="0.2032" layer="51"/> +<wire x1="0.3176" y1="0" x2="0.6351" y2="1.1112" width="0.3048" layer="51" curve="-37.874253" cap="flat"/> +<wire x1="0.6351" y1="-1.1113" x2="0.3176" y2="0" width="0.3048" layer="51" curve="-37.379812" cap="flat"/> +<wire x1="-0.3175" y1="-1.1112" x2="-0.3175" y2="1.1113" width="0.3048" layer="51"/> +<circle x="0" y="0" radius="3.62" width="0.2032" layer="21"/> +<pad name="+" x="-1.27" y="0" drill="0.8128" diameter="1.778"/> +<pad name="-" x="1.27" y="0" drill="0.8128" diameter="1.778" shape="octagon"/> +<text x="3.81" y="1.905" size="1.016" layer="25" ratio="18">>NAME</text> +<text x="3.81" y="-3.175" size="0.8128" layer="27" ratio="10">>VALUE</text> +</package> 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layer="27" ratio="10">>VALUE</text> +<text x="4.445" y="3.4925" size="1.016" layer="25" ratio="18">>NAME</text> +</package> +<package name="CE-035X080"> +<description><b>POLCAP RADIAL</b><p> +3.5 mm lead spacing, 8 mm diameter, grid 0.0125 inch</description> +<wire x1="-2.54" y1="2.2225" x2="-1.27" y2="2.2225" width="0.254" layer="21"/> +<wire x1="-1.905" y1="2.8575" x2="-1.905" y2="1.5875" width="0.254" layer="21"/> +<wire x1="-0.635" y1="0" x2="-1.905" y2="0" width="0.2032" layer="51"/> +<wire x1="0.4763" y1="0" x2="1.5875" y2="0" width="0.2032" layer="51"/> +<wire x1="0.4763" y1="0" x2="0.9525" y2="1.5875" width="0.4064" layer="51" curve="-37.872144" cap="flat"/> +<wire x1="0.9525" y1="-1.4288" x2="0.4763" y2="0" width="0.4064" layer="51" curve="-37.375347" cap="flat"/> +<wire x1="-0.635" y1="-1.5875" x2="-0.635" y2="1.5875" width="0.508" layer="51"/> +<circle x="0" y="0" radius="4.016" width="0.2032" layer="21"/> +<pad name="+" x="-1.905" y="0" drill="1.016" diameter="1.9304"/> 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direction="in" rot="R180"/> +<pin name="RI#" x="27.94" y="12.7" length="middle" direction="in" rot="R180"/> +<pin name="TXDEN" x="27.94" y="7.62" length="middle" direction="out" rot="R180"/> +<pin name="ACBUS1" x="27.94" y="5.08" length="middle" rot="R180"/> +<pin name="ACBUS2" x="27.94" y="2.54" length="middle" rot="R180"/> +<pin name="RXLED#" x="27.94" y="0" length="middle" direction="out" rot="R180"/> +<pin name="TXLED#" x="27.94" y="-2.54" length="middle" direction="out" rot="R180"/> +<pin name="ACBUS5" x="27.94" y="-5.08" length="middle" rot="R180"/> +<pin name="ACBUS6" x="27.94" y="-7.62" length="middle" rot="R180"/> +<pin name="PWRSAV#" x="27.94" y="-10.16" length="middle" rot="R180"/> +<pin name="ACBUS8" x="27.94" y="-12.7" length="middle" rot="R180"/> +<pin name="ACBUS9" x="27.94" y="-15.24" length="middle" rot="R180"/> +<pin name="AGND@4" x="-10.16" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="AGND@9" x="-7.62" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="AGND@41" x="-5.08" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@10" x="-2.54" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@11" x="0" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@22" x="2.54" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@23" x="5.08" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@35" x="7.62" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@36" x="10.16" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@47" x="12.7" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="GND@48" x="15.24" y="-38.1" length="middle" direction="pwr" rot="R90"/> +<pin name="VPHY" x="-5.08" y="38.1" length="middle" rot="R270"/> +<pin name="VPLL" x="-2.54" y="38.1" length="middle" rot="R270"/> +<pin name="VCCIO@12" x="0" y="38.1" length="middle" direction="pwr" rot="R270"/> +<pin name="VCCIO@24" x="2.54" y="38.1" length="middle" direction="pwr" rot="R270"/> +<pin name="VCCIO@46" x="5.08" y="38.1" length="middle" direction="pwr" rot="R270"/> +<text x="-12.7" y="0" size="1.778" layer="95">>NAME</text> +<text x="-12.7" y="-5.08" size="1.778" layer="96">>VALUE</text> +</symbol> +</symbols> +<devicesets> +<deviceset name="IS45S32160F" prefix="U"> +<description>16Mx32, 512Mb SDRAM +Clock frequency: 166, 143 MHz</description> +<gates> +<gate name="G$1" symbol="IS45S32160F-TSOP86L" x="0" y="0"/> +</gates> +<devices> +<device name="" package="TSOP2-86L"> +<connects> +<connect gate="G$1" pin="!CAS" pad="18"/> +<connect gate="G$1" pin="!CS" pad="20"/> +<connect gate="G$1" pin="!RAS" pad="19"/> +<connect gate="G$1" pin="!WE" pad="17"/> +<connect gate="G$1" pin="A0" pad="25"/> +<connect gate="G$1" pin="A1" pad="26"/> +<connect gate="G$1" pin="A10" pad="24"/> +<connect gate="G$1" pin="A11" pad="21"/> +<connect gate="G$1" pin="A12" pad="69"/> +<connect gate="G$1" pin="A2" pad="27"/> +<connect gate="G$1" pin="A3" pad="60"/> +<connect gate="G$1" pin="A4" pad="61"/> +<connect gate="G$1" pin="A5" pad="62"/> +<connect gate="G$1" pin="A6" pad="63"/> +<connect gate="G$1" pin="A7" pad="64"/> +<connect gate="G$1" pin="A8" pad="65"/> +<connect gate="G$1" pin="A9" pad="66"/> +<connect gate="G$1" pin="BA0" pad="22"/> +<connect gate="G$1" pin="BA1" pad="23"/> +<connect gate="G$1" pin="CKE" pad="67"/> +<connect gate="G$1" pin="CLK" pad="68"/> +<connect gate="G$1" pin="DQ0" pad="2"/> +<connect gate="G$1" pin="DQ1" pad="4"/> +<connect gate="G$1" pin="DQ10" pad="77"/> +<connect gate="G$1" pin="DQ11" pad="79"/> +<connect gate="G$1" pin="DQ12" pad="80"/> +<connect gate="G$1" pin="DQ13" pad="82"/> +<connect gate="G$1" pin="DQ14" pad="83"/> +<connect gate="G$1" pin="DQ15" pad="85"/> +<connect gate="G$1" pin="DQ16" pad="31"/> +<connect gate="G$1" pin="DQ17" pad="33"/> +<connect gate="G$1" pin="DQ18" pad="34"/> +<connect gate="G$1" pin="DQ19" pad="36"/> +<connect gate="G$1" pin="DQ2" pad="5"/> +<connect gate="G$1" pin="DQ20" pad="37"/> +<connect gate="G$1" pin="DQ21" pad="39"/> +<connect gate="G$1" pin="DQ22" pad="40"/> +<connect gate="G$1" pin="DQ23" pad="42"/> +<connect gate="G$1" pin="DQ24" pad="45"/> +<connect gate="G$1" pin="DQ25" pad="47"/> +<connect gate="G$1" pin="DQ26" pad="48"/> +<connect gate="G$1" pin="DQ27" pad="50"/> +<connect gate="G$1" pin="DQ28" pad="51"/> +<connect gate="G$1" pin="DQ29" pad="53"/> +<connect gate="G$1" pin="DQ3" pad="7"/> +<connect gate="G$1" pin="DQ30" pad="54"/> +<connect gate="G$1" pin="DQ31" pad="56"/> +<connect gate="G$1" pin="DQ4" pad="8"/> +<connect gate="G$1" pin="DQ5" pad="10"/> +<connect gate="G$1" pin="DQ6" pad="11"/> +<connect gate="G$1" pin="DQ7" pad="13"/> +<connect gate="G$1" pin="DQ8" pad="74"/> +<connect gate="G$1" pin="DQ9" pad="76"/> +<connect gate="G$1" pin="DQM0" pad="16"/> +<connect gate="G$1" pin="DQM1" pad="71"/> +<connect gate="G$1" pin="DQM2" pad="28"/> +<connect gate="G$1" pin="DQM3" pad="59"/> +<connect gate="G$1" pin="VDD@1" pad="1"/> +<connect gate="G$1" pin="VDD@15" pad="15"/> +<connect gate="G$1" pin="VDD@29" pad="29"/> +<connect gate="G$1" pin="VDD@43" pad="43"/> +<connect gate="G$1" pin="VDDQ@3" pad="3"/> +<connect gate="G$1" pin="VDDQ@35" pad="35"/> +<connect gate="G$1" pin="VDDQ@41" pad="41"/> +<connect gate="G$1" pin="VDDQ@49" pad="49"/> +<connect gate="G$1" pin="VDDQ@55" pad="55"/> +<connect gate="G$1" pin="VDDQ@75" pad="75"/> +<connect gate="G$1" pin="VDDQ@81" pad="81"/> +<connect gate="G$1" pin="VSS@44" pad="44"/> +<connect gate="G$1" pin="VSS@58" pad="58"/> +<connect gate="G$1" pin="VSS@72" pad="72"/> +<connect gate="G$1" pin="VSS@86" pad="86"/> +<connect gate="G$1" pin="VSSQ@12" pad="12"/> +<connect gate="G$1" pin="VSSQ@32" pad="32"/> +<connect gate="G$1" pin="VSSQ@38" pad="38"/> +<connect gate="G$1" pin="VSSQ@46" pad="46"/> +<connect gate="G$1" pin="VSSQ@52" pad="52"/> +<connect gate="G$1" pin="VSSQ@6" pad="6"/> +<connect gate="G$1" pin="VSSQ@78" pad="78"/> +<connect gate="G$1" pin="VSSQ@84" pad="84"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MPN" value="IS45S32160F" constant="no"/> +<attribute name="SUPPLIER" value="ISSI" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="STM32F429BIT6" prefix="U"> +<description>STM32F429 Cortex-M4 CPU +180 MHz, 256 KB RAM, 2 MB Flash</description> +<gates> +<gate name="IO" symbol="STM32F429_LQFP-208_IO" x="30.48" y="-10.16"/> +<gate name="CFG" symbol="STM32F429_LQFP-208_CFG" x="-78.74" y="-12.7"/> +<gate name="PWR" symbol="STM32F429_LQFP-208_PWR" x="-154.94" y="-12.7"/> +<gate name="FMC" symbol="STM32F429_LQFP-208_FMC" x="129.54" y="5.08"/> +</gates> +<devices> +<device name="" package="LQFP-208"> +<connects> +<connect gate="CFG" pin="BOOT0@197" pad="197"/> +<connect gate="CFG" pin="NRST" pad="34"/> +<connect gate="CFG" pin="OSC_IN/PH0" pad="32"/> +<connect gate="CFG" pin="OSC_OUT/PH1" pad="33"/> +<connect gate="CFG" pin="PA13/JTMS-SWDIO" pad="147"/> +<connect gate="CFG" pin="PA14/JTCK-SWCLK" pad="159"/> +<connect gate="CFG" pin="PA15/JTDI" pad="160"/> +<connect gate="CFG" pin="PB2/BOOT1" pad="63"/> +<connect gate="CFG" pin="PB3/JTDO/TRACESWO" pad="192"/> +<connect gate="CFG" pin="PB4/NJTRST" pad="193"/> +<connect gate="CFG" pin="PDR_ON@203" pad="203"/> +<connect gate="CFG" pin="VREF+@41" pad="41"/> +<connect gate="FMC" pin="FMC_A0/PF0" pad="16"/> +<connect gate="FMC" pin="FMC_A1/PF1" pad="17"/> +<connect gate="FMC" pin="FMC_A10/PG0" pad="77"/> +<connect gate="FMC" pin="FMC_A11/PG1" pad="78"/> +<connect gate="FMC" pin="FMC_A12/PG2" pad="129"/> +<connect gate="FMC" pin="FMC_A13/PG3" pad="130"/> +<connect gate="FMC" pin="FMC_A14/PG4" pad="131"/> +<connect gate="FMC" pin="FMC_A15/PG5" pad="132"/> +<connect gate="FMC" pin="FMC_A16/PD11" pad="111"/> +<connect gate="FMC" pin="FMC_A17/PD12" pad="112"/> +<connect gate="FMC" pin="FMC_A18/PD13" pad="113"/> +<connect gate="FMC" pin="FMC_A19/PE3" pad="2"/> +<connect gate="FMC" pin="FMC_A2/PF2" pad="18"/> +<connect gate="FMC" pin="FMC_A20/PE4" pad="3"/> +<connect gate="FMC" pin="FMC_A21/PE5" pad="4"/> +<connect gate="FMC" pin="FMC_A22/PE6" pad="5"/> +<connect gate="FMC" pin="FMC_A23/PE2" pad="1"/> +<connect gate="FMC" pin="FMC_A24/PG13" pad="182"/> +<connect gate="FMC" pin="FMC_A25/PG14" pad="183"/> +<connect gate="FMC" pin="FMC_A3/PF3" pad="22"/> +<connect gate="FMC" pin="FMC_A4/PF4" pad="23"/> +<connect gate="FMC" pin="FMC_A5/PF5" pad="24"/> +<connect gate="FMC" pin="FMC_A6/PF12" pad="71"/> +<connect gate="FMC" pin="FMC_A7/PF13" pad="74"/> +<connect gate="FMC" pin="FMC_A8/PF14" pad="75"/> +<connect gate="FMC" pin="FMC_A9/PF15" pad="76"/> +<connect gate="FMC" pin="FMC_CLK/PD3" pad="167"/> +<connect gate="FMC" pin="FMC_NBL0/PE0" pad="200"/> +<connect gate="FMC" pin="FMC_NBL1/PE1" pad="201"/> +<connect gate="FMC" pin="FMC_NBL2/PI4" pad="205"/> +<connect gate="FMC" pin="FMC_NBL3/PI5" pad="206"/> +<connect gate="FMC" pin="FMC_NE1/PD7" pad="173"/> +<connect gate="FMC" pin="FMC_NL/PB7" pad="196"/> +<connect gate="FMC" pin="FMC_NOE/PD4" pad="168"/> +<connect gate="FMC" pin="FMC_NWAIT/PD6" pad="172"/> +<connect gate="FMC" pin="FMC_NWE/PD5" pad="169"/> +<connect gate="FMC" pin="PB5/FMC_SDCKE1" pad="194"/> +<connect gate="FMC" pin="PB6/FMC_SDNE1" pad="195"/> +<connect gate="FMC" pin="PC0/FMC_SDNWE" pad="35"/> +<connect gate="FMC" pin="PC2/FMC_SDNE0" pad="37"/> +<connect gate="FMC" pin="PC3/FMC_SDCKE0" pad="38"/> +<connect gate="FMC" pin="PD0/FMC_D2" pad="164"/> +<connect gate="FMC" pin="PD1/FMC_D3" pad="165"/> +<connect gate="FMC" pin="PD10/FMC_D15" pad="110"/> +<connect gate="FMC" pin="PD14/FMC_D0" pad="116"/> +<connect gate="FMC" pin="PD15/FMC_D1" pad="117"/> +<connect gate="FMC" pin="PD8/FMC_D13" pad="108"/> +<connect gate="FMC" pin="PD9/FMC_D14" pad="109"/> +<connect gate="FMC" pin="PE10/FMC_D7" pad="84"/> +<connect gate="FMC" pin="PE11/FMC_D8" pad="85"/> +<connect gate="FMC" pin="PE12/FMC_D9" pad="86"/> +<connect gate="FMC" pin="PE13/FMC_D10" pad="87"/> +<connect gate="FMC" pin="PE14/FMC_D11" pad="88"/> +<connect gate="FMC" pin="PE15/FMC_D12" pad="89"/> +<connect gate="FMC" pin="PE7/FMC_D4" pad="79"/> +<connect gate="FMC" pin="PE8/FMC_D5" pad="80"/> +<connect gate="FMC" pin="PE9/FMC_D6" pad="81"/> +<connect gate="FMC" pin="PF11/FMC_SDNRAS" pad="70"/> +<connect gate="FMC" pin="PG15/FMC_SDNCAS" pad="191"/> +<connect gate="FMC" pin="PG8/FMC_SDCLK" pad="135"/> +<connect gate="FMC" pin="PH10/FMC_D18" pad="100"/> +<connect gate="FMC" pin="PH11/FMC_D19" pad="101"/> +<connect gate="FMC" pin="PH12/FMC_D20" pad="102"/> +<connect gate="FMC" pin="PH13/FMC_D21" pad="151"/> +<connect gate="FMC" pin="PH14/FMC_D22" pad="152"/> +<connect gate="FMC" pin="PH15/FMC_D23" pad="153"/> +<connect gate="FMC" pin="PH8/FMC_D16" pad="98"/> +<connect gate="FMC" pin="PH9/FMC_D17" pad="99"/> +<connect gate="FMC" pin="PI0/FMC_D24" pad="154"/> +<connect gate="FMC" pin="PI1/FMC_D25" pad="155"/> +<connect gate="FMC" pin="PI10/FMC_D31" pad="12"/> +<connect gate="FMC" pin="PI2/FMC_D26" pad="156"/> +<connect gate="FMC" pin="PI3/FMC_D27" pad="157"/> +<connect gate="FMC" pin="PI6/FMC_D28" pad="207"/> +<connect gate="FMC" pin="PI7/FMC_D29" pad="208"/> +<connect gate="FMC" pin="PI9/FMC_D30" pad="11"/> +<connect gate="IO" pin="FMC_CD/PF9" pad="30"/> +<connect gate="IO" pin="FMC_INT2/PG6" pad="133"/> +<connect gate="IO" pin="FMC_INT3/PG7" pad="134"/> +<connect gate="IO" pin="FMC_INTR/PF10" pad="31"/> +<connect gate="IO" pin="FMC_NCE4_1/FMC_NE3/PG10" pad="179"/> +<connect gate="IO" pin="FMC_NCE4_2/PG11" pad="180"/> +<connect gate="IO" pin="FMC_NE2/FMC_NCE3/PG9" pad="178"/> +<connect gate="IO" pin="FMC_NE4/PG12" pad="181"/> +<connect gate="IO" pin="FMC_NIORD/PF6" pad="27"/> +<connect gate="IO" pin="FMC_NIOWR/PF8" pad="29"/> +<connect gate="IO" pin="FMC_NREG/PF7" pad="28"/> +<connect gate="IO" pin="FMC_SDCKE0/PH2" pad="46"/> +<connect gate="IO" pin="FMC_SDCKE1/PH7" pad="97"/> +<connect gate="IO" pin="FMC_SDNE1/PH6" pad="96"/> +<connect gate="IO" pin="I2C2_SCL/PH4" pad="48"/> +<connect gate="IO" pin="I2C2_SDA/PH5" pad="49"/> +<connect gate="IO" pin="PA4" pad="53"/> +<connect gate="IO" pin="PA8" pad="142"/> +<connect gate="IO" pin="PB0" pad="61"/> +<connect gate="IO" pin="PB1" pad="62"/> +<connect gate="IO" pin="PB10" pad="90"/> +<connect gate="IO" pin="PB11" pad="91"/> +<connect gate="IO" pin="PB12" pad="104"/> +<connect gate="IO" pin="PB8/I2C1_SCL" pad="198"/> +<connect gate="IO" pin="PB9/I2C1_SDA" pad="199"/> +<connect gate="IO" pin="PC1" pad="36"/> +<connect gate="IO" pin="PC13" pad="8"/> +<connect gate="IO" pin="PC14" pad="9"/> +<connect gate="IO" pin="PC15" pad="10"/> +<connect gate="IO" pin="PC4" pad="57"/> +<connect gate="IO" pin="PC5" pad="58"/> +<connect gate="IO" pin="PC6" pad="138"/> +<connect gate="IO" pin="PC7" pad="139"/> +<connect gate="IO" pin="PH3" pad="47"/> +<connect gate="IO" pin="PI11" pad="13"/> +<connect gate="IO" pin="PI12" pad="19"/> +<connect gate="IO" pin="PI13" pad="20"/> +<connect gate="IO" pin="PI14" pad="21"/> +<connect gate="IO" pin="PI15" pad="64"/> +<connect gate="IO" pin="PI8" pad="7"/> +<connect gate="IO" pin="PJ0" pad="65"/> +<connect gate="IO" pin="PJ1" pad="66"/> +<connect gate="IO" pin="PJ10" pad="122"/> +<connect gate="IO" pin="PJ11" pad="123"/> +<connect gate="IO" pin="PJ12" pad="174"/> +<connect gate="IO" pin="PJ13" pad="175"/> +<connect gate="IO" pin="PJ14" pad="176"/> +<connect gate="IO" pin="PJ15" pad="177"/> +<connect gate="IO" pin="PJ2" pad="67"/> +<connect gate="IO" pin="PJ3" pad="68"/> +<connect gate="IO" pin="PJ4" pad="69"/> +<connect gate="IO" pin="PJ5" pad="95"/> +<connect gate="IO" pin="PJ6" pad="118"/> +<connect gate="IO" pin="PJ7" pad="119"/> +<connect gate="IO" pin="PJ8" pad="120"/> +<connect gate="IO" pin="PJ9" pad="121"/> +<connect gate="IO" pin="PK0" pad="126"/> +<connect gate="IO" pin="PK1" pad="127"/> +<connect gate="IO" pin="PK2" pad="128"/> +<connect gate="IO" pin="PK3" pad="186"/> +<connect gate="IO" pin="PK4" pad="187"/> +<connect gate="IO" pin="PK5" pad="188"/> +<connect gate="IO" pin="PK6" pad="189"/> +<connect gate="IO" pin="PK7" pad="190"/> +<connect gate="IO" pin="SDIO_CK/PC12" pad="163"/> +<connect gate="IO" pin="SDIO_CMD/PD2" pad="166"/> +<connect gate="IO" pin="SDIO_D0/PC8" pad="140"/> +<connect gate="IO" pin="SDIO_D1/PC9" pad="141"/> +<connect gate="IO" pin="SDIO_D2/PC10" pad="161"/> +<connect gate="IO" pin="SDIO_D3/PC11" pad="162"/> +<connect gate="IO" pin="SPI1_MISO/PA6" pad="55"/> +<connect gate="IO" pin="SPI1_MOSI/PA7" pad="56"/> +<connect gate="IO" pin="SPI1_SCK/PA5" pad="54"/> +<connect gate="IO" pin="SPI2_MISO/PB14" pad="106"/> +<connect gate="IO" pin="SPI2_MOSI/PB15" pad="107"/> +<connect gate="IO" pin="SPI2_SCK/PB13" pad="105"/> +<connect gate="IO" pin="USART1_CTS/PA11" pad="145"/> +<connect gate="IO" pin="USART1_RTS/PA12" pad="146"/> +<connect gate="IO" pin="USART1_RX/PA10" pad="144"/> +<connect gate="IO" pin="USART1_TX/PA9" pad="143"/> +<connect gate="IO" pin="USART2_CTS/WKUP/PA0" pad="43"/> +<connect gate="IO" pin="USART2_RTS/PA1" pad="44"/> +<connect gate="IO" pin="USART2_RX/PA3" pad="50"/> +<connect gate="IO" pin="USART2_TX/PA2" pad="45"/> +<connect gate="PWR" pin="VBAT@6" pad="6"/> +<connect gate="PWR" pin="VCAP1@92" pad="92"/> +<connect gate="PWR" pin="VCAP2@148" pad="148"/> +<connect gate="PWR" pin="VDD@103" pad="103"/> +<connect gate="PWR" pin="VDD@115" pad="115"/> +<connect gate="PWR" pin="VDD@124" pad="124"/> +<connect gate="PWR" pin="VDD@137" pad="137"/> +<connect gate="PWR" pin="VDD@15" pad="15"/> +<connect gate="PWR" pin="VDD@150" pad="150"/> +<connect gate="PWR" pin="VDD@158" pad="158"/> +<connect gate="PWR" pin="VDD@171" pad="171"/> +<connect gate="PWR" pin="VDD@185" pad="185"/> +<connect gate="PWR" pin="VDD@204" pad="204"/> +<connect gate="PWR" pin="VDD@26" pad="26"/> +<connect gate="PWR" pin="VDD@39" pad="39"/> +<connect gate="PWR" pin="VDD@52" pad="52"/> +<connect gate="PWR" pin="VDD@59" pad="59"/> +<connect gate="PWR" pin="VDD@73" pad="73"/> +<connect gate="PWR" pin="VDD@83" pad="83"/> +<connect gate="PWR" pin="VDD@94" pad="94"/> +<connect gate="PWR" pin="VDDA@42" pad="42"/> +<connect gate="PWR" pin="VSS@114" pad="114"/> +<connect gate="PWR" pin="VSS@125" pad="125"/> +<connect gate="PWR" pin="VSS@136" pad="136"/> +<connect gate="PWR" pin="VSS@14" pad="14"/> +<connect gate="PWR" pin="VSS@149" pad="149"/> +<connect gate="PWR" pin="VSS@170" pad="170"/> +<connect gate="PWR" pin="VSS@184" pad="184"/> +<connect gate="PWR" pin="VSS@202" pad="202"/> +<connect gate="PWR" pin="VSS@25" pad="25"/> +<connect gate="PWR" pin="VSS@51" pad="51"/> +<connect gate="PWR" pin="VSS@60" pad="60"/> +<connect gate="PWR" pin="VSS@72" pad="72"/> +<connect gate="PWR" pin="VSS@82" pad="82"/> +<connect gate="PWR" pin="VSS@93" pad="93"/> +<connect gate="PWR" pin="VSSA@40" pad="40"/> +</connects> +<technologies> +<technology name=""> +<attribute name="OC_FARNELL" value="2469581" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="FT232H_SERIAL" prefix="U"> +<description>INTERFACE, USB - UART/FIFO</description> +<gates> +<gate name="G$1" symbol="FT232H_ASYNC_SERIAL" x="0" y="0"/> +</gates> +<devices> +<device name="" package="FT2323HL_LQFP48"> +<connects> +<connect gate="G$1" pin="!RESET" pad="34"/> +<connect gate="G$1" pin="ACBUS1" pad="25"/> +<connect gate="G$1" pin="ACBUS2" pad="26"/> +<connect gate="G$1" pin="ACBUS5" pad="29"/> +<connect gate="G$1" pin="ACBUS6" pad="30"/> +<connect gate="G$1" pin="ACBUS8" pad="32"/> +<connect gate="G$1" pin="ACBUS9" pad="33"/> +<connect gate="G$1" pin="AGND@4" pad="4"/> +<connect gate="G$1" pin="AGND@41" pad="41"/> +<connect gate="G$1" pin="AGND@9" pad="9"/> +<connect gate="G$1" pin="CTS#" pad="16"/> +<connect gate="G$1" pin="DCD#" pad="19"/> +<connect gate="G$1" pin="DM" pad="6"/> +<connect gate="G$1" pin="DP" pad="7"/> +<connect gate="G$1" pin="DSR#" pad="18"/> +<connect gate="G$1" pin="DTR#" pad="17"/> +<connect gate="G$1" pin="EECLK" pad="44"/> +<connect gate="G$1" pin="EECS" pad="45"/> +<connect gate="G$1" pin="EEDATA" pad="43"/> +<connect gate="G$1" pin="GND@10" pad="10"/> +<connect gate="G$1" pin="GND@11" pad="11"/> +<connect gate="G$1" pin="GND@22" pad="22"/> +<connect gate="G$1" pin="GND@23" pad="23"/> +<connect gate="G$1" pin="GND@35" pad="35"/> +<connect gate="G$1" pin="GND@36" pad="36"/> +<connect gate="G$1" pin="GND@47" pad="47"/> +<connect gate="G$1" pin="GND@48" pad="48"/> +<connect gate="G$1" pin="PWRSAV#" pad="31"/> +<connect gate="G$1" pin="REF" pad="5"/> +<connect gate="G$1" pin="RI#" pad="20"/> +<connect gate="G$1" pin="RTS#" pad="15"/> +<connect gate="G$1" pin="RXD" pad="14"/> +<connect gate="G$1" pin="RXLED#" pad="27"/> +<connect gate="G$1" pin="TEST" pad="42"/> +<connect gate="G$1" pin="TXD" pad="13"/> +<connect gate="G$1" pin="TXDEN" pad="21"/> +<connect gate="G$1" pin="TXLED#" pad="28"/> +<connect gate="G$1" pin="VCCA" pad="37"/> +<connect gate="G$1" pin="VCCD" pad="39"/> +<connect gate="G$1" pin="VCCIO@12" pad="12"/> +<connect gate="G$1" pin="VCCIO@24" pad="24"/> +<connect gate="G$1" pin="VCCIO@46" pad="46"/> +<connect gate="G$1" pin="VCCORE" pad="38"/> +<connect gate="G$1" pin="VPHY" pad="3"/> +<connect gate="G$1" pin="VPLL" pad="8"/> +<connect gate="G$1" pin="VREGIN" pad="40"/> +<connect gate="G$1" pin="XCSI" pad="1"/> +<connect gate="G$1" pin="XCSO" pad="2"/> +</connects> +<technologies> +<technology name=""> +<attribute name="OC_FARNELL" value="1870924" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="74xx-eu"> +<description><b>TTL Devices, 74xx Series with European Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic 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device="R0402" value="100"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="R87" library="resistor" deviceset="R-EU_" device="R0402" value="100"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="J2" library="SparkFun-Connectors" deviceset="M03X2" device="NO_SILK"/> +<part name="P+88" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="C214" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF"> +<attribute name="DIELECTRIC" value="X7R"/> +<attribute name="RATED_VOLTAGE" value="10V"/> +</part> +<part name="SUPPLY82" library="supply2" deviceset="GND" device=""/> +<part name="IC6" library="UsedComponents" deviceset="RCLAMP0502A" device="SC-89"/> +<part name="SUPPLY224" library="supply2" deviceset="GND" device=""/> +<part name="R88" library="resistor" deviceset="R-EU_" device="R0402" value="100"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="R89" library="resistor" deviceset="R-EU_" device="R0402" value="100"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="J3" library="SparkFun-Connectors" deviceset="M03X2" device="NO_SILK"/> +<part name="P+90" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="C215" library="resistor" deviceset="C-EU" device="C0402" value="0.1 uF"> +<attribute name="DIELECTRIC" value="X7R"/> +<attribute name="RATED_VOLTAGE" value="10V"/> +</part> +<part name="SUPPLY225" library="supply2" deviceset="GND" device=""/> +<part name="R90" library="resistor" deviceset="R-EU_" device="R0402" value="10k"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="P+89" library="SUPPLY1" deviceset="VCC" device=""/> +<part name="R91" library="resistor" deviceset="R-EU_" device="R0402" value="10k"> +<attribute name="TOLERANCE" value="5%"/> +</part> +<part name="P+91" library="SUPPLY1" deviceset="VCC" device=""/> +</parts> +<sheets> +<sheet> +<plain> +<text x="48.26" y="-27.94" size="5.08" layer="91">This document contains the electrical schematics for the Crypthech Alpha board. + +The latest version of these schematics can be found here: + +https://wiki.cryptech.is/browser/hardware/eagle/alpha + +For more information about the Alpha board including functionality, goals +and block diagram, please see: + +https://wiki.cryptech.is/wiki/AlphaBoardStrategy + +For more information about the Cryptech project, please see: +https://cryptech.is/</text> +</plain> +<instances> +<instance part="FRAME1" gate="G$1" x="22.86" y="-106.68"/> +<instance part="LOGO1" gate="G$1" x="337.82" y="-91.44"/> +</instances> +<busses> +</busses> +<nets> +</nets> +</sheet> +<sheet> +<description>Input power</description> +<plain> +<text x="43.18" y="74.93" size="2.54" layer="91">15V LDO powered from external 18V +and supplying stable 15V to noise source</text> +<text x="-175.26" y="60.96" size="3.81" layer="91">Main power input +18V DC</text> +<text x="-85.09" y="53.34" size="1.778" layer="91">To mitigate component ageing in the avalanche noise circuit, +this jumper can be used to decide if FPGA/ARM/None should +be allowed to turn off the entropy source +(default On through pull-up)</text> +<text x="111.76" y="33.02" size="1.778" layer="91">Max 3 ohm ESR</text> +<text x="-53.34" y="-22.86" size="2.54" layer="91">*) Intermediate Regulator: 18V -> 5V</text> +<text x="30.48" y="-104.14" size="1.778" layer="91">*) VCC_5V0 = 0.8V x (1 + 6.3/1.21) = 4.965V + +*) Current sharing not used + +*) SYNC is not used</text> +<text x="-83.82" y="78.74" size="3.81" layer="91">Entropy source power</text> +<text x="-172.72" y="20.32" size="1.778" layer="91">XXX verify symbol</text> +<text x="144.78" y="-121.92" size="2.54" layer="94">Input power</text> +</plain> +<instances> +<instance part="FRAME2" gate="G$1" x="-198.12" y="-142.24"/> +<instance part="JP1" gate="G$1" x="-165.1" y="35.56"/> +<instance part="SUPPLY1" gate="GND" x="-144.78" y="30.48" rot="MR0"/> +<instance part="U2" gate="G$1" x="78.74" y="48.26"/> +<instance part="SUPPLY17" gate="GND" x="60.96" y="27.94" rot="MR0"/> +<instance part="C11" gate="G$1" x="96.52" y="50.8" smashed="yes" rot="R180"> +<attribute name="NAME" x="99.06" y="50.8" size="1.6764" layer="95"/> +<attribute name="VALUE" x="99.06" y="48.26" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="99.06" y="45.72" size="1.27" layer="96"/> +<attribute name="RATED_VOLTAGE" x="96.52" y="50.8" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C12" gate="G$1" x="96.52" y="35.56" smashed="yes" rot="R180"> +<attribute name="NAME" x="99.06" y="35.56" size="1.6764" layer="95"/> +<attribute name="VALUE" x="99.06" y="33.02" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="99.06" y="30.48" size="1.27" layer="96"/> +<attribute name="RATED_VOLTAGE" x="96.52" y="35.56" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SUPPLY20" gate="GND" x="96.52" y="27.94" rot="MR0"/> +<instance part="C13" gate="G$1" x="109.22" y="43.18" smashed="yes"> +<attribute name="NAME" x="111.76" y="40.64" size="1.6764" layer="95" font="vector"/> +<attribute name="VALUE" x="111.76" y="38.1" size="1.6764" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="109.22" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="109.22" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY21" gate="GND" x="109.22" y="27.94" rot="MR0"/> +<instance part="R7" gate="G$1" x="12.7" y="55.88" rot="R270"> +<attribute name="TOLERANCE" x="12.7" y="55.88" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="P+1" gate="VCC" x="-144.78" y="53.34" smashed="yes"> +<attribute name="VALUE" x="-142.24" y="53.34" size="1.778" layer="96"/> +</instance> +<instance part="P+4" gate="VCC" x="48.26" y="66.04" smashed="yes"> +<attribute name="VALUE" x="50.8" y="66.04" size="1.778" layer="96"/> +</instance> +<instance part="P+6" gate="VCC" x="116.84" y="66.04" smashed="yes"> +<attribute name="VALUE" x="119.38" y="66.04" size="1.778" layer="96"/> +</instance> +<instance part="U1" gate="G$1" x="-10.16" y="-58.42"/> +<instance part="SUPPLY11" gate="GND" x="-12.7" y="-99.06"/> +<instance part="SUPPLY12" gate="GND" x="-7.62" y="-99.06"/> +<instance part="C5" gate="G$1" x="-38.1" y="-86.36"> +<attribute name="DIELECTRIC" x="-38.1" y="-86.36" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-38.1" y="-86.36" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-38.1" y="-86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY8" gate="GND" x="-38.1" y="-99.06"/> +<instance part="R3" gate="G$1" x="-53.34" y="-55.88"> +<attribute name="TOLERANCE" x="-53.34" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R2" gate="G$1" x="-66.04" y="-63.5" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="-62.23" y="-62.23" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="-67.5386" y="-67.31" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="-62.23" y="-71.12" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="R1" gate="G$1" x="-66.04" y="-48.26" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="-62.23" y="-45.72" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="-67.5386" y="-52.07" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="-62.23" y="-52.07" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="C1" gate="G$1" x="-116.84" y="-55.88"> +<attribute name="DIELECTRIC" x="-116.84" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-116.84" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-116.84" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY6" gate="GND" x="-66.04" y="-73.66"/> +<instance part="SUPPLY5" gate="GND" x="-81.28" y="-73.66"/> +<instance part="SUPPLY4" gate="GND" x="-96.52" y="-73.66"/> +<instance part="SUPPLY3" gate="GND" x="-106.68" y="-73.66"/> +<instance part="SUPPLY2" gate="GND" x="-116.84" y="-73.66"/> +<instance part="R8" gate="G$1" x="25.4" y="-50.8" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="29.21" y="-46.99" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="23.9014" y="-54.61" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="29.21" y="-54.61" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="R9" gate="G$1" x="25.4" y="-68.58" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="29.21" y="-64.77" size="1.778" layer="96" rot="R90"/> +<attribute name="NAME" x="23.9014" y="-72.39" size="1.778" layer="95" rot="R90"/> +<attribute name="VALUE" x="29.21" y="-73.66" size="1.778" layer="96" rot="R90"/> +</instance> +<instance part="SUPPLY13" gate="GND" x="25.4" y="-78.74"/> +<instance part="C9" gate="G$1" x="66.04" y="-50.8" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="66.04" y="-50.8" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="RATED_VOLTAGE" x="66.04" y="-50.8" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="69.215" y="-50.165" size="1.778" layer="95"/> +<attribute name="VALUE" x="68.58" y="-54.61" size="1.778" layer="96"/> +</instance> +<instance part="C6" gate="G$1" x="35.56" y="-48.26"> +<attribute name="RATED_VOLTAGE" x="35.56" y="-48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="35.56" y="-48.26" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="35.56" y="-48.26" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C10" gate="G$1" x="81.28" y="-50.8" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="81.28" y="-50.8" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="RATED_VOLTAGE" x="81.28" y="-50.8" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="84.455" y="-50.165" size="1.778" layer="95"/> +<attribute name="VALUE" x="83.82" y="-54.61" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY14" gate="GND" x="35.56" y="-60.96"/> +<instance part="SUPPLY16" gate="GND" x="50.8" y="-60.96"/> +<instance part="SUPPLY18" gate="GND" x="66.04" y="-60.96"/> +<instance part="SUPPLY19" gate="GND" x="81.28" y="-60.96"/> +<instance part="C4" gate="G$1" x="-81.28" y="-55.88"> +<attribute name="RATED_VOLTAGE" x="-81.28" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-81.28" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-81.28" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C2" gate="G$1" x="-106.68" y="-55.88"> +<attribute name="DIELECTRIC" x="-106.68" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-106.68" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-106.68" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C3" gate="G$1" x="-96.52" y="-55.88"> +<attribute name="DIELECTRIC" x="-96.52" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-96.52" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-96.52" y="-55.88" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C8" gate="G$1" x="50.8" y="-48.26"> +<attribute name="DIELECTRIC" x="50.8" y="-48.26" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="50.8" y="-48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="50.8" y="-48.26" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+2" gate="VCC" x="-121.92" y="-30.48" smashed="yes"> +<attribute name="VALUE" x="-119.38" y="-30.48" size="1.778" layer="96"/> +</instance> +<instance part="P+3" gate="VCC" x="12.7" y="66.04" smashed="yes"> +<attribute name="VALUE" x="15.24" y="66.04" size="1.778" layer="96"/> +</instance> +<instance part="Q1" gate="G$1" x="-22.86" y="39.37"/> +<instance part="R6" gate="G$1" x="-33.02" y="26.67" rot="R270"> +<attribute name="TOLERANCE" x="-33.02" y="26.67" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="R5" gate="G$1" x="-43.18" y="36.83"> +<attribute name="TOLERANCE" x="-43.18" y="36.83" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY9" gate="GND" x="-33.02" y="13.97" rot="MR0"/> +<instance part="SUPPLY10" gate="GND" x="-12.7" y="13.97" rot="MR0"/> +<instance part="JP2" gate="A" x="-1.27" y="48.26" rot="R90"/> +<instance part="C7" gate="G$1" x="48.26" y="38.1" smashed="yes"> +<attribute name="NAME" x="44.45" y="38.1" size="1.6764" layer="95" font="vector" rot="R180"/> +<attribute name="VALUE" x="44.45" y="35.56" size="1.6764" layer="96" font="vector" rot="R180"/> +<attribute name="DIELECTRIC" x="48.26" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY15" gate="GND" x="48.26" y="27.94" rot="MR0"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="JP1" gate="G$1" pin="GND"/> +<wire x1="-162.56" y1="38.1" x2="-144.78" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-144.78" y1="38.1" x2="-144.78" y2="33.02" width="0.1524" layer="91"/> +<pinref part="SUPPLY1" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="U2" gate="G$1" pin="GND"/> +<pinref part="SUPPLY17" gate="GND" pin="GND"/> +<wire x1="63.5" y1="40.64" x2="60.96" y2="40.64" width="0.1524" layer="91"/> +<wire x1="60.96" y1="40.64" x2="60.96" y2="30.48" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C12" gate="G$1" pin="1"/> +<pinref part="SUPPLY20" gate="GND" pin="GND"/> +<wire x1="96.52" y1="33.02" x2="96.52" y2="30.48" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C13" gate="G$1" pin="2"/> +<pinref part="SUPPLY21" gate="GND" pin="GND"/> +<wire x1="109.22" y1="38.1" x2="109.22" y2="30.48" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY11" gate="GND" pin="GND"/> +<pinref part="U1" gate="G$1" pin="PGND"/> +<wire x1="-12.7" y1="-96.52" x2="-12.7" y2="-86.36" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY12" gate="GND" pin="GND"/> +<pinref part="U1" gate="G$1" pin="AGND"/> +<wire x1="-7.62" y1="-96.52" x2="-7.62" y2="-86.36" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY8" gate="GND" pin="GND"/> +<pinref part="C5" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="-96.52" x2="-38.1" y2="-91.44" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R2" gate="G$1" pin="1"/> +<pinref part="SUPPLY6" gate="GND" pin="GND"/> +<wire x1="-66.04" y1="-71.12" x2="-66.04" y2="-68.58" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY2" gate="GND" pin="GND"/> +<pinref part="C1" gate="G$1" pin="2"/> +<wire x1="-116.84" y1="-71.12" x2="-116.84" y2="-60.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY3" gate="GND" pin="GND"/> +<wire x1="-106.68" y1="-71.12" x2="-106.68" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C2" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY4" gate="GND" pin="GND"/> +<wire x1="-96.52" y1="-71.12" x2="-96.52" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C3" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY5" gate="GND" pin="GND"/> +<wire x1="-81.28" y1="-71.12" x2="-81.28" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C4" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="R9" gate="G$1" pin="1"/> +<pinref part="SUPPLY13" gate="GND" pin="GND"/> +<wire x1="25.4" y1="-73.66" x2="25.4" y2="-76.2" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY14" gate="GND" pin="GND"/> +<pinref part="C6" gate="G$1" pin="2"/> +<wire x1="35.56" y1="-58.42" x2="35.56" y2="-53.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY16" gate="GND" pin="GND"/> +<wire x1="50.8" y1="-58.42" x2="50.8" y2="-53.34" width="0.1524" layer="91"/> +<pinref part="C8" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY18" gate="GND" pin="GND"/> +<pinref part="C9" gate="G$1" pin="-"/> +<wire x1="66.04" y1="-58.42" x2="66.04" y2="-53.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY19" gate="GND" pin="GND"/> +<pinref part="C10" gate="G$1" pin="-"/> +<wire x1="81.28" y1="-58.42" x2="81.28" y2="-53.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY9" gate="GND" pin="GND"/> +<pinref part="R6" gate="G$1" pin="2"/> +<wire x1="-33.02" y1="16.51" x2="-33.02" y2="21.59" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="Q1" gate="G$1" pin="S"/> +<wire x1="-17.78" y1="36.83" x2="-12.7" y2="36.83" width="0.1524" layer="91"/> +<pinref part="SUPPLY10" gate="GND" pin="GND"/> +<wire x1="-12.7" y1="36.83" x2="-12.7" y2="16.51" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY15" gate="GND" pin="GND"/> +<pinref part="C7" gate="G$1" pin="2"/> +<wire x1="48.26" y1="30.48" x2="48.26" y2="33.02" width="0.1524" layer="91"/> +</segment> +</net> +<net name="PWR_18V" class="0"> +<segment> +<pinref part="JP1" gate="G$1" pin="PWR"/> +<wire x1="-162.56" y1="43.18" x2="-144.78" y2="43.18" width="0.1524" layer="91"/> +<label x="-142.24" y="49.53" size="1.778" layer="95"/> +<pinref part="P+1" gate="VCC" pin="VCC"/> +<wire x1="-144.78" y1="43.18" x2="-144.78" y2="50.8" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="48.26" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/> +<label x="50.8" y="63.5" size="1.778" layer="95"/> +<pinref part="U2" gate="G$1" pin="IN"/> +<pinref part="P+4" gate="VCC" pin="VCC"/> +<wire x1="48.26" y1="55.88" x2="48.26" y2="63.5" width="0.1524" layer="91"/> +<pinref part="C7" gate="G$1" pin="1"/> +<wire x1="48.26" y1="55.88" x2="48.26" y2="40.64" width="0.1524" layer="91"/> +<junction x="48.26" y="55.88"/> +</segment> +<segment> +<pinref part="U1" gate="G$1" pin="VIN"/> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="-43.18" x2="-66.04" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="-40.64" x2="-33.02" y2="-40.64" width="0.1524" layer="91"/> +<pinref part="C1" gate="G$1" pin="1"/> +<wire x1="-116.84" y1="-53.34" x2="-116.84" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-116.84" y1="-40.64" x2="-106.68" y2="-40.64" width="0.1524" layer="91"/> +<junction x="-66.04" y="-40.64"/> +<wire x1="-106.68" y1="-40.64" x2="-96.52" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-40.64" x2="-81.28" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="-40.64" x2="-66.04" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-106.68" y1="-53.34" x2="-106.68" y2="-40.64" width="0.1524" layer="91"/> +<junction x="-106.68" y="-40.64"/> +<wire x1="-81.28" y1="-53.34" x2="-81.28" y2="-40.64" width="0.1524" layer="91"/> +<junction x="-81.28" y="-40.64"/> +<junction x="-116.84" y="-40.64"/> +<pinref part="C4" gate="G$1" pin="1"/> +<pinref part="C2" gate="G$1" pin="1"/> +<pinref part="C3" gate="G$1" pin="1"/> +<wire x1="-96.52" y1="-53.34" x2="-96.52" y2="-40.64" width="0.1524" layer="91"/> +<junction x="-96.52" y="-40.64"/> +<pinref part="P+2" gate="VCC" pin="VCC"/> +<wire x1="-116.84" y1="-40.64" x2="-121.92" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="-121.92" y1="-40.64" x2="-121.92" y2="-33.02" width="0.1524" layer="91"/> +<label x="-119.38" y="-33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R7" gate="G$1" pin="1"/> +<wire x1="12.7" y1="63.5" x2="12.7" y2="60.96" width="0.1524" layer="91"/> +<pinref part="P+3" gate="VCC" pin="VCC"/> +<label x="15.24" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$1" class="0"> +<segment> +<pinref part="C11" gate="G$1" pin="1"/> +<pinref part="U2" gate="G$1" pin="ADJ"/> +<wire x1="96.52" y1="48.26" x2="93.98" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$2" class="0"> +<segment> +<pinref part="C12" gate="G$1" pin="2"/> +<pinref part="U2" gate="G$1" pin="REF/BYP"/> +<wire x1="96.52" y1="40.64" x2="93.98" y2="40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="15V_LDO_ENABLE" class="0"> +<segment> +<pinref part="U2" gate="G$1" pin="!SHDN"/> +<wire x1="63.5" y1="48.26" x2="12.7" y2="48.26" width="0.1524" layer="91"/> +<pinref part="JP2" gate="A" pin="1"/> +<label x="20.32" y="49.53" size="1.778" layer="95"/> +<pinref part="R7" gate="G$1" pin="2"/> +<wire x1="12.7" y1="50.8" x2="12.7" y2="48.26" width="0.1524" layer="91"/> +<wire x1="6.35" y1="48.26" x2="12.7" y2="48.26" width="0.1524" layer="91"/> +<junction x="12.7" y="48.26"/> +</segment> +</net> +<net name="15V_STABLE" class="0"> +<segment> +<pinref part="U2" gate="G$1" pin="OUT"/> +<wire x1="93.98" y1="55.88" x2="96.52" y2="55.88" width="0.1524" layer="91"/> +<label x="119.38" y="55.88" size="1.778" layer="95" xref="yes"/> +<pinref part="C11" gate="G$1" pin="2"/> +<wire x1="96.52" y1="55.88" x2="109.22" y2="55.88" width="0.1524" layer="91"/> +<junction x="96.52" y="55.88"/> +<pinref part="C13" gate="G$1" pin="1"/> +<wire x1="109.22" y1="55.88" x2="116.84" y2="55.88" width="0.1524" layer="91"/> +<wire x1="116.84" y1="55.88" x2="119.38" y2="55.88" width="0.1524" layer="91"/> +<wire x1="109.22" y1="45.72" x2="109.22" y2="55.88" width="0.1524" layer="91"/> +<junction x="109.22" y="55.88"/> +<pinref part="P+6" gate="VCC" pin="VCC"/> +<wire x1="116.84" y1="63.5" x2="116.84" y2="55.88" width="0.1524" layer="91"/> +<junction x="116.84" y="55.88"/> +<label x="119.38" y="63.5" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$52" class="0"> +<segment> +<pinref part="C5" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-83.82" x2="-38.1" y2="-76.2" width="0.1524" layer="91"/> +<pinref part="U1" gate="G$1" pin="SS/TRK"/> +<wire x1="-38.1" y1="-76.2" x2="-33.02" y2="-76.2" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$54" class="0"> +<segment> +<pinref part="R3" gate="G$1" pin="1"/> +<wire x1="-58.42" y1="-55.88" x2="-66.04" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="-55.88" x2="-66.04" y2="-53.34" width="0.1524" layer="91"/> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="-58.42" x2="-66.04" y2="-55.88" width="0.1524" layer="91"/> +<junction x="-66.04" y="-55.88"/> +</segment> +</net> +<net name="N$55" class="0"> +<segment> +<pinref part="R3" gate="G$1" pin="2"/> +<pinref part="U1" gate="G$1" pin="EN"/> +<wire x1="-48.26" y1="-55.88" x2="-33.02" y2="-55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$56" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="FB"/> +<wire x1="12.7" y1="-60.96" x2="25.4" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="R8" gate="G$1" pin="1"/> +<wire x1="25.4" y1="-60.96" x2="25.4" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="R9" gate="G$1" pin="2"/> +<wire x1="25.4" y1="-63.5" x2="25.4" y2="-60.96" width="0.1524" layer="91"/> +<junction x="25.4" y="-60.96"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<pinref part="U1" gate="G$1" pin="VOUT"/> +<pinref part="R8" gate="G$1" pin="2"/> +<junction x="25.4" y="-40.64"/> +<wire x1="25.4" y1="-45.72" x2="25.4" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="50.8" y1="-45.72" x2="50.8" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="50.8" y1="-40.64" x2="35.56" y2="-40.64" width="0.1524" layer="91"/> +<pinref part="C9" gate="G$1" pin="+"/> +<wire x1="35.56" y1="-40.64" x2="25.4" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="25.4" y1="-40.64" x2="12.7" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="66.04" y1="-48.26" x2="66.04" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="66.04" y1="-40.64" x2="50.8" y2="-40.64" width="0.1524" layer="91"/> +<junction x="50.8" y="-40.64"/> +<pinref part="C10" gate="G$1" pin="+"/> +<wire x1="81.28" y1="-48.26" x2="81.28" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="81.28" y1="-40.64" x2="66.04" y2="-40.64" width="0.1524" layer="91"/> +<junction x="66.04" y="-40.64"/> +<wire x1="81.28" y1="-40.64" x2="104.14" y2="-40.64" width="0.1524" layer="91"/> +<junction x="81.28" y="-40.64"/> +<pinref part="C8" gate="G$1" pin="1"/> +<label x="91.44" y="-38.1" size="1.778" layer="95"/> +<pinref part="C6" gate="G$1" pin="1"/> +<wire x1="35.56" y1="-45.72" x2="35.56" y2="-40.64" width="0.1524" layer="91"/> +<junction x="35.56" y="-40.64"/> +</segment> +</net> +<net name="N$11" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="2"/> +<pinref part="Q1" gate="G$1" pin="G"/> +<wire x1="-38.1" y1="36.83" x2="-33.02" y2="36.83" width="0.1524" layer="91"/> +<pinref part="R6" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="36.83" x2="-27.94" y2="36.83" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="31.75" x2="-33.02" y2="36.83" width="0.1524" layer="91"/> +<junction x="-33.02" y="36.83"/> +</segment> +</net> +<net name="N$14" class="0"> +<segment> +<pinref part="Q1" gate="G$1" pin="D"/> +<wire x1="-17.78" y1="41.91" x2="-12.7" y2="41.91" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="41.91" x2="-12.7" y2="48.26" width="0.1524" layer="91"/> +<pinref part="JP2" gate="A" pin="2"/> +<wire x1="-8.89" y1="48.26" x2="-12.7" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_ENTROPY_DISABLE" class="0"> +<segment> +<pinref part="R5" gate="G$1" pin="1"/> +<wire x1="-48.26" y1="36.83" x2="-55.88" y2="36.83" width="0.1524" layer="91"/> +<label x="-55.88" y="36.83" size="1.778" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Noise source</description> +<plain> +<text x="66.04" y="63.5" size="3.81" layer="91">Digitizer</text> +<text x="-147.32" y="63.5" size="3.81" layer="91">Noise generator</text> +<text x="-121.92" y="0" size="1.778" layer="91" rot="R90">Noisy diode</text> +<text x="-55.88" y="63.5" size="3.81" layer="91">Amplifier</text> +<text x="-147.32" y="-35.56" size="1.778" layer="91">AGND is connected to GND on the board using polygons +(found no other good way) - not visible in schematics.</text> +<text x="10.16" y="-36.83" size="1.778" layer="91">This whole sheets circuitry should be as shielded as possible. +Solid isolated ground plane and internal planes connected +to the rest of the board at a single point is expected.</text> +<text x="121.92" y="-91.44" size="2.54" layer="94">Noise source</text> +</plain> +<instances> +<instance part="C16" gate="G$1" x="53.34" y="22.86" smashed="yes" rot="R180"> +<attribute name="NAME" x="50.8" y="20.32" size="1.778" layer="95" rot="R270"/> +<attribute name="VALUE" x="55.88" y="27.94" size="1.778" layer="96" rot="R270"/> +<attribute name="DIELECTRIC" x="53.34" y="22.86" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="53.34" y="22.86" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="53.34" y="22.86" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="U3" gate="A" x="81.28" y="30.48"/> +<instance part="P+9" gate="VCC" x="60.96" y="55.88" smashed="yes"/> +<instance part="SUPPLY25" gate="GND" x="60.96" y="5.08"/> +<instance part="Q2" gate="G$1" x="-118.11" y="5.08" smashed="yes" rot="R180"> +<attribute name="NAME" x="-114.3" y="2.54" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-120.65" y="-2.54" size="1.778" layer="96"/> +</instance> +<instance part="T1" gate="G$1" x="-102.87" y="5.08" smashed="yes"> +<attribute name="NAME" x="-97.79" y="7.62" size="1.778" layer="95"/> +<attribute name="VALUE" x="-97.79" y="5.08" size="1.778" layer="96"/> +</instance> +<instance part="C14" gate="G$1" x="-128.27" y="-5.08" smashed="yes" rot="R180"> +<attribute name="NAME" x="-139.7" y="-2.54" size="1.778" layer="95"/> +<attribute name="VALUE" x="-139.7" y="-5.08" size="1.778" layer="96"/> +<attribute name="RATED_VOLTAGE" x="-139.7" y="-7.62" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="-128.27" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="TOLERANCE" x="-128.27" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R10" gate="G$1" x="-110.49" y="20.32" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-109.22" y="15.24" size="1.778" layer="96"/> +<attribute name="NAME" x="-109.22" y="25.4" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-116.84" y="15.24" size="1.778" layer="96"/> +</instance> +<instance part="R11" gate="G$1" x="-100.33" y="27.94" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="-91.44" y="27.94" size="1.778" layer="96"/> +<attribute name="NAME" x="-96.52" y="30.48" size="1.778" layer="95"/> +<attribute name="VALUE" x="-96.52" y="27.94" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY23" gate="GND" x="-100.33" y="-11.43"/> +<instance part="TP1" gate="G$1" x="-92.71" y="25.4" smashed="yes"> +<attribute name="NAME" x="-95.25" y="17.78" size="1.778" layer="95"/> +<attribute name="TP_SIGNAL_NAME" x="-91.44" y="24.13" size="1.778" layer="97"/> +</instance> +<instance part="S1" gate="G$1" x="-137.16" y="29.21" smashed="yes"> +<attribute name="NAME" x="-144.78" y="40.64" size="1.778" layer="95"/> +<attribute name="VALUE" x="-137.16" y="39.37" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY22" gate="GND" x="-148.59" y="8.89"/> +<instance part="C15" gate="G$1" x="-30.48" y="20.32" smashed="yes" rot="R90"> +<attribute name="NAME" x="-33.02" y="15.24" size="1.778" layer="95"/> +<attribute name="VALUE" x="-33.02" y="12.7" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="-30.48" y="20.32" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="20.32" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="20.32" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R12" gate="G$1" x="-12.7" y="30.48" smashed="yes"> +<attribute name="NAME" x="-20.32" y="27.94" size="1.778" layer="95"/> +<attribute name="VALUE" x="-20.32" y="25.4" size="1.778" layer="96"/> +<attribute name="TOLERANCE" x="-12.7" y="25.4" size="1.778" layer="96"/> +</instance> +<instance part="T2" gate="G$1" x="-7.62" y="20.32" smashed="yes"> +<attribute name="NAME" x="-2.54" y="20.32" size="1.778" layer="95"/> +<attribute name="VALUE" x="-2.54" y="17.78" size="1.778" layer="96"/> +</instance> +<instance part="R13" gate="G$1" x="-5.08" y="45.72" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="2.54" y="43.18" size="1.778" layer="96"/> +<attribute name="NAME" x="-2.54" y="45.72" size="1.778" layer="95"/> +<attribute name="VALUE" x="-2.54" y="43.18" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY24" gate="GND" x="-5.08" y="10.16"/> +<instance part="P+8" gate="VCC" x="-5.08" y="55.88" smashed="yes"/> +<instance part="D1" gate="G$1" x="-12.7" y="38.1" smashed="yes"> +<attribute name="NAME" x="-14.986" y="40.005" size="1.778" layer="95"/> +<attribute name="VALUE" x="-14.986" y="34.671" size="1.778" layer="96"/> +</instance> +<instance part="TP2" gate="G$1" x="7.62" y="35.56"/> +<instance part="FRAME3" gate="G$1" x="-220.98" y="-111.76"/> +<instance part="P+7" gate="VCC" x="-100.33" y="49.53" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="U3" gate="A" pin="VCC"/> +<pinref part="P+9" gate="VCC" pin="VCC"/> +<wire x1="63.5" y1="35.56" x2="60.96" y2="35.56" width="0.1524" layer="91"/> +<wire x1="60.96" y1="35.56" x2="60.96" y2="53.34" width="0.1524" layer="91"/> +<junction x="60.96" y="35.56"/> +<pinref part="C16" gate="G$1" pin="2"/> +<wire x1="53.34" y1="35.56" x2="53.34" y2="27.94" width="0.1524" layer="91"/> +<wire x1="60.96" y1="35.56" x2="53.34" y2="35.56" width="0.1524" layer="91"/> +<label x="63.5" y="55.88" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R13" gate="G$1" pin="2"/> +<wire x1="-5.08" y1="50.8" x2="-5.08" y2="53.34" width="0.1524" layer="91"/> +<pinref part="P+8" gate="VCC" pin="VCC"/> +<label x="-2.54" y="55.88" size="1.778" layer="95"/> +</segment> +</net> +<net name="AMPLIFIED" class="0"> +<segment> +<wire x1="63.5" y1="30.48" x2="33.02" y2="30.48" width="0.1524" layer="91"/> +<label x="33.02" y="30.48" size="1.27" layer="95"/> +<pinref part="U3" gate="A" pin="IN_A"/> +</segment> +<segment> +<wire x1="7.62" y1="30.48" x2="26.67" y2="30.48" width="0.1524" layer="91"/> +<label x="16.51" y="30.48" size="1.27" layer="95"/> +<wire x1="-5.08" y1="40.64" x2="-5.08" y2="38.1" width="0.1524" layer="91"/> +<junction x="-5.08" y="30.48"/> +<junction x="-5.08" y="30.48"/> +<pinref part="T2" gate="G$1" pin="C"/> +<wire x1="-5.08" y1="38.1" x2="-5.08" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="30.48" x2="-5.08" y2="25.4" width="0.1524" layer="91"/> +<pinref part="R13" gate="G$1" pin="1"/> +<wire x1="-5.08" y1="30.48" x2="7.62" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R12" gate="G$1" pin="2"/> +<wire x1="-7.62" y1="30.48" x2="-5.08" y2="30.48" width="0.1524" layer="91"/> +<pinref part="D1" gate="G$1" pin="C"/> +<wire x1="-10.16" y1="38.1" x2="-5.08" y2="38.1" width="0.1524" layer="91"/> +<junction x="-5.08" y="38.1"/> +<wire x1="7.62" y1="30.48" x2="7.62" y2="33.02" width="0.1524" layer="91"/> +<pinref part="TP2" gate="G$1" pin="TP"/> +<junction x="7.62" y="30.48"/> +</segment> +</net> +<net name="DIGITIZED_NOISE" class="0"> +<segment> +<label x="111.76" y="35.56" size="1.27" layer="95" xref="yes"/> +<wire x1="111.76" y1="35.56" x2="99.06" y2="35.56" width="0.1524" layer="91"/> +<pinref part="U3" gate="A" pin="OUT_Y"/> +</segment> +</net> +<net name="AGND" class="0"> +<segment> +<pinref part="U3" gate="A" pin="GND"/> +<pinref part="SUPPLY25" gate="GND" pin="GND"/> +<wire x1="63.5" y1="20.32" x2="60.96" y2="20.32" width="0.1524" layer="91"/> +<wire x1="60.96" y1="20.32" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<pinref part="C16" gate="G$1" pin="1"/> +<wire x1="60.96" y1="10.16" x2="60.96" y2="7.62" width="0.1524" layer="91"/> +<wire x1="53.34" y1="20.32" x2="53.34" y2="10.16" width="0.1524" layer="91"/> +<wire x1="53.34" y1="10.16" x2="60.96" y2="10.16" width="0.1524" layer="91"/> +<junction x="60.96" y="10.16"/> +</segment> +<segment> +<pinref part="SUPPLY22" gate="GND" pin="GND"/> +<pinref part="S1" gate="G$1" pin="GND"/> +<wire x1="-147.32" y1="31.75" x2="-148.59" y2="31.75" width="0.1524" layer="91"/> +<wire x1="-148.59" y1="31.75" x2="-148.59" y2="11.43" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="T2" gate="G$1" pin="E"/> +<pinref part="SUPPLY24" gate="GND" pin="GND"/> +<wire x1="-5.08" y1="15.24" x2="-5.08" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="NOISE_OUT" class="0"> +<segment> +<pinref part="Q2" gate="G$1" pin="B"/> +<pinref part="T1" gate="G$1" pin="B"/> +<wire x1="-115.57" y1="5.08" x2="-105.41" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="NOISE_IN" class="0"> +<segment> +<pinref part="R10" gate="G$1" pin="2"/> +<pinref part="C14" gate="G$1" pin="2"/> +<wire x1="-128.27" y1="0" x2="-128.27" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-128.27" y1="20.32" x2="-120.65" y2="20.32" width="0.1524" layer="91"/> +<pinref part="Q2" gate="G$1" pin="E"/> +<wire x1="-120.65" y1="20.32" x2="-115.57" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-120.65" y1="10.16" x2="-120.65" y2="20.32" width="0.1524" layer="91"/> +<junction x="-120.65" y="20.32"/> +</segment> +</net> +<net name="RAW_NOISE" class="0"> +<segment> +<pinref part="R10" gate="G$1" pin="1"/> +<wire x1="-105.41" y1="20.32" x2="-100.33" y2="20.32" width="0.1524" layer="91"/> +<pinref part="T1" gate="G$1" pin="C"/> +<wire x1="-100.33" y1="20.32" x2="-100.33" y2="10.16" width="0.1524" layer="91"/> +<pinref part="R11" gate="G$1" pin="2"/> +<wire x1="-100.33" y1="20.32" x2="-100.33" y2="22.86" width="0.1524" layer="91"/> +<label x="-76.2" y="20.32" size="1.27" layer="95"/> +<junction x="-100.33" y="20.32"/> +<wire x1="-100.33" y1="20.32" x2="-92.71" y2="20.32" width="0.1524" layer="91"/> +<pinref part="TP1" gate="G$1" pin="TP"/> +<wire x1="-92.71" y1="20.32" x2="-66.04" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-92.71" y1="20.32" x2="-92.71" y2="22.86" width="0.1524" layer="91"/> +<junction x="-92.71" y="20.32"/> +</segment> +<segment> +<pinref part="C15" gate="G$1" pin="1"/> +<wire x1="-33.02" y1="20.32" x2="-57.15" y2="20.32" width="0.1524" layer="91"/> +<label x="-57.15" y="20.32" size="1.27" layer="95"/> +</segment> +</net> +<net name="AMP_P1" class="0"> +<segment> +<pinref part="D1" gate="G$1" pin="A"/> +<wire x1="-15.24" y1="38.1" x2="-22.86" y2="38.1" width="0.1524" layer="91"/> +<pinref part="C15" gate="G$1" pin="2"/> +<pinref part="R12" gate="G$1" pin="1"/> +<wire x1="-25.4" y1="20.32" x2="-22.86" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="20.32" x2="-22.86" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="30.48" x2="-17.78" y2="30.48" width="0.1524" layer="91"/> +<pinref part="T2" gate="G$1" pin="B"/> +<wire x1="-10.16" y1="20.32" x2="-22.86" y2="20.32" width="0.1524" layer="91"/> +<junction x="-22.86" y="20.32"/> +<wire x1="-22.86" y1="38.1" x2="-22.86" y2="30.48" width="0.1524" layer="91"/> +<junction x="-22.86" y="30.48"/> +</segment> +</net> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY23" gate="GND" pin="GND"/> +<pinref part="T1" gate="G$1" pin="E"/> +<wire x1="-100.33" y1="0" x2="-100.33" y2="-8.89" width="0.1524" layer="91"/> +<wire x1="-128.27" y1="-7.62" x2="-128.27" y2="-8.89" width="0.1524" layer="91"/> +<wire x1="-128.27" y1="-8.89" x2="-100.33" y2="-8.89" width="0.1524" layer="91"/> +<junction x="-100.33" y="-8.89"/> +<pinref part="C14" gate="G$1" pin="1"/> +</segment> +</net> +<net name="15V_STABLE" class="0"> +<segment> +<pinref part="P+7" gate="VCC" pin="VCC"/> +<pinref part="R11" gate="G$1" pin="1"/> +<label x="-97.79" y="46.99" size="1.778" layer="95"/> +<wire x1="-100.33" y1="33.02" x2="-100.33" y2="46.99" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>ARM Configuration</description> +<plain> +<text x="165.1" y="152.4" size="1.778" layer="91">ST 4488 §5.1 +BOOT0 to GND boots +Main Flash Memory</text> +<text x="58.42" y="200.66" size="1.778" layer="91">ST AN4488 §4.1.2 +suggests 25 MHz for good +Ethernet, USB OTG and I2C</text> +<text x="309.88" y="228.6" size="1.778" layer="91">SWD program/debug</text> +<text x="322.58" y="182.88" size="1.778" layer="91">ST AN4488 §2.3.3 +Reset circuit not needed, +but pull-down cap +recommended.</text> +<text x="157.48" y="198.12" size="1.778" layer="91" rot="R180">PDR_ON high enables +internal power regulator</text> +<text x="81.28" y="193.04" size="1.778" layer="91">CL 10pF</text> +<text x="45.72" y="251.46" size="3.81" layer="91">Basic configuration, STM32</text> +<text x="347.98" y="63.5" size="2.54" layer="94">ARM configuration</text> +</plain> +<instances> +<instance part="U4" gate="CFG" x="198.12" y="185.42"/> +<instance part="C18" gate="G$1" x="96.52" y="185.42" smashed="yes" rot="R180"> +<attribute name="NAME" x="99.06" y="187.96" size="1.778" layer="95"/> +<attribute name="VALUE" x="99.06" y="185.42" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="99.06" y="182.88" size="1.6764" layer="96"/> +</instance> +<instance part="C17" gate="G$1" x="55.88" y="185.42" smashed="yes" rot="R180"> +<attribute name="NAME" x="45.72" y="187.96" size="1.778" layer="95"/> +<attribute name="VALUE" x="45.72" y="185.42" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="45.72" y="182.88" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY26" gate="GND" x="55.88" y="177.8"/> +<instance part="SUPPLY29" gate="GND" x="96.52" y="177.8"/> +<instance part="J1" gate="G$1" x="327.66" y="205.74" smashed="yes" rot="R180"> +<attribute name="NAME" x="327.66" y="218.44" size="1.778" layer="95" rot="R180"/> +</instance> +<instance part="SUPPLY30" gate="GND" x="160.02" y="147.32"/> +<instance part="R15" gate="G$1" x="160.02" y="157.48" rot="R90"> +<attribute name="TOLERANCE" x="160.02" y="157.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C20" gate="G$1" x="317.5" y="193.04" smashed="yes"> +<attribute name="NAME" x="306.07" y="194.31" size="1.778" layer="95" font="vector"/> +<attribute name="VALUE" x="306.07" y="191.77" size="1.778" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="317.5" y="193.04" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="317.5" y="193.04" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY33" gate="GND" x="317.5" y="185.42"/> +<instance part="R14" gate="G$1" x="63.5" y="180.34" rot="R90"/> +<instance part="SUPPLY32" gate="GND" x="302.26" y="185.42"/> +<instance part="P+11" gate="VCC" x="294.64" y="223.52" smashed="yes"/> +<instance part="P+10" gate="VCC" x="160.02" y="220.98" smashed="yes"/> +<instance part="LED3" gate="G$1" x="335.28" y="144.78" smashed="yes" rot="R90"> +<attribute name="NAME" x="352.552" y="145.796" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="370.332" y="145.415" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED1" gate="G$1" x="330.2" y="142.24" smashed="yes" rot="R90"> +<attribute name="NAME" x="352.552" y="143.256" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="370.332" y="142.875" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED4" gate="G$1" x="335.28" y="139.7" smashed="yes" rot="R90"> +<attribute name="NAME" x="352.552" y="140.716" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="370.332" y="140.335" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED2" gate="G$1" x="330.2" y="137.16" smashed="yes" rot="R90"> +<attribute name="NAME" x="352.552" y="138.176" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="370.332" y="137.795" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R16" gate="A" x="314.96" y="137.16" rot="R180"/> +<instance part="SUPPLY34" gate="GND" x="342.9" y="132.08"/> +<instance part="Q3" gate="G$1" x="76.2" y="190.5"> +<attribute name="MPN" x="76.2" y="190.5" size="1.778" layer="96" display="off"/> +<attribute name="OC_FARNELL" x="76.2" y="190.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY27" gate="GND" x="71.12" y="177.8"/> +<instance part="SUPPLY28" gate="GND" x="81.28" y="177.8"/> +<instance part="C19" gate="G$1" x="294.64" y="205.74" smashed="yes"> +<attribute name="NAME" x="283.21" y="207.01" size="1.778" layer="95" font="vector"/> +<attribute name="VALUE" x="283.21" y="204.47" size="1.778" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="294.64" y="205.74" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="294.64" y="205.74" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY31" gate="GND" x="294.64" y="185.42"/> +<instance part="FRAME4" gate="G$1" x="5.08" y="43.18"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="C17" gate="G$1" pin="1"/> +<wire x1="55.88" y1="182.88" x2="55.88" y2="180.34" width="0.1524" layer="91"/> +<pinref part="SUPPLY26" gate="GND" pin="GND"/> +</segment> +<segment> +<wire x1="96.52" y1="182.88" x2="96.52" y2="180.34" width="0.1524" layer="91"/> +<pinref part="SUPPLY29" gate="GND" pin="GND"/> +<pinref part="C18" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="R15" gate="G$1" pin="1"/> +<pinref part="SUPPLY30" gate="GND" pin="GND"/> +<wire x1="160.02" y1="152.4" x2="160.02" y2="149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY33" gate="GND" pin="GND"/> +<pinref part="C20" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="J1" gate="G$1" pin="GND"/> +<pinref part="SUPPLY32" gate="GND" pin="GND"/> +<wire x1="317.5" y1="210.82" x2="302.26" y2="210.82" width="0.1524" layer="91"/> +<wire x1="302.26" y1="210.82" x2="302.26" y2="187.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="LED3" gate="G$1" pin="C"/> +<wire x1="340.36" y1="144.78" x2="342.9" y2="144.78" width="0.1524" layer="91"/> +<wire x1="342.9" y1="142.24" x2="342.9" y2="144.78" width="0.1524" layer="91"/> +<pinref part="LED1" gate="G$1" pin="C"/> +<wire x1="335.28" y1="142.24" x2="342.9" y2="142.24" width="0.1524" layer="91"/> +<junction x="342.9" y="142.24"/> +<wire x1="342.9" y1="139.7" x2="342.9" y2="142.24" width="0.1524" layer="91"/> +<pinref part="LED4" gate="G$1" pin="C"/> +<wire x1="340.36" y1="139.7" x2="342.9" y2="139.7" width="0.1524" layer="91"/> +<junction x="342.9" y="139.7"/> +<pinref part="LED2" gate="G$1" pin="C"/> +<wire x1="335.28" y1="137.16" x2="342.9" y2="137.16" width="0.1524" layer="91"/> +<wire x1="342.9" y1="137.16" x2="342.9" y2="139.7" width="0.1524" layer="91"/> +<pinref part="SUPPLY34" gate="GND" pin="GND"/> +<wire x1="342.9" y1="134.62" x2="342.9" y2="137.16" width="0.1524" layer="91"/> +<junction x="342.9" y="137.16"/> +</segment> +<segment> +<pinref part="Q3" gate="G$1" pin="G1"/> +<pinref part="SUPPLY27" gate="GND" pin="GND"/> +<wire x1="71.12" y1="182.88" x2="71.12" y2="180.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="Q3" gate="G$1" pin="G2"/> +<pinref part="SUPPLY28" gate="GND" pin="GND"/> +<wire x1="81.28" y1="182.88" x2="81.28" y2="180.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C19" gate="G$1" pin="2"/> +<pinref part="SUPPLY31" gate="GND" pin="GND"/> +<wire x1="294.64" y1="200.66" x2="294.64" y2="187.96" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="J1" gate="G$1" pin="VCC"/> +<wire x1="317.5" y1="213.36" x2="294.64" y2="213.36" width="0.1524" layer="91"/> +<wire x1="294.64" y1="213.36" x2="294.64" y2="220.98" width="0.1524" layer="91"/> +<pinref part="P+11" gate="VCC" pin="VCC"/> +<label x="297.18" y="220.98" size="1.778" layer="95"/> +<pinref part="C19" gate="G$1" pin="1"/> +<wire x1="294.64" y1="208.28" x2="294.64" y2="213.36" width="0.1524" layer="91"/> +<junction x="294.64" y="213.36"/> +</segment> +<segment> +<pinref part="P+10" gate="VCC" pin="VCC"/> +<label x="162.56" y="218.44" size="1.778" layer="95"/> +<pinref part="U4" gate="CFG" pin="VREF+@41"/> +<wire x1="167.64" y1="200.66" x2="160.02" y2="200.66" width="0.1524" layer="91"/> +<wire x1="160.02" y1="200.66" x2="160.02" y2="218.44" width="0.1524" layer="91"/> +<junction x="160.02" y="200.66"/> +<pinref part="U4" gate="CFG" pin="PDR_ON@203"/> +<wire x1="167.64" y1="195.58" x2="160.02" y2="195.58" width="0.1524" layer="91"/> +<wire x1="160.02" y1="195.58" x2="160.02" y2="200.66" width="0.1524" layer="91"/> +</segment> +</net> +<net name="OSC_OUT" class="0"> +<segment> +<wire x1="81.28" y1="190.5" x2="88.9" y2="190.5" width="0.1524" layer="91"/> +<pinref part="C18" gate="G$1" pin="2"/> +<wire x1="88.9" y1="190.5" x2="88.9" y2="162.56" width="0.1524" layer="91"/> +<wire x1="88.9" y1="190.5" x2="96.52" y2="190.5" width="0.1524" layer="91"/> +<junction x="88.9" y="190.5"/> +<label x="86.36" y="170.18" size="1.778" layer="95" rot="R270"/> +<pinref part="Q3" gate="G$1" pin="X2"/> +</segment> +<segment> +<pinref part="U4" gate="CFG" pin="OSC_OUT/PH1"/> +<wire x1="167.64" y1="182.88" x2="160.02" y2="182.88" width="0.1524" layer="91"/> +<label x="152.4" y="182.88" size="1.27" layer="95"/> +</segment> +</net> +<net name="OSC_IN" class="0"> +<segment> +<pinref part="R14" gate="G$1" pin="1"/> +<wire x1="63.5" y1="175.26" x2="63.5" y2="162.56" width="0.1524" layer="91"/> +<label x="60.96" y="170.18" size="1.778" layer="95" rot="R270"/> +</segment> +<segment> +<pinref part="U4" gate="CFG" pin="OSC_IN/PH0"/> +<wire x1="167.64" y1="185.42" x2="160.02" y2="185.42" width="0.1524" layer="91"/> +<label x="152.4" y="185.42" size="1.27" layer="95"/> +</segment> +</net> +<net name="SWDIO" class="0"> +<segment> +<pinref part="J1" gate="G$1" pin="SWDIO"/> +<wire x1="317.5" y1="208.28" x2="314.96" y2="208.28" width="0.1524" layer="91"/> +<label x="314.96" y="208.28" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="226.06" y1="187.96" x2="233.68" y2="187.96" width="0.1524" layer="91"/> +<label x="233.68" y="187.96" size="1.27" layer="95"/> +<pinref part="U4" gate="CFG" pin="PA13/JTMS-SWDIO"/> +</segment> +</net> +<net name="SWDCLK" class="0"> +<segment> +<pinref part="J1" gate="G$1" pin="SWDCLK"/> +<wire x1="317.5" y1="205.74" x2="314.96" y2="205.74" width="0.1524" layer="91"/> +<label x="314.96" y="205.74" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="U4" gate="CFG" pin="PA14/JTCK-SWCLK"/> +<wire x1="226.06" y1="190.5" x2="233.68" y2="190.5" width="0.1524" layer="91"/> +<label x="233.68" y="190.5" size="1.27" layer="95"/> +</segment> +</net> +<net name="NRST" class="0"> +<segment> +<pinref part="J1" gate="G$1" pin="NRST"/> +<pinref part="C20" gate="G$1" pin="1"/> +<wire x1="317.5" y1="195.58" x2="317.5" y2="200.66" width="0.1524" layer="91"/> +<wire x1="317.5" y1="200.66" x2="314.96" y2="200.66" width="0.1524" layer="91"/> +<junction x="317.5" y="200.66"/> +<label x="314.96" y="200.66" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="U4" gate="CFG" pin="NRST"/> +<wire x1="226.06" y1="193.04" x2="233.68" y2="193.04" width="0.1524" layer="91"/> +<label x="233.68" y="193.04" size="1.27" layer="95"/> +</segment> +</net> +<net name="BOOT0" class="1"> +<segment> +<pinref part="U4" gate="CFG" pin="BOOT0@197"/> +<wire x1="167.64" y1="167.64" x2="160.02" y2="167.64" width="0.1524" layer="91"/> +<wire x1="160.02" y1="167.64" x2="160.02" y2="162.56" width="0.1524" layer="91"/> +<pinref part="R15" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$21" class="0"> +<segment> +<pinref part="C17" gate="G$1" pin="2"/> +<wire x1="71.12" y1="190.5" x2="63.5" y2="190.5" width="0.1524" layer="91"/> +<wire x1="63.5" y1="190.5" x2="55.88" y2="190.5" width="0.1524" layer="91"/> +<wire x1="63.5" y1="190.5" x2="63.5" y2="185.42" width="0.1524" layer="91"/> +<junction x="63.5" y="190.5"/> +<pinref part="R14" gate="G$1" pin="2"/> +<pinref part="Q3" gate="G$1" pin="X1"/> +</segment> +</net> +<net name="ARM_LED1" class="0"> +<segment> +<wire x1="304.8" y1="144.78" x2="299.72" y2="144.78" width="0.1524" layer="91"/> +<label x="299.72" y="144.78" size="1.27" layer="95" rot="R180"/> +<pinref part="R16" gate="A" pin="5"/> +</segment> +</net> +<net name="ARM_LED2" class="0"> +<segment> +<wire x1="304.8" y1="142.24" x2="299.72" y2="142.24" width="0.1524" layer="91"/> +<label x="299.72" y="142.24" size="1.27" layer="95" rot="R180"/> +<pinref part="R16" gate="A" pin="6"/> +</segment> +</net> +<net name="ARM_LED3" class="0"> +<segment> +<wire x1="304.8" y1="139.7" x2="299.72" y2="139.7" width="0.1524" layer="91"/> +<label x="299.72" y="139.7" size="1.27" layer="95" rot="R180"/> +<pinref part="R16" gate="A" pin="7"/> +</segment> +</net> +<net name="ARM_LED4" class="0"> +<segment> +<wire x1="304.8" y1="137.16" x2="299.72" y2="137.16" width="0.1524" layer="91"/> +<label x="299.72" y="137.16" size="1.27" layer="95" rot="R180"/> +<pinref part="R16" gate="A" pin="8"/> +</segment> +</net> +<net name="N$17" class="0"> +<segment> +<pinref part="LED3" gate="G$1" pin="A"/> +<wire x1="325.12" y1="144.78" x2="332.74" y2="144.78" width="0.1524" layer="91"/> +<pinref part="R16" gate="A" pin="4"/> +</segment> +</net> +<net name="N$18" class="0"> +<segment> +<pinref part="LED1" gate="G$1" pin="A"/> +<wire x1="325.12" y1="142.24" x2="327.66" y2="142.24" width="0.1524" layer="91"/> +<pinref part="R16" gate="A" pin="3"/> +</segment> +</net> +<net name="N$19" class="0"> +<segment> +<pinref part="LED4" gate="G$1" pin="A"/> +<wire x1="325.12" y1="139.7" x2="332.74" y2="139.7" width="0.1524" layer="91"/> +<pinref part="R16" gate="A" pin="2"/> +</segment> +</net> +<net name="N$20" class="0"> +<segment> +<pinref part="LED2" gate="G$1" pin="A"/> +<wire x1="325.12" y1="137.16" x2="327.66" y2="137.16" width="0.1524" layer="91"/> +<pinref part="R16" gate="A" pin="1"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>ARM Power</description> +<plain> +<text x="114.3" y="20.32" size="1.778" layer="91">ST AN8844 §2.2 +One bypass capacitor for every VDD. +Use 0.1 uF X7R 10V.</text> +<text x="34.29" y="19.05" size="1.778" layer="91">ST AN8844 §2.2 +One 10uF bypass cap for the package. +(two used for extra comfort)</text> +<text x="-40.64" y="19.05" size="1.778" layer="91">2*2*2.2uF LowESR or +2*1*4.7uF LowESR +< 1 ohm +(ST AN4488 §2.2)</text> +<text x="-154.94" y="88.9" size="3.81" layer="91">Power and bypass capacitors, STM32</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">ARM power</text> +</plain> +<instances> +<instance part="FRAME5" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="C26" gate="G$1" x="48.26" y="-5.08" smashed="yes"> +<attribute name="NAME" x="44.45" y="-3.81" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="45.72" y="-6.35" size="1.6764" layer="96" rot="R180"/> +<attribute name="DIELECTRIC" x="48.26" y="-5.08" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="-5.08" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C27" gate="G$1" x="58.42" y="-5.08" smashed="yes"> +<attribute name="NAME" x="62.23" y="-5.08" size="1.6764" layer="95"/> +<attribute name="VALUE" x="60.96" y="-7.62" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="58.42" y="-5.08" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="58.42" y="-5.08" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="SUPPLY37" gate="GND" x="53.34" y="-20.32"/> +<instance part="P+14" gate="VCC" x="53.34" y="7.62" smashed="yes"/> +<instance part="P+15" gate="VCC" x="106.68" y="21.59" smashed="yes"/> +<instance part="SUPPLY38" gate="GND" x="106.68" y="-20.32"/> +<instance part="C45" gate="G$1" x="152.4" y="7.62" smashed="yes"> +<attribute name="NAME" x="152.4" y="12.7" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="160.02" y="10.16" size="1.27" layer="96" font="vector"/> +</instance> +<instance part="C43" gate="G$1" x="147.32" y="7.62" smashed="yes"> +<attribute name="NAME" x="147.32" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C41" gate="G$1" x="142.24" y="7.62" smashed="yes"> +<attribute name="NAME" x="142.24" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C39" gate="G$1" x="137.16" y="7.62" smashed="yes"> +<attribute name="NAME" x="137.16" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C37" gate="G$1" x="132.08" y="7.62" smashed="yes"> +<attribute name="NAME" x="132.08" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C35" gate="G$1" x="127" y="7.62" smashed="yes"> +<attribute name="NAME" x="127" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C33" gate="G$1" x="121.92" y="7.62" smashed="yes"> +<attribute name="NAME" x="121.92" y="12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C31" gate="G$1" x="116.84" y="7.62" smashed="yes"> +<attribute name="NAME" x="116.84" y="12.7" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="116.84" y="7.62" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="116.84" y="7.62" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C32" gate="G$1" x="116.84" y="-5.08" smashed="yes"> +<attribute name="NAME" x="114.3" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C30" gate="G$1" x="111.76" y="-5.08" smashed="yes"> +<attribute name="NAME" x="109.22" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C29" gate="G$1" x="111.76" y="7.62" smashed="yes"> +<attribute name="NAME" x="111.76" y="12.7" size="1.27" layer="95" font="vector"/> +<attribute name="RATED_VOLTAGE" x="111.76" y="7.62" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C28" gate="G$1" x="106.68" y="7.62" smashed="yes"> +<attribute name="NAME" x="106.68" y="12.7" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="106.68" y="7.62" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="106.68" y="7.62" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C46" gate="G$1" x="152.4" y="-5.08" smashed="yes"> +<attribute name="NAME" x="149.86" y="-12.7" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="157.48" y="-5.08" size="1.27" layer="96" font="vector"/> +</instance> +<instance part="C44" gate="G$1" x="147.32" y="-5.08" smashed="yes"> +<attribute name="NAME" x="144.78" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C42" gate="G$1" x="142.24" y="-5.08" smashed="yes"> +<attribute name="NAME" x="139.7" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C40" gate="G$1" x="137.16" y="-5.08" smashed="yes"> +<attribute name="NAME" x="134.62" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C38" gate="G$1" x="132.08" y="-5.08" smashed="yes"> +<attribute name="NAME" x="129.54" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C36" gate="G$1" x="127" y="-5.08" smashed="yes"> +<attribute name="NAME" x="124.46" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C34" gate="G$1" x="121.92" y="-5.08" smashed="yes"> +<attribute name="NAME" x="119.38" y="-12.7" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C21" gate="G$1" x="-142.24" y="-33.02" smashed="yes"> +<attribute name="NAME" x="-149.86" y="-30.48" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="-149.86" y="-33.02" size="1.27" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="-142.24" y="-33.02" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-142.24" y="-33.02" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="SUPPLY35" gate="GND" x="-142.24" y="-43.18"/> +<instance part="C24" gate="G$1" x="-43.18" y="-5.08" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-43.18" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="-43.18" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-39.116" y="-4.699" size="1.778" layer="95"/> +<attribute name="VALUE" x="-39.116" y="-7.239" size="1.778" layer="96"/> +</instance> +<instance part="C22" gate="G$1" x="-5.08" y="-5.08" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-5.08" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="-5.08" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-1.016" y="-4.699" size="1.778" layer="95"/> +<attribute name="VALUE" x="-1.016" y="-7.239" size="1.778" layer="96"/> +</instance> +<instance part="C23" gate="G$1" x="-10.16" y="-5.08" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-10.16" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="-10.16" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-12.7" y="-2.54" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-12.7" y="-5.08" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="C25" gate="G$1" x="-48.26" y="-5.08" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-48.26" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="-48.26" y="-5.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-52.324" y="-2.921" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-52.324" y="-5.461" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="U4" gate="PWR" x="-116.84" y="2.54"/> +<instance part="P+12" gate="VCC" x="-142.24" y="36.83" smashed="yes"/> +<instance part="SUPPLY36" gate="GND" x="-91.44" y="-43.18"/> +<instance part="SUPPLY7" gate="GND" x="-10.16" y="-17.78"/> +<instance part="SUPPLY43" gate="GND" x="-43.18" y="-17.78"/> +<instance part="R32" gate="G$1" x="-137.16" y="45.72" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="-137.16" y="45.72" size="1.778" layer="96" rot="R270" display="off"/> +<attribute name="NAME" x="-144.78" y="48.26" size="1.778" layer="95"/> +<attribute name="VALUE" x="-144.78" y="45.72" size="1.778" layer="96"/> +</instance> +<instance part="P+87" gate="VCC" x="-137.16" y="55.88" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="C26" gate="G$1" pin="2"/> +<wire x1="48.26" y1="-10.16" x2="48.26" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="SUPPLY37" gate="GND" pin="GND"/> +<wire x1="53.34" y1="-12.7" x2="53.34" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="C27" gate="G$1" pin="2"/> +<wire x1="58.42" y1="-10.16" x2="58.42" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="58.42" y1="-12.7" x2="53.34" y2="-12.7" width="0.1524" layer="91"/> +<junction x="53.34" y="-12.7"/> +</segment> +<segment> +<pinref part="C45" gate="G$1" pin="2"/> +<pinref part="C28" gate="G$1" pin="2"/> +<wire x1="152.4" y1="2.54" x2="147.32" y2="2.54" width="0.1524" layer="91"/> +<pinref part="SUPPLY38" gate="GND" pin="GND"/> +<wire x1="147.32" y1="2.54" x2="142.24" y2="2.54" width="0.1524" layer="91"/> +<wire x1="142.24" y1="2.54" x2="137.16" y2="2.54" width="0.1524" layer="91"/> +<wire x1="137.16" y1="2.54" x2="132.08" y2="2.54" width="0.1524" layer="91"/> +<wire x1="132.08" y1="2.54" x2="127" y2="2.54" width="0.1524" layer="91"/> +<wire x1="127" y1="2.54" x2="121.92" y2="2.54" width="0.1524" layer="91"/> +<wire x1="121.92" y1="2.54" x2="116.84" y2="2.54" width="0.1524" layer="91"/> +<wire x1="116.84" y1="2.54" x2="111.76" y2="2.54" width="0.1524" layer="91"/> +<wire x1="111.76" y1="2.54" x2="106.68" y2="2.54" width="0.1524" layer="91"/> +<wire x1="106.68" y1="2.54" x2="106.68" y2="-10.16" width="0.1524" layer="91"/> +<junction x="106.68" y="2.54"/> +<wire x1="106.68" y1="-10.16" x2="106.68" y2="-17.78" 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width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-10.16" x2="-142.24" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-12.7" x2="-142.24" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-17.78" x2="-142.24" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-20.32" x2="-142.24" y2="-22.86" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-22.86" x2="-142.24" y2="-25.4" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="-25.4" x2="-137.16" y2="-25.4" width="0.1524" layer="91"/> +<pinref part="U4" gate="PWR" pin="VDD@171"/> +<wire x1="-137.16" y1="-22.86" x2="-142.24" y2="-22.86" width="0.1524" layer="91"/> +<junction x="-142.24" y="-22.86"/> +<pinref part="U4" gate="PWR" pin="VDD@185"/> +<wire x1="-137.16" y1="-20.32" x2="-142.24" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-142.24" y="-20.32"/> +<pinref part="U4" gate="PWR" pin="VDD@204"/> +<wire x1="-137.16" y1="-17.78" x2="-142.24" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-142.24" y="-17.78"/> +<pinref part="U4" gate="PWR" pin="VDD@150"/> +<wire x1="-137.16" y1="-12.7" x2="-142.24" y2="-12.7" width="0.1524" layer="91"/> +<junction x="-142.24" y="-12.7"/> +<pinref part="U4" gate="PWR" pin="VDD@137"/> +<wire x1="-137.16" y1="-10.16" x2="-142.24" y2="-10.16" width="0.1524" layer="91"/> +<junction x="-142.24" y="-10.16"/> +<pinref part="U4" gate="PWR" pin="VDD@124"/> +<wire x1="-137.16" y1="-7.62" x2="-142.24" y2="-7.62" width="0.1524" layer="91"/> +<junction x="-142.24" y="-7.62"/> +<pinref part="U4" gate="PWR" pin="VDD@115"/> +<wire x1="-137.16" y1="-5.08" x2="-142.24" y2="-5.08" width="0.1524" layer="91"/> +<junction x="-142.24" y="-5.08"/> +<pinref part="U4" gate="PWR" pin="VDD@103"/> +<wire x1="-137.16" y1="0" x2="-142.24" y2="0" width="0.1524" layer="91"/> +<junction x="-142.24" y="0"/> +<pinref part="U4" gate="PWR" pin="VDD@94"/> +<wire x1="-137.16" y1="2.54" x2="-142.24" y2="2.54" width="0.1524" layer="91"/> +<junction x="-142.24" y="2.54"/> +<pinref part="U4" gate="PWR" pin="VDD@83"/> +<wire x1="-137.16" y1="5.08" x2="-142.24" y2="5.08" width="0.1524" layer="91"/> +<junction x="-142.24" y="5.08"/> +<pinref part="U4" gate="PWR" pin="VDD@73"/> +<wire x1="-137.16" y1="7.62" x2="-142.24" y2="7.62" width="0.1524" layer="91"/> +<junction x="-142.24" y="7.62"/> +<pinref part="U4" gate="PWR" pin="VDD@59"/> +<wire x1="-137.16" y1="10.16" x2="-142.24" y2="10.16" width="0.1524" layer="91"/> +<junction x="-142.24" y="10.16"/> +<pinref part="U4" gate="PWR" pin="VDD@52"/> +<wire x1="-137.16" y1="15.24" x2="-142.24" y2="15.24" width="0.1524" layer="91"/> +<junction x="-142.24" y="15.24"/> +<pinref part="U4" gate="PWR" pin="VDD@39"/> +<wire x1="-137.16" y1="17.78" x2="-142.24" y2="17.78" width="0.1524" layer="91"/> +<junction x="-142.24" y="17.78"/> +<pinref part="U4" gate="PWR" pin="VDD@26"/> +<wire x1="-137.16" y1="20.32" x2="-142.24" y2="20.32" width="0.1524" layer="91"/> +<junction x="-142.24" y="20.32"/> +<pinref part="U4" gate="PWR" pin="VDD@15"/> +<wire x1="-137.16" y1="22.86" x2="-142.24" y2="22.86" width="0.1524" layer="91"/> +<junction x="-142.24" y="22.86"/> +<pinref part="U4" gate="PWR" pin="VDDA@42"/> +<wire x1="-137.16" y1="27.94" x2="-142.24" y2="27.94" width="0.1524" layer="91"/> +<junction x="-142.24" y="27.94"/> +<pinref part="C21" gate="G$1" pin="1"/> +<wire x1="-142.24" y1="-25.4" x2="-142.24" y2="-30.48" width="0.1524" layer="91"/> +<junction x="-142.24" y="-25.4"/> +</segment> +</net> +<net name="VCAP2" class="0"> +<segment> +<pinref part="C24" gate="G$1" pin="2"/> +<pinref part="C25" gate="G$1" pin="2"/> +<wire x1="-48.26" y1="0" x2="-48.26" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="2.54" x2="-43.18" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="2.54" x2="-43.18" y2="0" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="2.54" x2="-43.18" y2="7.62" width="0.1524" layer="91"/> +<junction x="-43.18" y="2.54"/> +<label x="-53.34" y="10.16" size="1.778" layer="95"/> +<wire x1="-43.18" y1="7.62" x2="-53.34" y2="7.62" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U4" gate="PWR" pin="VCAP2@148"/> +<wire x1="-114.3" y1="43.18" x2="-114.3" y2="48.26" width="0.1524" layer="91"/> +<label x="-106.68" y="50.8" size="1.778" layer="95" rot="R180"/> +<wire x1="-114.3" y1="48.26" x2="-109.22" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCAP1" class="0"> +<segment> +<pinref part="C22" gate="G$1" pin="2"/> +<pinref part="C23" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="0" x2="-10.16" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="2.54" x2="-5.08" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="2.54" x2="-5.08" y2="0" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="2.54" x2="-10.16" y2="7.62" width="0.1524" layer="91"/> +<junction x="-10.16" y="2.54"/> +<label x="-20.32" y="10.16" size="1.778" layer="95"/> +<wire x1="-10.16" y1="7.62" x2="-20.32" y2="7.62" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U4" gate="PWR" pin="VCAP1@92"/> +<wire x1="-119.38" y1="43.18" x2="-119.38" y2="48.26" width="0.1524" layer="91"/> +<label x="-119.38" y="50.8" size="1.778" layer="95" rot="R180"/> +<wire x1="-119.38" y1="48.26" x2="-124.46" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$25" class="0"> +<segment> +<pinref part="U4" gate="PWR" pin="VBAT@6"/> +<wire x1="-137.16" y1="33.02" x2="-137.16" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$53" class="0"> +<segment> +<pinref part="R32" gate="G$1" pin="2"/> +<wire x1="-137.16" y1="40.64" x2="-137.16" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="3V3_BATT" class="0"> +<segment> +<pinref part="R32" gate="G$1" pin="1"/> +<wire x1="-137.16" y1="50.8" x2="-137.16" y2="53.34" width="0.1524" layer="91"/> +<pinref part="P+87" gate="VCC" pin="VCC"/> +<label x="-149.86" y="58.42" size="1.778" layer="95"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>ARM I/O</description> +<plain> +<text x="-121.92" y="-95.25" size="1.778" layer="91">All of these input/outputs can be swapped +with equivalent functionality pins.</text> +<text x="-167.64" y="104.14" size="3.81" layer="91">Input/output, STM32</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">ARM I/O</text> +</plain> +<instances> +<instance part="FRAME6" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="U4" gate="FMC" x="99.06" y="2.54"/> +<instance part="U4" gate="IO" x="-83.82" y="0"/> +</instances> +<busses> +<bus name="FMC_D[0..31],FMC_A[0..25]"> +<segment> +<wire x1="134.62" y1="60.96" x2="170.18" y2="60.96" width="0.762" layer="92"/> +<wire x1="134.62" y1="60.96" x2="134.62" y2="-22.86" width="0.762" layer="92"/> +<label x="134.62" y="63.5" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="58.42" y1="60.96" x2="58.42" y2="-7.62" width="0.762" layer="92"/> +<wire x1="58.42" y1="60.96" x2="22.86" y2="60.96" width="0.762" layer="92"/> +<label x="22.86" y="63.5" size="1.778" layer="95"/> +</segment> +</bus> +</busses> +<nets> +<net name="FMC_CLK" class="0"> +<segment> +<wire x1="66.04" y1="-38.1" x2="58.42" y2="-38.1" width="0.1524" layer="91"/> +<label x="58.42" y="-38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_CLK/PD3"/> +</segment> +</net> +<net name="FMC_NL" class="0"> +<segment> +<wire x1="58.42" y1="-30.48" x2="66.04" y2="-30.48" width="0.1524" layer="91"/> +<label x="58.42" y="-30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NL/PB7"/> +</segment> +</net> +<net name="FMC_NOE" class="0"> +<segment> +<wire x1="66.04" y1="-40.64" x2="58.42" y2="-40.64" width="0.1524" layer="91"/> +<label x="58.42" y="-40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NOE/PD4"/> +</segment> +</net> +<net name="FMC_NWE" class="0"> +<segment> +<wire x1="66.04" y1="-43.18" x2="58.42" y2="-43.18" width="0.1524" layer="91"/> +<label x="58.42" y="-43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NWE/PD5"/> +</segment> +</net> +<net name="FMC_NWAIT" class="0"> +<segment> +<wire x1="66.04" y1="-45.72" x2="58.42" y2="-45.72" width="0.1524" layer="91"/> +<label x="58.42" y="-45.72" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NWAIT/PD6"/> +</segment> +</net> +<net name="FMC_NE1" class="0"> +<segment> +<wire x1="66.04" y1="-48.26" x2="58.42" y2="-48.26" width="0.1524" layer="91"/> +<label x="58.42" y="-48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NE1/PD7"/> +</segment> +</net> +<net name="FMC_SDNCAS" class="0"> +<segment> +<wire x1="127" y1="-53.34" x2="134.62" y2="-53.34" width="0.1524" layer="91"/> +<label x="134.62" y="-53.34" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PG15/FMC_SDNCAS"/> +</segment> +</net> +<net name="FMC_SDNRAS" class="0"> +<segment> +<wire x1="127" y1="-55.88" x2="134.62" y2="-55.88" width="0.1524" layer="91"/> +<label x="134.62" y="-55.88" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PF11/FMC_SDNRAS"/> +</segment> +</net> +<net name="FMC_NBL0" class="0"> +<segment> +<wire x1="66.04" y1="-15.24" x2="58.42" y2="-15.24" width="0.1524" layer="91"/> +<label x="58.42" y="-15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NBL0/PE0"/> +</segment> +</net> +<net name="FMC_NBL1" class="0"> +<segment> +<wire x1="66.04" y1="-17.78" x2="58.42" y2="-17.78" width="0.1524" layer="91"/> +<label x="58.42" y="-17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NBL1/PE1"/> +</segment> +</net> +<net name="FMC_NBL2" class="0"> +<segment> +<wire x1="66.04" y1="-20.32" x2="58.42" y2="-20.32" width="0.1524" layer="91"/> +<label x="58.42" y="-20.32" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NBL2/PI4"/> +</segment> +</net> +<net name="FMC_NBL3" class="0"> +<segment> +<wire x1="66.04" y1="-22.86" x2="58.42" y2="-22.86" width="0.1524" layer="91"/> +<label x="58.42" y="-22.86" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="FMC" pin="FMC_NBL3/PI5"/> +</segment> +</net> +<net name="FMC_SDCKE1" class="0"> +<segment> +<wire x1="127" y1="-48.26" x2="134.62" y2="-48.26" width="0.1524" layer="91"/> +<label x="134.62" y="-48.26" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PB5/FMC_SDCKE1"/> +</segment> +</net> +<net name="FMC_SDNE1" class="0"> +<segment> +<wire x1="127" y1="-40.64" x2="134.62" y2="-40.64" width="0.1524" layer="91"/> +<label x="134.62" y="-40.64" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PB6/FMC_SDNE1"/> +</segment> +</net> +<net name="FMC_A0" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A0/PF0"/> +<wire x1="58.42" y1="55.88" x2="66.04" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A1" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A1/PF1"/> +<wire x1="58.42" y1="53.34" x2="66.04" y2="53.34" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A2" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A2/PF2"/> +<wire x1="58.42" y1="50.8" x2="66.04" y2="50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A3" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A3/PF3"/> +<wire x1="58.42" y1="48.26" x2="66.04" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A4" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A4/PF4"/> +<wire x1="58.42" y1="45.72" x2="66.04" y2="45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A5" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A5/PF5"/> +<wire x1="58.42" y1="43.18" x2="66.04" y2="43.18" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A6" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A6/PF12"/> +<wire x1="58.42" y1="40.64" x2="66.04" y2="40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A7" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A7/PF13"/> +<wire x1="58.42" y1="38.1" x2="66.04" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A8" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A8/PF14"/> +<wire x1="58.42" y1="35.56" x2="66.04" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A9" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A9/PF15"/> +<wire x1="58.42" y1="33.02" x2="66.04" y2="33.02" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A10" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A10/PG0"/> +<wire x1="58.42" y1="30.48" x2="66.04" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A11" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A11/PG1"/> +<wire x1="58.42" y1="27.94" x2="66.04" y2="27.94" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A12" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A12/PG2"/> +<wire x1="58.42" y1="25.4" x2="66.04" y2="25.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A13" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A13/PG3"/> +<wire x1="58.42" y1="22.86" x2="66.04" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A14" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A14/PG4"/> +<wire x1="58.42" y1="20.32" x2="66.04" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A15" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A15/PG5"/> +<wire x1="58.42" y1="17.78" x2="66.04" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A16" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A16/PD11"/> +<wire x1="58.42" y1="15.24" x2="66.04" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A17" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A17/PD12"/> +<wire x1="58.42" y1="12.7" x2="66.04" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A18" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A18/PD13"/> +<wire x1="58.42" y1="10.16" x2="66.04" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A19" class="3"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A19/PE3"/> +<wire x1="58.42" y1="7.62" x2="66.04" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A20" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A20/PE4"/> +<wire x1="58.42" y1="5.08" x2="66.04" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A21" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A21/PE5"/> +<wire x1="58.42" y1="2.54" x2="66.04" y2="2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A22" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A22/PE6"/> +<wire x1="58.42" y1="0" x2="66.04" y2="0" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A23" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A23/PE2"/> +<wire x1="58.42" y1="-2.54" x2="66.04" y2="-2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A24" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A24/PG13"/> +<wire x1="58.42" y1="-5.08" x2="66.04" y2="-5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A25" class="0"> +<segment> +<pinref part="U4" gate="FMC" pin="FMC_A25/PG14"/> +<wire x1="58.42" y1="-7.62" x2="66.04" y2="-7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D0" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD14/FMC_D0"/> +<wire x1="134.62" y1="55.88" x2="127" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D1" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD15/FMC_D1"/> +<wire x1="134.62" y1="53.34" x2="127" y2="53.34" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D2" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD0/FMC_D2"/> +<wire x1="134.62" y1="50.8" x2="127" y2="50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D3" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD1/FMC_D3"/> +<wire x1="134.62" y1="48.26" x2="127" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D4" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE7/FMC_D4"/> +<wire x1="134.62" y1="45.72" x2="127" y2="45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D5" class="2"> +<segment> +<wire x1="134.62" y1="43.18" x2="127" y2="43.18" width="0.1524" layer="91"/> +<pinref part="U4" gate="FMC" pin="PE8/FMC_D5"/> +</segment> +</net> +<net name="FMC_D6" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE9/FMC_D6"/> +<wire x1="134.62" y1="40.64" x2="127" y2="40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D7" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE10/FMC_D7"/> +<wire x1="134.62" y1="38.1" x2="127" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D8" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE11/FMC_D8"/> +<wire x1="134.62" y1="35.56" x2="127" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D9" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE12/FMC_D9"/> +<wire x1="134.62" y1="33.02" x2="127" y2="33.02" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D10" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE13/FMC_D10"/> +<wire x1="134.62" y1="30.48" x2="127" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D11" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE14/FMC_D11"/> +<wire x1="134.62" y1="27.94" x2="127" y2="27.94" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D12" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PE15/FMC_D12"/> +<wire x1="134.62" y1="25.4" x2="127" y2="25.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D13" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD8/FMC_D13"/> +<wire x1="134.62" y1="22.86" x2="127" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D14" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD9/FMC_D14"/> +<wire x1="134.62" y1="20.32" x2="127" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D15" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PD10/FMC_D15"/> +<wire x1="134.62" y1="17.78" x2="127" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D16" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH8/FMC_D16"/> +<wire x1="134.62" y1="15.24" x2="127" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D17" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH9/FMC_D17"/> +<wire x1="134.62" y1="12.7" x2="127" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D18" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH10/FMC_D18"/> +<wire x1="134.62" y1="10.16" x2="127" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D19" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH11/FMC_D19"/> +<wire x1="134.62" y1="7.62" x2="127" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D20" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH12/FMC_D20"/> +<wire x1="134.62" y1="5.08" x2="127" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D21" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH13/FMC_D21"/> +<wire x1="134.62" y1="2.54" x2="127" y2="2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D22" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH14/FMC_D22"/> +<wire x1="134.62" y1="0" x2="127" y2="0" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D23" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PH15/FMC_D23"/> +<wire x1="134.62" y1="-2.54" x2="127" y2="-2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D24" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI0/FMC_D24"/> +<wire x1="134.62" y1="-5.08" x2="127" y2="-5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D25" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI1/FMC_D25"/> +<wire x1="134.62" y1="-7.62" x2="127" y2="-7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D26" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI2/FMC_D26"/> +<wire x1="134.62" y1="-10.16" x2="127" y2="-10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D27" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI3/FMC_D27"/> +<wire x1="134.62" y1="-12.7" x2="127" y2="-12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D28" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI6/FMC_D28"/> +<wire x1="134.62" y1="-15.24" x2="127" y2="-15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D29" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI7/FMC_D29"/> +<wire x1="134.62" y1="-17.78" x2="127" y2="-17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D30" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI9/FMC_D30"/> +<wire x1="134.62" y1="-20.32" x2="127" y2="-20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D31" class="2"> +<segment> +<pinref part="U4" gate="FMC" pin="PI10/FMC_D31"/> +<wire x1="134.62" y1="-22.86" x2="127" y2="-22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_SDCKE0" class="0"> +<segment> +<wire x1="127" y1="-45.72" x2="134.62" y2="-45.72" width="0.1524" layer="91"/> +<label x="134.62" y="-45.72" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PC3/FMC_SDCKE0"/> +</segment> +</net> +<net name="FMC_SDNE0" class="0"> +<segment> +<wire x1="127" y1="-38.1" x2="134.62" y2="-38.1" width="0.1524" layer="91"/> +<label x="134.62" y="-38.1" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PC2/FMC_SDNE0"/> +</segment> +</net> +<net name="FMC_SDNWE" class="0"> +<segment> +<wire x1="127" y1="-33.02" x2="134.62" y2="-33.02" width="0.1524" layer="91"/> +<label x="134.62" y="-33.02" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PC0/FMC_SDNWE"/> +</segment> +</net> +<net name="FMC_SDCLK" class="0"> +<segment> +<wire x1="127" y1="-30.48" x2="134.62" y2="-30.48" width="0.1524" layer="91"/> +<label x="134.62" y="-30.48" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="FMC" pin="PG8/FMC_SDCLK"/> +</segment> +</net> +<net name="FT_TXD" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="USART2_RX/PA3"/> +<wire x1="-124.46" y1="68.58" x2="-132.08" y2="68.58" width="0.1524" layer="91"/> +<label x="-132.08" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FT_RXD" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="USART2_TX/PA2"/> +<wire x1="-124.46" y1="71.12" x2="-132.08" y2="71.12" width="0.1524" layer="91"/> +<label x="-132.08" y="71.12" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ARM_LED1" class="0"> +<segment> +<wire x1="-45.72" y1="2.54" x2="-38.1" y2="2.54" width="0.1524" layer="91"/> +<label x="-38.1" y="2.54" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ0"/> +</segment> +</net> +<net name="ARM_LED2" class="0"> +<segment> +<wire x1="-45.72" y1="0" x2="-38.1" y2="0" width="0.1524" layer="91"/> +<label x="-38.1" y="0" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ1"/> +</segment> +</net> +<net name="ARM_LED3" class="0"> +<segment> +<wire x1="-45.72" y1="-2.54" x2="-38.1" y2="-2.54" width="0.1524" layer="91"/> +<label x="-38.1" y="-2.54" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ2"/> +</segment> +</net> +<net name="ARM_LED4" class="0"> +<segment> +<wire x1="-45.72" y1="-5.08" x2="-38.1" y2="-5.08" width="0.1524" layer="91"/> +<label x="-38.1" y="-5.08" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ3"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_1" class="0"> +<segment> +<wire x1="-132.08" y1="-68.58" x2="-124.46" y2="-68.58" width="0.1524" layer="91"/> +<label x="-132.08" y="-68.58" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="PC14"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_0" class="0"> +<segment> +<wire x1="-124.46" y1="-66.04" x2="-132.08" y2="-66.04" width="0.1524" layer="91"/> +<label x="-132.08" y="-66.04" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="PC13"/> +</segment> +</net> +<net name="RTC_SCL" class="0"> +<segment> +<wire x1="-124.46" y1="-15.24" x2="-132.08" y2="-15.24" width="0.1524" layer="91"/> +<label x="-132.08" y="-15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="I2C2_SCL/PH4"/> +</segment> +</net> +<net name="RTC_SDA" class="0"> +<segment> +<wire x1="-124.46" y1="-12.7" x2="-132.08" y2="-12.7" width="0.1524" layer="91"/> +<label x="-132.08" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="I2C2_SDA/PH5"/> +</segment> +</net> +<net name="RTC_MFP" class="0"> +<segment> +<wire x1="-124.46" y1="-17.78" x2="-132.08" y2="-17.78" width="0.1524" layer="91"/> +<label x="-132.08" y="-17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="PH3"/> +</segment> +</net> +<net name="FPGA_IRQ_N_0" class="0"> +<segment> +<wire x1="-45.72" y1="-22.86" x2="-38.1" y2="-22.86" width="0.1524" layer="91"/> +<label x="-38.1" y="-22.86" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ10"/> +</segment> +</net> +<net name="FPGA_IRQ_N_1" class="0"> +<segment> +<wire x1="-45.72" y1="-25.4" x2="-38.1" y2="-25.4" width="0.1524" layer="91"/> +<label x="-38.1" y="-25.4" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ11"/> +</segment> +</net> +<net name="FPGA_IRQ_N_2" class="0"> +<segment> +<wire x1="-45.72" y1="-27.94" x2="-38.1" y2="-27.94" width="0.1524" layer="91"/> +<label x="-38.1" y="-27.94" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ12"/> +</segment> +</net> +<net name="FPGA_IRQ_N_3" class="0"> +<segment> +<wire x1="-45.72" y1="-30.48" x2="-38.1" y2="-30.48" width="0.1524" layer="91"/> +<label x="-38.1" y="-30.48" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ13"/> +</segment> +</net> +<net name="FPGA_PROGRAM_B" class="0"> +<segment> +<wire x1="-45.72" y1="-17.78" x2="-38.1" y2="-17.78" width="0.1524" layer="91"/> +<label x="-38.1" y="-17.78" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ8"/> +</segment> +</net> +<net name="FPGA_INIT_B" class="0"> +<segment> +<wire x1="-45.72" y1="-15.24" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> +<label x="-38.1" y="-15.24" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ7"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_SCLK" class="0"> +<segment> +<wire x1="-124.46" y1="35.56" x2="-132.08" y2="35.56" width="0.1524" layer="91"/> +<label x="-132.08" y="35.56" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI2_SCK/PB13"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_MISO" class="0"> +<segment> +<wire x1="-124.46" y1="33.02" x2="-132.08" y2="33.02" width="0.1524" layer="91"/> +<label x="-132.08" y="33.02" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI2_MISO/PB14"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_MOSI" class="0"> +<segment> +<wire x1="-124.46" y1="30.48" x2="-132.08" y2="30.48" width="0.1524" layer="91"/> +<label x="-132.08" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI2_MOSI/PB15"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_ARM_ENA" class="0"> +<segment> +<wire x1="-45.72" y1="-12.7" x2="-38.1" y2="-12.7" width="0.1524" layer="91"/> +<label x="-38.1" y="-12.7" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ6"/> +</segment> +</net> +<net name="KSM_PROM_SCLK" class="0"> +<segment> +<wire x1="-124.46" y1="20.32" x2="-132.08" y2="20.32" width="0.1524" layer="91"/> +<label x="-132.08" y="20.32" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI1_SCK/PA5"/> +</segment> +</net> +<net name="KSM_PROM_MISO" class="0"> +<segment> +<wire x1="-124.46" y1="17.78" x2="-132.08" y2="17.78" width="0.1524" layer="91"/> +<label x="-132.08" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI1_MISO/PA6"/> +</segment> +</net> +<net name="KSM_PROM_MOSI" class="0"> +<segment> +<wire x1="-124.46" y1="15.24" x2="-132.08" y2="15.24" width="0.1524" layer="91"/> +<label x="-132.08" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="SPI1_MOSI/PA7"/> +</segment> +</net> +<net name="FT_RTS" class="0"> +<segment> +<wire x1="-124.46" y1="63.5" x2="-132.08" y2="63.5" width="0.1524" layer="91"/> +<label x="-132.08" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="USART2_CTS/WKUP/PA0"/> +</segment> +</net> +<net name="FT_CTS" class="0"> +<segment> +<wire x1="-124.46" y1="66.04" x2="-132.08" y2="66.04" width="0.1524" layer="91"/> +<label x="-132.08" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="USART2_RTS/PA1"/> +</segment> +</net> +<net name="FT_MGMT_RXD" class="0"> +<segment> +<wire x1="-124.46" y1="53.34" x2="-132.08" y2="53.34" width="0.1524" layer="91"/> +<pinref part="U4" gate="IO" pin="USART1_TX/PA9"/> +<label x="-132.08" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_TXD" class="0"> +<segment> +<wire x1="-124.46" y1="50.8" x2="-132.08" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U4" gate="IO" pin="USART1_RX/PA10"/> +<label x="-132.08" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_CTS" class="0"> +<segment> +<wire x1="-124.46" y1="48.26" x2="-132.08" y2="48.26" width="0.1524" layer="91"/> +<label x="-132.08" y="48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="USART1_RTS/PA12"/> +</segment> +</net> +<net name="FT_MGMT_RTS" class="0"> +<segment> +<wire x1="-124.46" y1="45.72" x2="-132.08" y2="45.72" width="0.1524" layer="91"/> +<label x="-132.08" y="45.72" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U4" gate="IO" pin="USART1_CTS/PA11"/> +</segment> +</net> +<net name="FPGA_DONE" class="0"> +<segment> +<wire x1="-45.72" y1="-35.56" x2="-38.1" y2="-35.56" width="0.1524" layer="91"/> +<label x="-38.1" y="-35.56" size="1.27" layer="95" xref="yes"/> +<pinref part="U4" gate="IO" pin="PJ15"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_FPGA_DIS" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="PJ5"/> +<wire x1="-45.72" y1="-10.16" x2="-38.1" y2="-10.16" width="0.1524" layer="91"/> +<label x="-38.1" y="-10.16" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_DTR" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="PA4"/> +<wire x1="-124.46" y1="73.66" x2="-132.08" y2="73.66" width="0.1524" layer="91"/> +<label x="-132.08" y="73.66" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_DTR" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="PA8"/> +<wire x1="-124.46" y1="55.88" x2="-132.08" y2="55.88" width="0.1524" layer="91"/> +<label x="-132.08" y="55.88" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_CS_N" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="PB12"/> +<wire x1="-124.46" y1="38.1" x2="-132.08" y2="38.1" width="0.1524" layer="91"/> +<label x="-132.08" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="KSM_PROM_CS_N" class="0"> +<segment> +<pinref part="U4" gate="IO" pin="PB0"/> +<wire x1="-124.46" y1="22.86" x2="-132.08" y2="22.86" width="0.1524" layer="91"/> +<label x="-132.08" y="22.86" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_2" class="0"> +<segment> +<wire x1="-132.08" y1="-71.12" x2="-124.46" y2="-71.12" width="0.1524" layer="91"/> +<label x="-132.08" y="-71.12" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_3" class="0"> +<segment> +<wire x1="-45.72" y1="22.86" x2="-38.1" y2="22.86" width="0.1524" layer="91"/> +<label x="-38.1" y="22.86" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>SDRAM</description> +<plain> +<text x="-63.5" y="109.22" size="3.81" layer="91">2x512 Mbit SDRAM memory for the ARM</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">SDRAM</text> +<text x="-50.8" y="99.06" size="1.778" layer="91">These packages are TSSOP, but if new packages are to be created +for layout, BGA package is preferred.</text> +</plain> +<instances> +<instance part="FRAME7" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="U5" gate="G$1" x="-88.9" y="25.4"/> +<instance part="P+17" gate="VCC" x="-104.14" y="92.71" smashed="yes"/> +<instance part="P+18" gate="VCC" x="-91.44" y="92.71" smashed="yes"/> +<instance part="SUPPLY40" gate="GND" x="-88.9" y="-43.18"/> +<instance part="P+16" gate="VCC" x="-114.3" y="-49.53" smashed="yes"/> +<instance part="SUPPLY39" gate="GND" x="-114.3" y="-88.9"/> +<instance part="C56" gate="G$1" x="-88.9" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-88.9" y="-55.88" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C54" gate="G$1" x="-93.98" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-93.98" y="-55.88" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C52" gate="G$1" x="-99.06" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-99.06" y="-55.88" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C50" gate="G$1" x="-104.14" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-104.14" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="-104.14" y="-60.96" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-104.14" y="-60.96" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C51" gate="G$1" x="-104.14" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-106.68" y="-81.28" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C49" gate="G$1" x="-109.22" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-111.76" y="-81.28" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C48" gate="G$1" x="-109.22" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-109.22" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="RATED_VOLTAGE" x="-109.22" y="-60.96" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C47" gate="G$1" x="-114.3" y="-60.96" smashed="yes"> +<attribute name="NAME" x="-114.3" y="-55.88" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="-114.3" y="-60.96" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-114.3" y="-60.96" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C57" gate="G$1" x="-88.9" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-91.44" y="-81.28" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C55" gate="G$1" x="-93.98" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-96.52" y="-81.28" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C53" gate="G$1" x="-99.06" y="-73.66" smashed="yes"> +<attribute name="NAME" x="-101.6" y="-81.28" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="U6" gate="G$1" x="88.9" y="22.86"/> +<instance part="P+20" gate="VCC" x="73.66" y="90.17" smashed="yes"/> +<instance part="P+21" gate="VCC" x="86.36" y="90.17" smashed="yes"/> +<instance part="SUPPLY42" gate="GND" x="88.9" y="-45.72"/> +<instance part="P+19" gate="VCC" x="63.5" y="-52.07" smashed="yes"/> +<instance part="SUPPLY41" gate="GND" x="63.5" y="-91.44"/> +<instance part="C67" gate="G$1" x="88.9" y="-63.5" smashed="yes"> +<attribute name="NAME" x="88.9" y="-58.42" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C65" gate="G$1" x="83.82" y="-63.5" smashed="yes"> +<attribute name="NAME" x="83.82" y="-58.42" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C63" gate="G$1" x="78.74" y="-63.5" smashed="yes"> +<attribute name="NAME" x="78.74" y="-58.42" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C61" gate="G$1" x="73.66" y="-63.5" smashed="yes"> +<attribute name="NAME" x="73.66" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="73.66" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="73.66" y="-63.5" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C62" gate="G$1" x="73.66" y="-76.2" smashed="yes"> +<attribute name="NAME" x="71.12" y="-83.82" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C60" gate="G$1" x="68.58" y="-76.2" smashed="yes"> +<attribute name="NAME" x="66.04" y="-83.82" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C59" gate="G$1" x="68.58" y="-63.5" smashed="yes"> +<attribute name="NAME" x="68.58" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="RATED_VOLTAGE" x="68.58" y="-63.5" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C58" gate="G$1" x="63.5" y="-63.5" smashed="yes"> +<attribute name="NAME" x="63.5" y="-58.42" size="1.27" layer="95" font="vector"/> +<attribute name="DIELECTRIC" x="63.5" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="63.5" y="-63.5" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C68" gate="G$1" x="88.9" y="-76.2" smashed="yes"> +<attribute name="NAME" x="86.36" y="-83.82" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C66" gate="G$1" x="83.82" y="-76.2" smashed="yes"> +<attribute name="NAME" x="81.28" y="-83.82" size="1.27" layer="95" font="vector"/> +</instance> +<instance part="C64" gate="G$1" x="78.74" y="-76.2" smashed="yes"> +<attribute name="NAME" x="76.2" y="-83.82" size="1.27" layer="95" font="vector"/> +</instance> +</instances> +<busses> +<bus name="FMC_A[0..25]"> +<segment> +<wire x1="-134.62" y1="81.28" x2="-148.59" y2="81.28" width="0.762" layer="92"/> +<wire x1="-134.62" y1="81.28" x2="-134.62" y2="35.56" width="0.762" layer="92"/> +<label x="-151.13" y="83.82" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="43.18" y1="78.74" x2="29.21" y2="78.74" width="0.762" layer="92"/> +<wire x1="43.18" y1="78.74" x2="43.18" y2="33.02" width="0.762" layer="92"/> +<label x="26.67" y="81.28" size="1.778" layer="95"/> +</segment> +</bus> +<bus name="FMC_D[0..31]"> +<segment> +<wire x1="-43.18" y1="-2.54" x2="-43.18" y2="81.28" width="0.762" layer="92"/> +<wire x1="-43.18" y1="81.28" x2="-27.94" y2="81.28" width="0.762" layer="92"/> +<label x="-43.18" y="81.28" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="134.62" y1="-5.08" x2="134.62" y2="78.74" width="0.762" layer="92"/> +<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.762" layer="92"/> +<label x="134.62" y="78.74" size="1.778" layer="95"/> +</segment> +</bus> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U5" gate="G$1" pin="VSS@86"/> +<wire x1="-73.66" y1="-33.02" x2="-73.66" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="-38.1" x2="-76.2" y2="-38.1" width="0.1524" layer="91"/> +<pinref part="U5" gate="G$1" pin="VSSQ@6"/> +<wire x1="-76.2" y1="-38.1" x2="-78.74" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="-38.1" x2="-81.28" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-38.1" x2="-88.9" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="-38.1" x2="-91.44" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="-38.1" x2="-93.98" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-38.1" x2="-96.52" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-38.1" x2="-99.06" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-38.1" x2="-101.6" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-101.6" y1="-38.1" x2="-104.14" y2="-38.1" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-38.1" x2="-104.14" y2="-33.02" width="0.1524" layer="91"/> +<pinref part="U5" gate="G$1" pin="VSSQ@12"/> +<wire x1="-101.6" y1="-33.02" x2="-101.6" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-101.6" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@32"/> +<wire x1="-99.06" y1="-33.02" x2="-99.06" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-99.06" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@38"/> +<wire x1="-96.52" y1="-33.02" x2="-96.52" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-96.52" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@46"/> +<wire x1="-93.98" y1="-33.02" x2="-93.98" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-93.98" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@52"/> +<wire x1="-91.44" y1="-33.02" x2="-91.44" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-91.44" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@78"/> +<wire x1="-88.9" y1="-33.02" x2="-88.9" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-88.9" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSSQ@84"/> +<wire x1="-86.36" y1="-33.02" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-86.36" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSS@44"/> +<wire x1="-81.28" y1="-33.02" x2="-81.28" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-81.28" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSS@58"/> +<wire x1="-78.74" y1="-33.02" x2="-78.74" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-78.74" y="-38.1"/> +<pinref part="U5" gate="G$1" pin="VSS@72"/> +<wire x1="-76.2" y1="-33.02" x2="-76.2" y2="-38.1" width="0.1524" layer="91"/> +<junction x="-76.2" y="-38.1"/> +<pinref part="SUPPLY40" gate="GND" pin="GND"/> +<wire x1="-88.9" y1="-40.64" x2="-88.9" y2="-38.1" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C47" gate="G$1" pin="2"/> +<pinref part="SUPPLY39" gate="GND" pin="GND"/> +<wire x1="-88.9" y1="-66.04" x2="-93.98" y2="-66.04" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-66.04" x2="-99.06" y2="-66.04" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-66.04" x2="-104.14" y2="-66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-66.04" x2="-109.22" y2="-66.04" width="0.1524" layer="91"/> +<wire x1="-109.22" y1="-66.04" x2="-114.3" y2="-66.04" width="0.1524" layer="91"/> +<wire x1="-114.3" y1="-66.04" x2="-114.3" y2="-78.74" width="0.1524" layer="91"/> +<junction x="-114.3" y="-66.04"/> +<wire x1="-114.3" y1="-78.74" x2="-114.3" y2="-86.36" width="0.1524" layer="91"/> +<junction x="-114.3" y="-78.74"/> +<pinref part="C56" gate="G$1" pin="2"/> +<pinref part="C54" gate="G$1" pin="2"/> +<junction x="-93.98" y="-66.04"/> +<pinref part="C52" gate="G$1" pin="2"/> +<junction x="-99.06" y="-66.04"/> +<pinref part="C50" gate="G$1" pin="2"/> +<junction x="-104.14" y="-66.04"/> +<pinref part="C48" gate="G$1" pin="2"/> +<junction x="-109.22" y="-66.04"/> +<pinref part="C57" gate="G$1" pin="2"/> +<wire x1="-88.9" y1="-78.74" x2="-93.98" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="C55" gate="G$1" pin="2"/> +<junction x="-93.98" y="-78.74"/> +<wire x1="-93.98" y1="-78.74" x2="-99.06" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="C53" gate="G$1" pin="2"/> +<junction x="-99.06" y="-78.74"/> +<wire x1="-99.06" y1="-78.74" x2="-104.14" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="C51" gate="G$1" pin="2"/> +<junction x="-104.14" y="-78.74"/> +<wire x1="-104.14" y1="-78.74" x2="-109.22" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="C49" gate="G$1" pin="2"/> +<junction x="-109.22" y="-78.74"/> +<wire x1="-109.22" y1="-78.74" x2="-114.3" y2="-78.74" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="VSS@86"/> +<wire x1="104.14" y1="-35.56" x2="104.14" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="104.14" y1="-40.64" x2="101.6" y2="-40.64" width="0.1524" layer="91"/> +<pinref part="U6" gate="G$1" pin="VSSQ@6"/> +<wire x1="101.6" y1="-40.64" x2="99.06" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-40.64" x2="96.52" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="96.52" y1="-40.64" x2="91.44" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="91.44" y1="-40.64" x2="88.9" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="88.9" y1="-40.64" x2="86.36" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="86.36" y1="-40.64" x2="83.82" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-40.64" x2="81.28" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="81.28" y1="-40.64" x2="78.74" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-40.64" x2="76.2" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="76.2" y1="-40.64" x2="73.66" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="73.66" y1="-40.64" x2="73.66" y2="-35.56" width="0.1524" layer="91"/> +<pinref part="U6" gate="G$1" pin="VSSQ@12"/> +<wire x1="76.2" y1="-35.56" x2="76.2" y2="-40.64" width="0.1524" layer="91"/> +<junction x="76.2" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@32"/> +<wire x1="78.74" y1="-35.56" x2="78.74" y2="-40.64" width="0.1524" layer="91"/> +<junction x="78.74" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@38"/> +<wire x1="81.28" y1="-35.56" x2="81.28" y2="-40.64" width="0.1524" layer="91"/> +<junction x="81.28" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@46"/> +<wire x1="83.82" y1="-35.56" x2="83.82" y2="-40.64" width="0.1524" layer="91"/> +<junction x="83.82" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@52"/> +<wire x1="86.36" y1="-35.56" x2="86.36" y2="-40.64" width="0.1524" layer="91"/> +<junction x="86.36" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@78"/> +<wire x1="88.9" y1="-35.56" x2="88.9" y2="-40.64" width="0.1524" layer="91"/> +<junction x="88.9" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSSQ@84"/> +<wire x1="91.44" y1="-35.56" x2="91.44" y2="-40.64" width="0.1524" layer="91"/> +<junction x="91.44" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSS@44"/> +<wire x1="96.52" y1="-35.56" x2="96.52" y2="-40.64" width="0.1524" layer="91"/> +<junction x="96.52" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSS@58"/> +<wire x1="99.06" y1="-35.56" x2="99.06" y2="-40.64" width="0.1524" layer="91"/> +<junction x="99.06" y="-40.64"/> +<pinref part="U6" gate="G$1" pin="VSS@72"/> +<wire x1="101.6" y1="-35.56" x2="101.6" y2="-40.64" width="0.1524" layer="91"/> +<junction x="101.6" y="-40.64"/> +<pinref part="SUPPLY42" gate="GND" pin="GND"/> +<wire x1="88.9" y1="-43.18" x2="88.9" y2="-40.64" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C58" gate="G$1" pin="2"/> +<pinref part="SUPPLY41" gate="GND" pin="GND"/> +<wire x1="88.9" y1="-68.58" x2="83.82" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-68.58" x2="78.74" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-68.58" x2="73.66" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="73.66" y1="-68.58" x2="68.58" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="68.58" y1="-68.58" x2="63.5" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="63.5" y1="-68.58" x2="63.5" y2="-81.28" width="0.1524" layer="91"/> +<junction x="63.5" y="-68.58"/> +<wire x1="63.5" y1="-81.28" x2="63.5" y2="-88.9" width="0.1524" layer="91"/> +<junction x="63.5" y="-81.28"/> +<pinref part="C67" gate="G$1" pin="2"/> +<pinref part="C65" gate="G$1" pin="2"/> +<junction x="83.82" y="-68.58"/> +<pinref part="C63" gate="G$1" pin="2"/> +<junction x="78.74" y="-68.58"/> +<pinref part="C61" gate="G$1" pin="2"/> +<junction x="73.66" y="-68.58"/> +<pinref part="C59" gate="G$1" pin="2"/> +<junction x="68.58" y="-68.58"/> +<pinref part="C68" gate="G$1" pin="2"/> +<wire x1="88.9" y1="-81.28" x2="83.82" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="C66" gate="G$1" pin="2"/> +<junction x="83.82" y="-81.28"/> +<wire x1="83.82" y1="-81.28" x2="78.74" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="C64" gate="G$1" pin="2"/> +<junction x="78.74" y="-81.28"/> +<wire x1="78.74" y1="-81.28" x2="73.66" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="C62" gate="G$1" pin="2"/> +<junction x="73.66" y="-81.28"/> +<wire x1="73.66" y1="-81.28" x2="68.58" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="C60" gate="G$1" pin="2"/> +<junction x="68.58" y="-81.28"/> +<wire x1="68.58" y1="-81.28" x2="63.5" y2="-81.28" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="P+17" gate="VCC" pin="VCC"/> +<wire x1="-104.14" y1="90.17" x2="-104.14" y2="86.36" width="0.1524" layer="91"/> +<label x="-119.38" y="88.9" size="1.778" layer="95"/> +<pinref part="U5" gate="G$1" pin="VDD@43"/> +<wire x1="-104.14" y1="86.36" x2="-104.14" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="86.36" x2="-101.6" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-101.6" y1="86.36" x2="-99.06" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="86.36" x2="-96.52" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="86.36" x2="-96.52" y2="83.82" width="0.1524" layer="91"/> +<junction x="-104.14" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDD@29"/> +<wire x1="-99.06" y1="83.82" x2="-99.06" y2="86.36" width="0.1524" layer="91"/> +<junction x="-99.06" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDD@15"/> +<wire x1="-101.6" y1="83.82" x2="-101.6" y2="86.36" width="0.1524" layer="91"/> +<junction x="-101.6" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDD@1"/> +</segment> +<segment> +<pinref part="P+18" gate="VCC" pin="VCC"/> +<wire x1="-91.44" y1="90.17" x2="-91.44" y2="86.36" width="0.1524" layer="91"/> +<label x="-88.9" y="88.9" size="1.778" layer="95"/> +<pinref part="U5" gate="G$1" pin="VDDQ@81"/> +<wire x1="-91.44" y1="86.36" x2="-91.44" y2="83.82" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="86.36" x2="-88.9" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="86.36" x2="-86.36" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="86.36" x2="-83.82" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="86.36" x2="-81.28" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="86.36" x2="-78.74" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="86.36" x2="-76.2" y2="86.36" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="86.36" x2="-76.2" y2="83.82" width="0.1524" layer="91"/> +<junction x="-91.44" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@75"/> +<wire x1="-78.74" y1="83.82" x2="-78.74" y2="86.36" width="0.1524" layer="91"/> +<junction x="-78.74" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@55"/> +<wire x1="-81.28" y1="83.82" x2="-81.28" y2="86.36" width="0.1524" layer="91"/> +<junction x="-81.28" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@49"/> +<wire x1="-83.82" y1="83.82" x2="-83.82" y2="86.36" width="0.1524" layer="91"/> +<junction x="-83.82" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@41"/> +<wire x1="-86.36" y1="83.82" x2="-86.36" y2="86.36" width="0.1524" layer="91"/> +<junction x="-86.36" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@35"/> +<wire x1="-88.9" y1="83.82" x2="-88.9" y2="86.36" width="0.1524" layer="91"/> +<junction x="-88.9" y="86.36"/> +<pinref part="U5" gate="G$1" pin="VDDQ@3"/> +</segment> +<segment> +<pinref part="C47" gate="G$1" pin="1"/> +<pinref part="P+16" gate="VCC" pin="VCC"/> +<wire x1="-114.3" y1="-52.07" x2="-114.3" y2="-58.42" width="0.1524" layer="91"/> +<junction x="-114.3" y="-58.42"/> +<wire x1="-114.3" y1="-58.42" x2="-109.22" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C48" gate="G$1" pin="1"/> +<junction x="-109.22" y="-58.42"/> +<wire x1="-109.22" y1="-58.42" x2="-104.14" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C50" gate="G$1" pin="1"/> +<junction x="-104.14" y="-58.42"/> +<wire x1="-104.14" y1="-58.42" x2="-99.06" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C52" gate="G$1" pin="1"/> +<junction x="-99.06" y="-58.42"/> +<wire x1="-99.06" y1="-58.42" x2="-93.98" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C54" gate="G$1" pin="1"/> +<junction x="-93.98" y="-58.42"/> +<wire x1="-93.98" y1="-58.42" x2="-88.9" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C56" gate="G$1" pin="1"/> +<wire x1="-88.9" y1="-58.42" x2="-83.82" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-58.42" x2="-83.82" y2="-71.12" width="0.1524" layer="91"/> +<junction x="-88.9" y="-58.42"/> +<pinref part="C49" gate="G$1" pin="1"/> +<pinref part="C51" gate="G$1" pin="1"/> +<junction x="-104.14" y="-71.12"/> +<wire x1="-88.9" y1="-71.12" x2="-93.98" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-93.98" y1="-71.12" x2="-99.06" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-71.12" x2="-104.14" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="-71.12" x2="-109.22" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C53" gate="G$1" pin="1"/> +<junction x="-99.06" y="-71.12"/> +<pinref part="C55" gate="G$1" pin="1"/> +<junction x="-93.98" y="-71.12"/> +<pinref part="C57" gate="G$1" pin="1"/> +<wire x1="-83.82" y1="-71.12" x2="-88.9" y2="-71.12" width="0.1524" layer="91"/> +<junction x="-88.9" y="-71.12"/> +<label x="-129.54" y="-53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+20" gate="VCC" pin="VCC"/> +<wire x1="73.66" y1="87.63" x2="73.66" y2="83.82" width="0.1524" layer="91"/> +<label x="58.42" y="86.36" size="1.778" layer="95"/> +<pinref part="U6" gate="G$1" pin="VDD@43"/> +<wire x1="73.66" y1="83.82" x2="73.66" y2="81.28" width="0.1524" layer="91"/> +<wire x1="73.66" y1="83.82" x2="76.2" y2="83.82" width="0.1524" layer="91"/> +<wire x1="76.2" y1="83.82" x2="78.74" y2="83.82" width="0.1524" layer="91"/> +<wire x1="78.74" y1="83.82" x2="81.28" y2="83.82" width="0.1524" layer="91"/> +<wire x1="81.28" y1="83.82" x2="81.28" y2="81.28" width="0.1524" layer="91"/> +<junction x="73.66" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDD@29"/> +<wire x1="78.74" y1="81.28" x2="78.74" y2="83.82" width="0.1524" layer="91"/> +<junction x="78.74" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDD@15"/> +<wire x1="76.2" y1="81.28" x2="76.2" y2="83.82" width="0.1524" layer="91"/> +<junction x="76.2" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDD@1"/> +</segment> +<segment> +<pinref part="P+21" gate="VCC" pin="VCC"/> +<wire x1="86.36" y1="87.63" x2="86.36" y2="83.82" width="0.1524" layer="91"/> +<label x="88.9" y="86.36" size="1.778" layer="95"/> +<pinref part="U6" gate="G$1" pin="VDDQ@81"/> +<wire x1="86.36" y1="83.82" x2="86.36" y2="81.28" width="0.1524" layer="91"/> +<wire x1="86.36" y1="83.82" x2="88.9" y2="83.82" width="0.1524" layer="91"/> +<wire x1="88.9" y1="83.82" x2="91.44" y2="83.82" width="0.1524" layer="91"/> +<wire x1="91.44" y1="83.82" x2="93.98" y2="83.82" width="0.1524" layer="91"/> +<wire x1="93.98" y1="83.82" x2="96.52" y2="83.82" width="0.1524" layer="91"/> +<wire x1="96.52" y1="83.82" x2="99.06" y2="83.82" width="0.1524" layer="91"/> +<wire x1="99.06" y1="83.82" x2="101.6" y2="83.82" width="0.1524" layer="91"/> +<wire x1="101.6" y1="83.82" x2="101.6" y2="81.28" width="0.1524" layer="91"/> +<junction x="86.36" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@75"/> +<wire x1="99.06" y1="81.28" x2="99.06" y2="83.82" width="0.1524" layer="91"/> +<junction x="99.06" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@55"/> +<wire x1="96.52" y1="81.28" x2="96.52" y2="83.82" width="0.1524" layer="91"/> +<junction x="96.52" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@49"/> +<wire x1="93.98" y1="81.28" x2="93.98" y2="83.82" width="0.1524" layer="91"/> +<junction x="93.98" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@41"/> +<wire x1="91.44" y1="81.28" x2="91.44" y2="83.82" width="0.1524" layer="91"/> +<junction x="91.44" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@35"/> +<wire x1="88.9" y1="81.28" x2="88.9" y2="83.82" width="0.1524" layer="91"/> +<junction x="88.9" y="83.82"/> +<pinref part="U6" gate="G$1" pin="VDDQ@3"/> +</segment> +<segment> +<pinref part="C58" gate="G$1" pin="1"/> +<pinref part="P+19" gate="VCC" pin="VCC"/> +<wire x1="63.5" y1="-54.61" x2="63.5" y2="-60.96" width="0.1524" layer="91"/> +<junction x="63.5" y="-60.96"/> +<wire x1="63.5" y1="-60.96" x2="68.58" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C59" gate="G$1" pin="1"/> +<junction x="68.58" y="-60.96"/> +<wire x1="68.58" y1="-60.96" x2="73.66" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C61" gate="G$1" pin="1"/> +<junction x="73.66" y="-60.96"/> +<wire x1="73.66" y1="-60.96" x2="78.74" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C63" gate="G$1" pin="1"/> +<junction x="78.74" y="-60.96"/> +<wire x1="78.74" y1="-60.96" x2="83.82" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C65" gate="G$1" pin="1"/> +<junction x="83.82" y="-60.96"/> +<wire x1="83.82" y1="-60.96" x2="88.9" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C67" gate="G$1" pin="1"/> +<wire x1="88.9" y1="-60.96" x2="93.98" y2="-60.96" width="0.1524" layer="91"/> +<wire x1="93.98" y1="-60.96" x2="93.98" y2="-73.66" width="0.1524" layer="91"/> +<junction x="88.9" y="-60.96"/> +<pinref part="C60" gate="G$1" pin="1"/> +<pinref part="C62" gate="G$1" pin="1"/> +<junction x="73.66" y="-73.66"/> +<wire x1="88.9" y1="-73.66" x2="83.82" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-73.66" x2="78.74" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-73.66" x2="73.66" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="73.66" y1="-73.66" x2="68.58" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C64" gate="G$1" pin="1"/> +<junction x="78.74" y="-73.66"/> +<pinref part="C66" gate="G$1" pin="1"/> +<junction x="83.82" y="-73.66"/> +<pinref part="C68" gate="G$1" pin="1"/> +<wire x1="93.98" y1="-73.66" x2="88.9" y2="-73.66" width="0.1524" layer="91"/> +<junction x="88.9" y="-73.66"/> +<label x="48.26" y="-55.88" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A0" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A0"/> +<wire x1="-134.62" y1="76.2" x2="-119.38" y2="76.2" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A0"/> +<wire x1="43.18" y1="73.66" x2="58.42" y2="73.66" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A1" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A1"/> +<wire x1="-134.62" y1="73.66" x2="-119.38" y2="73.66" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A1"/> +<wire x1="43.18" y1="71.12" x2="58.42" y2="71.12" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A2" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A2"/> +<wire x1="-134.62" y1="71.12" x2="-119.38" y2="71.12" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A2"/> +<wire x1="43.18" y1="68.58" x2="58.42" y2="68.58" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A3" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A3"/> +<wire x1="-134.62" y1="68.58" x2="-119.38" y2="68.58" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A3"/> +<wire x1="43.18" y1="66.04" x2="58.42" y2="66.04" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A4" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A4"/> +<wire x1="-134.62" y1="66.04" x2="-119.38" y2="66.04" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A4"/> +<wire x1="43.18" y1="63.5" x2="58.42" y2="63.5" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A5" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A5"/> +<wire x1="-134.62" y1="63.5" x2="-119.38" y2="63.5" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A5"/> +<wire x1="43.18" y1="60.96" x2="58.42" y2="60.96" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A6" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A6"/> +<wire x1="-134.62" y1="60.96" x2="-119.38" y2="60.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A6"/> +<wire x1="43.18" y1="58.42" x2="58.42" y2="58.42" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A7" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A7"/> +<wire x1="-134.62" y1="58.42" x2="-119.38" y2="58.42" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A7"/> +<wire x1="43.18" y1="55.88" x2="58.42" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A8" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A8"/> +<wire x1="-134.62" y1="55.88" x2="-119.38" y2="55.88" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A8"/> +<wire x1="43.18" y1="53.34" x2="58.42" y2="53.34" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A9" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A9"/> +<wire x1="-134.62" y1="53.34" x2="-119.38" y2="53.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A9"/> +<wire x1="43.18" y1="50.8" x2="58.42" y2="50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A10" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A10"/> +<wire x1="-134.62" y1="50.8" x2="-119.38" y2="50.8" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A10"/> +<wire x1="43.18" y1="48.26" x2="58.42" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A11" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A11"/> +<wire x1="-134.62" y1="48.26" x2="-119.38" y2="48.26" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A11"/> +<wire x1="43.18" y1="45.72" x2="58.42" y2="45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_A12" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="A12"/> +<wire x1="-134.62" y1="45.72" x2="-119.38" y2="45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="A12"/> +<wire x1="43.18" y1="43.18" x2="58.42" y2="43.18" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D0" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ0"/> +<wire x1="-43.18" y1="76.2" x2="-58.42" y2="76.2" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ0"/> +<wire x1="134.62" y1="73.66" x2="119.38" y2="73.66" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D1" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ1"/> +<wire x1="-43.18" y1="73.66" x2="-58.42" y2="73.66" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ1"/> +<wire x1="134.62" y1="71.12" x2="119.38" y2="71.12" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D2" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ2"/> +<wire x1="-43.18" y1="71.12" x2="-58.42" y2="71.12" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ2"/> +<wire x1="134.62" y1="68.58" x2="119.38" y2="68.58" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D3" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ3"/> +<wire x1="-43.18" y1="68.58" x2="-58.42" y2="68.58" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ3"/> +<wire x1="134.62" y1="66.04" x2="119.38" y2="66.04" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D4" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ4"/> +<wire x1="-43.18" y1="66.04" x2="-58.42" y2="66.04" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ4"/> +<wire x1="134.62" y1="63.5" x2="119.38" y2="63.5" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D5" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ5"/> +<wire x1="-43.18" y1="63.5" x2="-58.42" y2="63.5" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ5"/> +<wire x1="134.62" y1="60.96" x2="119.38" y2="60.96" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D6" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ6"/> +<wire x1="-43.18" y1="60.96" x2="-58.42" y2="60.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ6"/> +<wire x1="134.62" y1="58.42" x2="119.38" y2="58.42" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D7" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ7"/> +<wire x1="-43.18" y1="58.42" x2="-58.42" y2="58.42" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ7"/> +<wire x1="134.62" y1="55.88" x2="119.38" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D8" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ8"/> +<wire x1="-43.18" y1="55.88" x2="-58.42" y2="55.88" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ8"/> +<wire x1="134.62" y1="53.34" x2="119.38" y2="53.34" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D10" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ9"/> +<wire x1="-43.18" y1="53.34" x2="-58.42" y2="53.34" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U5" gate="G$1" pin="DQ10"/> +<wire x1="-43.18" y1="50.8" x2="-58.42" y2="50.8" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ9"/> +<wire x1="134.62" y1="50.8" x2="119.38" y2="50.8" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ10"/> +<wire x1="134.62" y1="48.26" x2="119.38" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D11" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ11"/> +<wire x1="-43.18" y1="48.26" x2="-58.42" y2="48.26" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ11"/> +<wire x1="134.62" y1="45.72" x2="119.38" y2="45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D12" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ12"/> +<wire x1="-43.18" y1="45.72" x2="-58.42" y2="45.72" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ12"/> +<wire x1="134.62" y1="43.18" x2="119.38" y2="43.18" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D13" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ13"/> +<wire x1="-43.18" y1="43.18" x2="-58.42" y2="43.18" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ13"/> +<wire x1="134.62" y1="40.64" x2="119.38" y2="40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D14" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ14"/> +<wire x1="-43.18" y1="40.64" x2="-58.42" y2="40.64" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ14"/> +<wire x1="134.62" y1="38.1" x2="119.38" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D15" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ15"/> +<wire x1="-43.18" y1="38.1" x2="-58.42" y2="38.1" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ15"/> +<wire x1="134.62" y1="35.56" x2="119.38" y2="35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D16" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ16"/> +<wire x1="-43.18" y1="35.56" x2="-58.42" y2="35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ16"/> +<wire x1="134.62" y1="33.02" x2="119.38" y2="33.02" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D17" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ17"/> +<wire x1="-43.18" y1="33.02" x2="-58.42" y2="33.02" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ17"/> +<wire x1="134.62" y1="30.48" x2="119.38" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D18" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ18"/> +<wire x1="-43.18" y1="30.48" x2="-58.42" y2="30.48" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ18"/> +<wire x1="134.62" y1="27.94" x2="119.38" y2="27.94" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D19" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ19"/> +<wire x1="-43.18" y1="27.94" x2="-58.42" y2="27.94" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ19"/> +<wire x1="134.62" y1="25.4" x2="119.38" y2="25.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D20" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ20"/> +<wire x1="-43.18" y1="25.4" x2="-58.42" y2="25.4" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ20"/> +<wire x1="134.62" y1="22.86" x2="119.38" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D21" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ21"/> +<wire x1="-43.18" y1="22.86" x2="-58.42" y2="22.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ21"/> +<wire x1="134.62" y1="20.32" x2="119.38" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D22" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ22"/> +<wire x1="-43.18" y1="20.32" x2="-58.42" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ22"/> +<wire x1="134.62" y1="17.78" x2="119.38" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D23" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ23"/> +<wire x1="-43.18" y1="17.78" x2="-58.42" y2="17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ23"/> +<wire x1="134.62" y1="15.24" x2="119.38" y2="15.24" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D24" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ24"/> +<wire x1="-43.18" y1="15.24" x2="-58.42" y2="15.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ24"/> +<wire x1="134.62" y1="12.7" x2="119.38" y2="12.7" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D25" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ25"/> +<wire x1="-43.18" y1="12.7" x2="-58.42" y2="12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ25"/> +<wire x1="134.62" y1="10.16" x2="119.38" y2="10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D26" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ26"/> +<wire x1="-43.18" y1="10.16" x2="-58.42" y2="10.16" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ26"/> +<wire x1="134.62" y1="7.62" x2="119.38" y2="7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D27" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ27"/> +<wire x1="-43.18" y1="7.62" x2="-58.42" y2="7.62" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ27"/> +<wire x1="134.62" y1="5.08" x2="119.38" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D28" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ28"/> +<wire x1="-43.18" y1="5.08" x2="-58.42" y2="5.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ28"/> +<wire x1="134.62" y1="2.54" x2="119.38" y2="2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D29" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ29"/> +<wire x1="-43.18" y1="2.54" x2="-58.42" y2="2.54" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ29"/> +<wire x1="134.62" y1="0" x2="119.38" y2="0" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D30" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ30"/> +<wire x1="-43.18" y1="0" x2="-58.42" y2="0" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ30"/> +<wire x1="134.62" y1="-2.54" x2="119.38" y2="-2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_D31" class="2"> +<segment> +<pinref part="U5" gate="G$1" pin="DQ31"/> +<wire x1="-43.18" y1="-2.54" x2="-58.42" y2="-2.54" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQ31"/> +<wire x1="134.62" y1="-5.08" x2="119.38" y2="-5.08" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FMC_SDCKE0" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="CKE"/> +<wire x1="-119.38" y1="2.54" x2="-134.62" y2="2.54" width="0.1524" layer="91"/> +<label x="-134.62" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDNE0" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="!CS"/> +<wire x1="-119.38" y1="-10.16" x2="-134.62" y2="-10.16" width="0.1524" layer="91"/> +<label x="-134.62" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDNWE" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="!WE"/> +<wire x1="-119.38" y1="-22.86" x2="-134.62" y2="-22.86" width="0.1524" layer="91"/> +<label x="-134.62" y="-22.86" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="!WE"/> +<wire x1="58.42" y1="-25.4" x2="43.18" y2="-25.4" width="0.1524" layer="91"/> +<label x="43.18" y="-25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDNCAS" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="!CAS"/> +<wire x1="-119.38" y1="30.48" x2="-134.62" y2="30.48" width="0.1524" layer="91"/> +<label x="-134.62" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="!CAS"/> +<wire x1="58.42" y1="27.94" x2="43.18" y2="27.94" width="0.1524" layer="91"/> +<label x="43.18" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDNRAS" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="!RAS"/> +<wire x1="-119.38" y1="27.94" x2="-134.62" y2="27.94" width="0.1524" layer="91"/> +<label x="-134.62" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="!RAS"/> +<wire x1="58.42" y1="25.4" x2="43.18" y2="25.4" width="0.1524" layer="91"/> +<label x="43.18" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_A14" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="BA0"/> +<wire x1="-134.62" y1="38.1" x2="-119.38" y2="38.1" width="0.1524" layer="91"/> +<label x="-132.08" y="38.1" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="BA0"/> +<wire x1="43.18" y1="35.56" x2="58.42" y2="35.56" width="0.1524" layer="91"/> +<label x="45.72" y="35.56" size="1.27" layer="95"/> +</segment> +</net> +<net name="FMC_A15" class="3"> +<segment> +<pinref part="U5" gate="G$1" pin="BA1"/> +<wire x1="-134.62" y1="35.56" x2="-119.38" y2="35.56" width="0.1524" layer="91"/> +<label x="-132.08" y="35.56" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="BA1"/> +<wire x1="43.18" y1="33.02" x2="58.42" y2="33.02" width="0.1524" layer="91"/> +<label x="45.72" y="33.02" size="1.27" layer="95"/> +</segment> +</net> +<net name="FMC_NBL0" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="DQM0"/> +<wire x1="-58.42" y1="-7.62" x2="-43.18" y2="-7.62" width="0.1524" layer="91"/> +<label x="-43.18" y="-7.62" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQM0"/> +<wire x1="119.38" y1="-10.16" x2="134.62" y2="-10.16" width="0.1524" layer="91"/> +<label x="134.62" y="-10.16" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NBL1" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="DQM1"/> +<wire x1="-58.42" y1="-10.16" x2="-43.18" y2="-10.16" width="0.1524" layer="91"/> +<label x="-43.18" y="-10.16" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQM1"/> +<wire x1="119.38" y1="-12.7" x2="134.62" y2="-12.7" width="0.1524" layer="91"/> +<label x="134.62" y="-12.7" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NBL2" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="DQM2"/> +<wire x1="-58.42" y1="-12.7" x2="-43.18" y2="-12.7" width="0.1524" layer="91"/> +<label x="-43.18" y="-12.7" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQM2"/> +<wire x1="119.38" y1="-15.24" x2="134.62" y2="-15.24" width="0.1524" layer="91"/> +<label x="134.62" y="-15.24" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NBL3" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="DQM3"/> +<wire x1="-58.42" y1="-15.24" x2="-43.18" y2="-15.24" width="0.1524" layer="91"/> +<label x="-43.18" y="-15.24" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="DQM3"/> +<wire x1="119.38" y1="-17.78" x2="134.62" y2="-17.78" width="0.1524" layer="91"/> +<label x="134.62" y="-17.78" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_SDCLK" class="0"> +<segment> +<pinref part="U5" gate="G$1" pin="CLK"/> +<wire x1="-119.38" y1="15.24" x2="-134.62" y2="15.24" width="0.1524" layer="91"/> +<label x="-134.62" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="U6" gate="G$1" pin="CLK"/> +<wire x1="58.42" y1="12.7" x2="43.18" y2="12.7" width="0.1524" layer="91"/> +<label x="43.18" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDCKE1" class="0"> +<segment> +<pinref part="U6" gate="G$1" pin="CKE"/> +<wire x1="58.42" y1="0" x2="43.18" y2="0" width="0.1524" layer="91"/> +<label x="43.18" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FMC_SDNE1" class="0"> +<segment> +<pinref part="U6" gate="G$1" pin="!CS"/> +<wire x1="58.42" y1="-12.7" x2="43.18" y2="-12.7" width="0.1524" layer="91"/> +<label x="43.18" y="-12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Keystore memory</description> +<plain> +<text x="22.86" y="10.16" size="1.778" layer="91">*) HOLD feature not used</text> +<text x="-40.64" y="45.72" size="2.54" layer="91">This memory holds cryptographic keys +wrapped with the master key.</text> +<text x="-40.64" y="60.96" size="3.81" layer="91">Keystore memory, 128 Mbit</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">Keystore memory</text> +</plain> +<instances> +<instance part="FRAME8" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="IC1" gate="A" x="-7.62" y="-3.81"/> +<instance part="SUPPLY45" gate="GND" x="-30.48" y="-25.4"/> +<instance part="R18" gate="G$1" x="-38.1" y="12.7" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="-38.1" y="12.7" size="1.778" layer="96" rot="R270" display="off"/> +<attribute name="NAME" x="-34.29" y="14.1986" size="1.778" layer="95"/> +<attribute name="VALUE" x="-34.29" y="11.938" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY46" gate="GND" x="43.18" y="-25.4"/> +<instance part="C69" gate="G$1" x="43.18" y="-10.16"> +<attribute name="DIELECTRIC" x="43.18" y="-10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="43.18" y="-10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="43.18" y="-10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+22" gate="VCC" x="-45.72" y="33.02" smashed="yes"/> +<instance part="R17" gate="G$1" x="-45.72" y="12.7" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="-45.72" y="12.7" size="1.778" layer="96" rot="R270" display="off"/> +<attribute name="NAME" x="-52.07" y="14.1986" size="1.778" layer="95"/> +<attribute name="VALUE" x="-52.07" y="11.938" size="1.778" layer="96"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY45" gate="GND" pin="GND"/> +<wire x1="-30.48" y1="-22.86" x2="-30.48" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="VSS"/> +<wire x1="-30.48" y1="-5.08" x2="-25.4" y2="-5.08" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY46" gate="GND" pin="GND"/> +<wire x1="43.18" y1="-22.86" x2="43.18" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="C69" gate="G$1" pin="2"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<label x="-38.1" y="30.48" size="1.778" layer="95"/> +<pinref part="IC1" gate="A" pin="VCC"/> +<wire x1="-45.72" y1="22.86" x2="-45.72" y2="30.48" width="0.1524" layer="91"/> +<wire x1="11.43" y1="2.54" x2="17.78" y2="2.54" width="0.1524" layer="91"/> +<wire x1="17.78" y1="2.54" x2="17.78" y2="22.86" width="0.1524" layer="91"/> +<wire x1="17.78" y1="22.86" x2="-38.1" y2="22.86" width="0.1524" layer="91"/> +<pinref part="IC1" gate="A" pin="!HOLD!/DQ3"/> +<wire x1="-38.1" y1="22.86" x2="-45.72" y2="22.86" width="0.1524" layer="91"/> +<wire x1="11.43" y1="0" x2="17.78" y2="0" width="0.1524" layer="91"/> +<wire x1="17.78" y1="0" x2="17.78" y2="2.54" width="0.1524" layer="91"/> +<junction x="17.78" y="2.54"/> +<wire x1="43.18" y1="0" x2="43.18" y2="-7.62" width="0.1524" layer="91"/> +<wire x1="17.78" y1="0" x2="43.18" y2="0" width="0.1524" layer="91"/> +<junction x="17.78" y="0"/> +<pinref part="C69" gate="G$1" pin="1"/> +<pinref part="P+22" gate="VCC" pin="VCC"/> +<pinref part="R18" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="17.78" x2="-38.1" y2="22.86" width="0.1524" layer="91"/> +<junction x="-38.1" y="22.86"/> +<pinref part="R17" gate="G$1" pin="1"/> +<wire x1="-45.72" y1="22.86" x2="-45.72" y2="17.78" width="0.1524" layer="91"/> +<junction x="-45.72" y="22.86"/> +</segment> +</net> +<net name="KSM_PROM_CS_N" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="!S"/> +<pinref part="R18" gate="G$1" pin="2"/> +<wire x1="-25.4" y1="2.54" x2="-38.1" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="2.54" x2="-38.1" y2="7.62" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="2.54" x2="-53.34" y2="2.54" width="0.1524" layer="91"/> +<junction x="-38.1" y="2.54"/> +<label x="-53.34" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="KSM_PROM_MOSI" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="DQ0"/> +<wire x1="11.43" y1="-5.08" x2="15.24" y2="-5.08" width="0.1524" layer="91"/> +<label x="15.24" y="-5.08" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="KSM_PROM_SCLK" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="C"/> +<wire x1="11.43" y1="-2.54" x2="15.24" y2="-2.54" width="0.1524" layer="91"/> +<label x="15.24" y="-2.54" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="KSM_PROM_MISO" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="DQ1"/> +<wire x1="-25.4" y1="0" x2="-53.34" y2="0" width="0.1524" layer="91"/> +<label x="-53.34" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$23" class="0"> +<segment> +<pinref part="IC1" gate="A" pin="!W!/VPP/DQ2"/> +<wire x1="-25.4" y1="-2.54" x2="-45.72" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="R17" gate="G$1" pin="2"/> +<wire x1="-45.72" y1="7.62" x2="-45.72" y2="-2.54" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Real Time Clock</description> +<plain> +<text x="-45.72" y="0" size="1.778" layer="91">CL 12.5 pF</text> +<text x="20.32" y="-15.24" size="1.778" layer="91">MFP is Multi Function Pin. +GPIO output from RTC.</text> +<text x="10.16" y="25.4" size="1.778" layer="91">i2c pull-ups, typically 10K for 100kHz</text> +<text x="-45.72" y="55.88" size="3.81" layer="91">Real Time Clock</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">Real Time Clock</text> +</plain> +<instances> +<instance part="U7" gate="A" x="0" y="0"/> +<instance part="SUPPLY49" gate="GND" x="-20.32" y="-22.86"/> +<instance part="P+23" gate="VCC" x="-20.32" y="22.86" smashed="yes"/> +<instance part="P+24" gate="VCC" x="-15.24" y="22.86" smashed="yes"/> +<instance part="C71" gate="G$1" x="-33.02" y="-15.24" smashed="yes" rot="R180"> +<attribute name="NAME" x="-38.1" y="-17.78" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-38.1" y="-20.32" size="1.778" layer="96" rot="R180"/> +<attribute name="DIELECTRIC" x="-38.1" y="-22.86" size="1.778" layer="96" rot="R180"/> +<attribute name="RATED_VOLTAGE" x="-33.02" y="-15.24" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C70" gate="G$1" x="-48.26" y="-15.24" smashed="yes" rot="R180"> +<attribute name="NAME" x="-38.1" y="-15.24" size="1.778" layer="95" rot="R180"/> +<attribute name="DIELECTRIC" x="-48.26" y="-15.24" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="RATED_VOLTAGE" x="-48.26" y="-15.24" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SUPPLY47" gate="GND" x="-48.26" y="-22.86"/> +<instance part="SUPPLY48" gate="GND" x="-33.02" y="-22.86"/> +<instance part="FRAME9" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="X1" gate="G$1" x="-40.64" y="-10.16"> +<attribute name="MPN" x="-40.64" y="-10.16" size="1.778" layer="96" display="off"/> +<attribute name="OC_FARNELL" x="-40.64" y="-10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+25" gate="VCC" x="27.94" y="22.86" smashed="yes"/> +<instance part="R21" gate="G$1" x="33.02" y="10.16" smashed="yes" rot="R270"> +<attribute name="NAME" x="40.64" y="10.16" size="1.778" layer="95"/> +<attribute name="VALUE" x="40.64" y="7.62" size="1.778" layer="96"/> +<attribute name="TOLERANCE" x="33.02" y="10.16" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="R20" gate="G$1" x="27.94" y="10.16" smashed="yes" rot="R270"> +<attribute name="NAME" x="40.64" y="12.7" size="1.778" layer="95"/> +<attribute name="TOLERANCE" x="27.94" y="10.16" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="R19" gate="G$1" x="22.86" y="10.16" smashed="yes" rot="R270"> +<attribute name="NAME" x="40.64" y="15.24" size="1.778" layer="95"/> +<attribute name="TOLERANCE" x="22.86" y="10.16" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="3V3_BATT" class="0"> +<segment> +<wire x1="-20.32" y1="2.54" x2="-20.32" y2="20.32" width="0.1524" layer="91"/> +<pinref part="P+23" gate="VCC" pin="VCC"/> +<label x="-33.02" y="20.32" size="1.27" layer="95"/> +<pinref part="U7" gate="A" pin="VBAT"/> +<wire x1="-15.24" y1="2.54" x2="-20.32" y2="2.54" width="0.1524" layer="91"/> +</segment> +</net> +<net name="GND" class="1"> +<segment> +<pinref part="U7" gate="A" pin="VSS"/> +<pinref part="SUPPLY49" gate="GND" pin="GND"/> +<wire x1="-15.24" y1="-10.16" x2="-20.32" y2="-10.16" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-10.16" x2="-20.32" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C71" gate="G$1" pin="1"/> +<pinref part="SUPPLY48" gate="GND" pin="GND"/> +<wire x1="-33.02" y1="-17.78" x2="-33.02" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C70" gate="G$1" pin="1"/> +<pinref part="SUPPLY47" gate="GND" pin="GND"/> +<wire x1="-48.26" y1="-17.78" x2="-48.26" y2="-20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="U7" gate="A" pin="VCC"/> +<wire x1="-15.24" y1="5.08" x2="-15.24" y2="20.32" width="0.1524" layer="91"/> +<pinref part="P+24" gate="VCC" pin="VCC"/> +<label x="-10.16" y="20.32" size="1.27" layer="95"/> +</segment> +</net> +<net name="RTC_X1" class="0"> +<segment> +<pinref part="U7" gate="A" pin="X1"/> +<pinref part="C70" gate="G$1" pin="2"/> +<wire x1="-48.26" y1="-10.16" x2="-45.72" y2="-10.16" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-2.54" x2="-48.26" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="-2.54" x2="-48.26" y2="-10.16" width="0.1524" layer="91"/> +<junction x="-48.26" y="-10.16"/> +<pinref part="X1" gate="G$1" pin="P$1"/> +</segment> +</net> +<net name="RTC_X2" class="0"> +<segment> +<pinref part="U7" gate="A" pin="X2"/> +<pinref part="C71" gate="G$1" pin="2"/> +<wire x1="-35.56" y1="-10.16" x2="-33.02" y2="-10.16" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-5.08" x2="-33.02" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="-5.08" x2="-33.02" y2="-10.16" width="0.1524" layer="91"/> +<junction x="-33.02" y="-10.16"/> +<pinref part="X1" gate="G$1" pin="P$2"/> +</segment> +</net> +<net name="RTC_MFP" class="0"> +<segment> +<pinref part="U7" gate="A" pin="MFP"/> +<wire x1="15.24" y1="2.54" x2="33.02" y2="2.54" width="0.1524" layer="91"/> +<label x="38.1" y="2.54" size="1.27" layer="95" xref="yes"/> +<pinref part="R21" gate="G$1" pin="2"/> +<wire x1="33.02" y1="2.54" x2="38.1" y2="2.54" width="0.1524" layer="91"/> +<wire x1="33.02" y1="5.08" x2="33.02" y2="2.54" width="0.1524" layer="91"/> +<junction x="33.02" y="2.54"/> +</segment> +</net> +<net name="RTC_SCL" class="0"> +<segment> +<pinref part="U7" gate="A" pin="SCL"/> +<wire x1="15.24" y1="0" x2="27.94" y2="0" width="0.1524" layer="91"/> +<label x="38.1" y="0" size="1.27" layer="95" xref="yes"/> +<pinref part="R20" gate="G$1" pin="2"/> +<wire x1="27.94" y1="0" x2="38.1" y2="0" width="0.1524" layer="91"/> +<wire x1="27.94" y1="5.08" x2="27.94" y2="0" width="0.1524" layer="91"/> +<junction x="27.94" y="0"/> +</segment> +</net> +<net name="RTC_SDA" class="0"> +<segment> +<pinref part="U7" gate="A" pin="SDA"/> +<wire x1="15.24" y1="-2.54" x2="22.86" y2="-2.54" width="0.1524" layer="91"/> +<label x="38.1" y="-2.54" size="1.27" layer="95" xref="yes"/> +<pinref part="R19" gate="G$1" pin="2"/> +<wire x1="22.86" y1="-2.54" x2="38.1" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="22.86" y1="5.08" x2="22.86" y2="-2.54" width="0.1524" layer="91"/> +<junction x="22.86" y="-2.54"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="P+25" gate="VCC" pin="VCC"/> +<pinref part="R20" gate="G$1" pin="1"/> +<wire x1="27.94" y1="20.32" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R19" gate="G$1" pin="1"/> +<wire x1="27.94" y1="17.78" x2="27.94" y2="15.24" width="0.1524" layer="91"/> +<wire x1="22.86" y1="15.24" x2="22.86" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R21" gate="G$1" pin="1"/> +<wire x1="22.86" y1="17.78" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +<wire x1="27.94" y1="17.78" x2="33.02" y2="17.78" width="0.1524" layer="91"/> +<wire x1="33.02" y1="17.78" x2="33.02" y2="15.24" width="0.1524" layer="91"/> +<junction x="27.94" y="17.78"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>USB-UART interface</description> +<plain> +<text x="-76.2" y="66.04" size="1.778" layer="91">DS_FT232H.pdf +6.1 USB Bus Powered Configuration +copy of reference circuit</text> +<text x="-6.35" y="-49.53" size="1.27" layer="91">Place close to FT232</text> +<text x="-48.26" y="0" size="1.778" layer="91">CL 10pF</text> +<text x="-45.72" y="93.98" size="3.81" layer="91">Application access USB UART</text> +<text x="147.32" y="-111.76" size="2.54" layer="94">USB-UART interface</text> +<text x="144.78" y="-12.7" size="1.778" layer="91">If possible, line up with +corresponding header +for MGMT USB-UART and +label pins on silk screen</text> +</plain> +<instances> +<instance part="U8" gate="G$1" x="10.16" y="20.32"/> +<instance part="R23" gate="G$1" x="-25.4" y="27.94" rot="R180"> +<attribute name="TOLERANCE" x="-25.4" y="27.94" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C76" gate="G$1" x="-45.72" y="33.02" smashed="yes"> +<attribute name="NAME" x="-43.18" y="33.02" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-43.18" y="27.94" size="1.6764" layer="96"/> +</instance> +<instance part="C74" gate="G$1" x="-50.8" y="33.02" smashed="yes"> +<attribute name="NAME" x="-58.42" y="33.02" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-60.96" y="27.94" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY53" gate="GND" x="-48.26" y="17.78"/> +<instance part="SUPPLY57" gate="GND" x="12.7" y="-22.86"/> +<instance part="R22" gate="G$1" x="-35.56" y="22.86" smashed="yes" rot="R180"> +<attribute name="NAME" x="-39.37" y="18.0086" size="1.778" layer="95"/> +<attribute name="VALUE" x="-40.64" y="15.24" size="1.778" layer="96"/> +<attribute name="TOLERANCE" x="-33.02" y="15.24" size="1.778" layer="96"/> +</instance> +<instance part="R24" gate="G$1" x="50.8" y="20.32" smashed="yes" rot="R180"> +<attribute name="NAME" x="53.34" y="27.94" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="53.34" y="25.4" size="1.778" layer="96" rot="R180"/> +<attribute name="TOLERANCE" x="50.8" y="20.32" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R25" gate="G$1" x="50.8" y="17.78" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="50.8" y="17.78" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="53.34" y="15.24" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="53.34" y="12.7" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED5" gate="G$1" x="73.66" y="27.94" smashed="yes" rot="MR0"> +<attribute name="NAME" x="66.04" y="25.4" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="68.58" y="25.4" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="LED6" gate="G$1" x="78.74" y="27.94" smashed="yes" rot="MR0"> +<attribute name="NAME" x="83.82" y="25.4" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="86.36" y="25.4" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="SUPPLY56" gate="GND" x="-17.78" y="-22.86"/> +<instance part="C78" gate="G$1" x="-35.56" y="-12.7" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-33.02" y="-17.78" size="1.778" layer="96"/> +<attribute name="RATED_VOLTAGE" x="-35.56" y="-12.7" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-33.02" y="-12.7" size="1.778" layer="95"/> +<attribute name="VALUE" x="-33.02" y="-15.24" size="1.778" layer="96"/> +</instance> +<instance part="C75" gate="G$1" x="-50.8" y="-12.7" smashed="yes" rot="R180"> +<attribute name="NAME" x="-58.42" y="-12.7" size="1.778" layer="95"/> +<attribute name="VALUE" x="-58.42" y="-15.24" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="-58.42" y="-17.78" size="1.778" layer="96"/> +<attribute name="RATED_VOLTAGE" x="-50.8" y="-12.7" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SUPPLY52" gate="GND" x="-50.8" y="-22.86"/> +<instance part="SUPPLY54" gate="GND" x="-35.56" y="-22.86"/> +<instance part="P+30" gate="VCC" x="12.7" y="76.2" smashed="yes"/> +<instance part="P+33" gate="VCC" x="76.2" y="43.18" smashed="yes"/> +<instance part="C72" gate="G$1" x="-86.36" y="-66.04" smashed="yes"> +<attribute name="NAME" x="-88.9" y="-62.23" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="-88.9" y="-64.77" size="1.6764" layer="96" rot="R180"/> +<attribute name="DIELECTRIC" x="-86.36" y="-66.04" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-86.36" y="-66.04" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C73" gate="G$1" x="-78.74" y="-66.04" smashed="yes"> +<attribute name="NAME" x="-76.2" y="-63.5" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-76.2" y="-66.04" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="-78.74" y="-66.04" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="-66.04" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="SUPPLY51" gate="GND" x="-78.74" y="-78.74"/> +<instance part="C82" gate="G$1" x="45.72" y="-66.04" smashed="yes"> +<attribute name="NAME" x="43.18" y="-62.23" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="43.18" y="-64.77" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="C83" gate="G$1" x="53.34" y="-66.04" smashed="yes"> +<attribute name="NAME" x="55.88" y="-63.5" size="1.6764" layer="95"/> +<attribute name="VALUE" x="55.88" y="-66.04" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY59" gate="GND" x="53.34" y="-78.74"/> +<instance part="C79" gate="G$1" x="-27.94" y="-66.04" smashed="yes"> +<attribute name="NAME" x="-25.4" y="-68.58" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-25.4" y="-71.12" size="1.6764" layer="96"/> +</instance> +<instance part="C77" gate="G$1" x="-40.64" y="-66.04" smashed="yes"> +<attribute name="NAME" x="-43.18" y="-67.31" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="-43.18" y="-69.85" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="SUPPLY55" gate="GND" x="-27.94" y="-78.74"/> +<instance part="C81" gate="G$1" x="17.78" y="-66.04" smashed="yes"> +<attribute name="NAME" x="20.32" y="-68.58" size="1.6764" layer="95"/> +<attribute name="VALUE" x="20.32" y="-71.12" size="1.6764" layer="96"/> +</instance> +<instance part="C80" gate="G$1" x="5.08" y="-66.04" smashed="yes"> +<attribute name="NAME" x="2.54" y="-66.04" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="2.54" y="-68.58" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="SUPPLY58" gate="GND" x="17.78" y="-78.74"/> +<instance part="C84" gate="G$1" x="78.74" y="-66.04" smashed="yes"> +<attribute name="NAME" x="75.184" y="-68.199" size="1.778" layer="95" rot="MR0"/> +<attribute name="VALUE" x="70.104" y="-70.739" size="1.778" layer="96"/> +</instance> +<instance part="C85" gate="G$1" x="88.9" y="-66.04" smashed="yes"> +<attribute name="NAME" x="83.82" y="-60.96" size="1.778" layer="95"/> +<attribute name="VALUE" x="83.82" y="-63.5" size="1.778" layer="96"/> +</instance> +<instance part="C86" gate="G$1" x="99.06" y="-66.04" smashed="yes"> +<attribute name="NAME" x="101.6" y="-68.58" size="1.6764" layer="95"/> +<attribute name="VALUE" x="101.6" y="-71.12" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY60" gate="GND" x="88.9" y="-78.74"/> +<instance part="P+34" gate="VCC" x="88.9" y="-45.72" smashed="yes"/> +<instance part="FB2" gate="G$1" x="-2.54" y="-58.42"/> +<instance part="FB1" gate="G$1" x="-48.26" y="-58.42"/> +<instance part="CN1" gate="G$1" x="-162.56" y="48.26"/> +<instance part="SUPPLY50" gate="GND" x="-148.59" y="36.83"/> +<instance part="Y1" gate="G$1" x="-43.18" y="-5.08" smashed="yes"> +<attribute name="NAME" x="-44.45" y="-2.54" size="1.778" layer="95"/> +<attribute name="VALUE" x="-46.99" y="-8.89" size="1.27" layer="96"/> +<attribute name="TOLERANCE" x="-46.99" y="-11.43" size="1.27" layer="96" display="off"/> +<attribute name="MPN" x="-43.18" y="-5.08" size="1.778" layer="96" display="off"/> +<attribute name="OC_FARNELL" x="-43.18" y="-5.08" size="1.778" layer="96" display="off"/> +<attribute name="SUPPLIER" x="-43.18" y="-5.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="FRAME10" gate="G$1" x="-195.58" y="-132.08"/> +<instance part="P+32" gate="VCC" x="45.72" y="-45.72" smashed="yes"/> +<instance part="P+26" gate="VCC" x="-86.36" y="-45.72" smashed="yes"/> +<instance part="P+27" gate="VCC" x="-53.34" y="-45.72" smashed="yes"/> +<instance part="P+28" gate="VCC" x="-27.94" y="-45.72" smashed="yes"/> +<instance part="P+29" gate="VCC" x="-7.62" y="-45.72" smashed="yes"/> +<instance part="P+31" gate="VCC" x="17.78" y="-45.72" smashed="yes"/> +<instance part="IC5" gate="G$1" x="-124.46" y="48.26"/> +<instance part="SUPPLY81" gate="GND" x="-104.14" y="35.56"/> +<instance part="R86" gate="G$1" x="68.58" y="50.8" smashed="yes" rot="R180"> +<attribute name="NAME" x="71.12" y="58.42" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="71.12" y="55.88" size="1.778" layer="96" rot="R180"/> +<attribute name="TOLERANCE" x="68.58" y="50.8" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R87" gate="G$1" x="68.58" y="48.26" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="68.58" y="48.26" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="71.12" y="45.72" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="71.12" y="43.18" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="J2" gate="G$1" x="124.46" y="-17.78"/> +<instance part="P+88" gate="VCC" x="134.62" y="2.54" smashed="yes"/> +<instance part="C214" gate="G$1" x="114.3" y="-7.62" smashed="yes"> +<attribute name="NAME" x="104.14" y="-10.16" size="1.6764" layer="95"/> +<attribute name="VALUE" x="104.14" y="-12.7" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY82" gate="GND" x="114.3" y="-27.94"/> +<instance part="R91" gate="G$1" x="76.2" y="63.5" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="76.2" y="63.5" size="1.778" layer="96" rot="R270" display="off"/> +<attribute name="NAME" x="78.74" y="66.04" size="1.778" layer="95"/> +<attribute name="VALUE" x="78.74" y="63.5" size="1.778" layer="96"/> +</instance> +<instance part="P+91" gate="VCC" x="76.2" y="76.2" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="C76" gate="G$1" pin="2"/> +<pinref part="SUPPLY53" gate="GND" pin="GND"/> +<wire x1="-45.72" y1="27.94" x2="-45.72" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="22.86" x2="-45.72" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="20.32" x2="-48.26" y2="20.32" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="20.32" x2="-50.8" y2="20.32" width="0.1524" layer="91"/> +<junction x="-48.26" y="20.32"/> +<pinref part="C74" gate="G$1" pin="2"/> +<wire x1="-50.8" y1="20.32" x2="-50.8" y2="27.94" width="0.1524" layer="91"/> +<pinref part="R22" gate="G$1" pin="2"/> +<wire x1="-40.64" y1="22.86" x2="-45.72" y2="22.86" width="0.1524" layer="91"/> +<junction x="-45.72" y="22.86"/> +</segment> +<segment> +<pinref part="U8" gate="G$1" pin="GND@48"/> +<wire x1="25.4" y1="-17.78" x2="25.4" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY57" gate="GND" pin="GND"/> +<wire x1="25.4" y1="-20.32" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="AGND@4"/> +<wire x1="22.86" y1="-20.32" x2="20.32" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="20.32" y1="-20.32" x2="17.78" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="17.78" y1="-20.32" x2="15.24" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="15.24" y1="-20.32" x2="12.7" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="0" y1="-17.78" x2="0" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="0" y1="-20.32" x2="2.54" y2="-20.32" width="0.1524" layer="91"/> +<junction x="12.7" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="AGND@9"/> +<wire x1="2.54" y1="-20.32" x2="5.08" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="5.08" y1="-20.32" x2="7.62" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-20.32" x2="10.16" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="10.16" y1="-20.32" x2="12.7" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="2.54" y1="-17.78" x2="2.54" y2="-20.32" width="0.1524" layer="91"/> +<junction x="2.54" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="AGND@41"/> +<wire x1="5.08" y1="-17.78" x2="5.08" y2="-20.32" width="0.1524" layer="91"/> +<junction x="5.08" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@10"/> +<wire x1="7.62" y1="-17.78" x2="7.62" y2="-20.32" width="0.1524" layer="91"/> +<junction x="7.62" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@11"/> +<wire x1="10.16" y1="-17.78" x2="10.16" y2="-20.32" width="0.1524" layer="91"/> +<junction x="10.16" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@22"/> +<wire x1="12.7" y1="-17.78" x2="12.7" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="GND@23"/> +<wire x1="15.24" y1="-17.78" x2="15.24" y2="-20.32" width="0.1524" layer="91"/> +<junction x="15.24" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@35"/> +<wire x1="17.78" y1="-17.78" x2="17.78" y2="-20.32" width="0.1524" layer="91"/> +<junction x="17.78" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@36"/> +<wire x1="20.32" y1="-17.78" x2="20.32" y2="-20.32" width="0.1524" layer="91"/> +<junction x="20.32" y="-20.32"/> +<pinref part="U8" gate="G$1" pin="GND@47"/> +<wire x1="22.86" y1="-17.78" x2="22.86" y2="-20.32" width="0.1524" layer="91"/> +<junction x="22.86" y="-20.32"/> +</segment> +<segment> +<pinref part="U8" gate="G$1" pin="TEST"/> +<pinref part="SUPPLY56" gate="GND" pin="GND"/> +<wire x1="-17.78" y1="-10.16" x2="-17.78" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C75" gate="G$1" pin="1"/> +<wire x1="-50.8" y1="-15.24" x2="-50.8" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY52" gate="GND" pin="GND"/> +</segment> +<segment> +<wire x1="-35.56" y1="-15.24" x2="-35.56" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY54" gate="GND" pin="GND"/> +<pinref part="C78" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="SUPPLY51" gate="GND" pin="GND"/> +<pinref part="C73" gate="G$1" pin="2"/> +<wire x1="-78.74" y1="-71.12" x2="-78.74" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C72" gate="G$1" pin="2"/> +<wire x1="-78.74" y1="-73.66" x2="-78.74" y2="-76.2" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-71.12" x2="-86.36" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-73.66" x2="-78.74" y2="-73.66" width="0.1524" layer="91"/> +<junction x="-78.74" y="-73.66"/> +</segment> +<segment> +<pinref part="SUPPLY59" gate="GND" pin="GND"/> +<pinref part="C83" gate="G$1" pin="2"/> +<wire x1="53.34" y1="-71.12" x2="53.34" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C82" gate="G$1" pin="2"/> +<wire x1="53.34" y1="-73.66" x2="53.34" y2="-76.2" width="0.1524" layer="91"/> +<wire x1="45.72" y1="-71.12" x2="45.72" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="45.72" y1="-73.66" x2="53.34" y2="-73.66" width="0.1524" layer="91"/> +<junction x="53.34" y="-73.66"/> +</segment> +<segment> +<pinref part="C79" gate="G$1" pin="2"/> +<pinref part="SUPPLY55" gate="GND" pin="GND"/> +<wire x1="-27.94" y1="-71.12" x2="-27.94" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C77" gate="G$1" pin="2"/> +<wire x1="-27.94" y1="-73.66" x2="-27.94" y2="-76.2" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="-71.12" x2="-40.64" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="-73.66" x2="-27.94" y2="-73.66" width="0.1524" layer="91"/> +<junction x="-27.94" y="-73.66"/> +</segment> +<segment> +<pinref part="C81" gate="G$1" pin="2"/> +<pinref part="SUPPLY58" gate="GND" pin="GND"/> +<wire x1="17.78" y1="-76.2" x2="17.78" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C80" gate="G$1" pin="2"/> +<wire x1="17.78" y1="-73.66" x2="17.78" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="5.08" y1="-71.12" x2="5.08" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="5.08" y1="-73.66" x2="17.78" y2="-73.66" width="0.1524" layer="91"/> +<junction x="17.78" y="-73.66"/> +</segment> +<segment> +<pinref part="C84" gate="G$1" pin="2"/> +<wire x1="78.74" y1="-71.12" x2="78.74" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-73.66" x2="88.9" y2="-73.66" width="0.1524" layer="91"/> +<pinref part="C86" gate="G$1" pin="2"/> +<wire x1="88.9" y1="-73.66" x2="99.06" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-73.66" x2="99.06" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C85" gate="G$1" pin="2"/> +<wire x1="88.9" y1="-71.12" x2="88.9" y2="-73.66" width="0.1524" layer="91"/> +<junction x="88.9" y="-73.66"/> +<pinref part="SUPPLY60" gate="GND" pin="GND"/> +<wire x1="88.9" y1="-73.66" x2="88.9" y2="-76.2" width="0.1524" layer="91"/> +</segment> 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name="FT_RESET" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="!RESET"/> +<pinref part="R23" gate="G$1" pin="1"/> +<wire x1="-17.78" y1="27.94" x2="-20.32" y2="27.94" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_VCCA" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VCCA"/> +<wire x1="-17.78" y1="40.64" x2="-45.72" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="40.64" x2="-45.72" y2="35.56" width="0.1524" layer="91"/> +<pinref part="C76" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FT_VCCORE" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VCCORE"/> +<wire x1="-17.78" y1="43.18" x2="-50.8" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="43.18" x2="-50.8" y2="35.56" width="0.1524" layer="91"/> +<pinref part="C74" gate="G$1" pin="1"/> +</segment> +</net> +<net name="USB_DP" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="DP"/> +<wire x1="-17.78" y1="33.02" x2="-20.32" y2="33.02" width="0.1524" layer="91"/> +<label x="-27.94" y="33.02" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="-100.33" y1="50.8" x2="-111.76" y2="50.8" width="0.1524" layer="91"/> +<pinref part="IC5" gate="G$1" pin="OUT1"/> +<label x="-99.06" y="50.8" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="116.84" y1="-17.78" x2="111.76" y2="-17.78" width="0.1524" layer="91"/> +<label x="101.6" y="-17.78" size="1.27" layer="95"/> +</segment> +</net> +<net name="USB_DM" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="DM"/> +<wire x1="-17.78" y1="35.56" x2="-20.32" y2="35.56" width="0.1524" layer="91"/> +<label x="-27.94" y="35.56" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="-111.76" y1="45.72" x2="-100.33" y2="45.72" width="0.1524" layer="91"/> +<pinref part="IC5" gate="G$1" pin="OUT2"/> +<label x="-99.06" y="45.72" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="137.16" y1="-17.78" x2="132.08" y2="-17.78" width="0.1524" layer="91"/> +<label x="139.7" y="-17.78" size="1.27" layer="95"/> +</segment> +</net> +<net name="FT_VREGIN" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VREGIN"/> +<wire x1="-17.78" y1="50.8" x2="-50.8" y2="50.8" width="0.1524" layer="91"/> +<label x="-50.8" y="50.8" size="1.778" layer="95"/> +</segment> +<segment> +<label x="-151.13" y="53.34" size="1.27" layer="95"/> +<pinref part="CN1" gate="G$1" pin="VBUS"/> +<wire x1="-152.4" y1="53.34" x2="-139.7" y2="53.34" width="0.1524" layer="91"/> +<pinref part="IC5" gate="G$1" pin="VCC"/> +<wire x1="-139.7" y1="53.34" x2="-139.7" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-139.7" y1="48.26" x2="-137.16" y2="48.26" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C73" gate="G$1" pin="1"/> +<wire x1="-78.74" y1="-63.5" x2="-78.74" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="-58.42" x2="-86.36" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C72" gate="G$1" pin="1"/> +<wire x1="-86.36" y1="-58.42" x2="-86.36" y2="-63.5" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="-58.42" x2="-86.36" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-86.36" y="-58.42"/> +<label x="-91.44" y="-43.18" size="1.778" layer="95"/> +<pinref part="P+26" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FT_REF" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="REF"/> +<wire x1="-17.78" y1="22.86" x2="-30.48" y2="22.86" width="0.1524" layer="91"/> +<pinref part="R22" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$24" class="0"> +<segment> +<pinref part="R24" gate="G$1" pin="1"/> +<wire x1="55.88" y1="20.32" x2="73.66" y2="20.32" width="0.1524" layer="91"/> +<pinref part="LED5" gate="G$1" pin="C"/> +<wire x1="73.66" y1="20.32" x2="73.66" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$26" class="0"> +<segment> +<pinref part="R25" gate="G$1" pin="1"/> +<wire x1="55.88" y1="17.78" x2="78.74" y2="17.78" width="0.1524" layer="91"/> +<pinref part="LED6" gate="G$1" pin="C"/> +<wire x1="78.74" y1="22.86" x2="78.74" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_RXLED" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="RXLED#"/> +<pinref part="R24" gate="G$1" pin="2"/> +<wire x1="38.1" y1="20.32" x2="45.72" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_TXLED" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="TXLED#"/> +<pinref part="R25" gate="G$1" pin="2"/> +<wire x1="38.1" y1="17.78" x2="45.72" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_VCC3V3" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VCCD"/> +<wire x1="-17.78" y1="45.72" x2="-33.02" y2="45.72" width="0.1524" layer="91"/> +<label x="-50.8" y="45.72" size="1.778" layer="95"/> +<pinref part="R23" gate="G$1" pin="2"/> +<wire x1="-33.02" y1="45.72" x2="-50.8" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="27.94" x2="-33.02" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="27.94" x2="-33.02" y2="45.72" width="0.1524" layer="91"/> +<junction x="-33.02" y="45.72"/> +</segment> +<segment> +<pinref part="P+33" gate="VCC" pin="VCC"/> +<wire x1="76.2" y1="40.64" x2="76.2" y2="35.56" width="0.1524" layer="91"/> +<pinref part="LED5" gate="G$1" pin="A"/> +<wire x1="73.66" y1="30.48" x2="73.66" y2="35.56" width="0.1524" layer="91"/> +<wire x1="73.66" y1="35.56" x2="76.2" y2="35.56" width="0.1524" layer="91"/> +<pinref part="LED6" gate="G$1" pin="A"/> +<wire x1="76.2" y1="35.56" x2="78.74" y2="35.56" width="0.1524" layer="91"/> +<wire x1="78.74" y1="35.56" x2="78.74" y2="30.48" width="0.1524" layer="91"/> +<junction x="76.2" y="35.56"/> +<label x="78.74" y="40.64" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+30" gate="VCC" pin="VCC"/> +<wire x1="12.7" y1="73.66" x2="12.7" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="VCCIO@46"/> +<wire x1="15.24" y1="58.42" x2="15.24" y2="66.04" width="0.1524" layer="91"/> +<wire x1="15.24" y1="66.04" x2="12.7" y2="66.04" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="VCCIO@24"/> +<wire x1="12.7" y1="66.04" x2="12.7" y2="58.42" width="0.1524" layer="91"/> +<junction x="12.7" y="66.04"/> +<pinref part="U8" gate="G$1" pin="VCCIO@12"/> +<wire x1="10.16" y1="58.42" x2="10.16" y2="66.04" width="0.1524" layer="91"/> +<wire x1="10.16" y1="66.04" x2="12.7" y2="66.04" width="0.1524" layer="91"/> +<label x="15.24" y="73.66" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+34" gate="VCC" pin="VCC"/> +<wire x1="88.9" y1="-48.26" x2="88.9" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C84" gate="G$1" pin="1"/> +<wire x1="78.74" y1="-63.5" x2="78.74" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-58.42" x2="88.9" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C85" gate="G$1" pin="1"/> +<wire x1="88.9" y1="-58.42" x2="88.9" y2="-63.5" width="0.1524" layer="91"/> +<junction x="88.9" y="-58.42"/> +<pinref part="C86" gate="G$1" pin="1"/> +<wire x1="99.06" y1="-63.5" x2="99.06" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-58.42" x2="88.9" y2="-58.42" width="0.1524" layer="91"/> +<label x="83.82" y="-43.18" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-53.34" y1="-58.42" x2="-53.34" y2="-48.26" width="0.1524" layer="91"/> +<label x="-58.42" y="-43.18" size="1.778" layer="95"/> +<pinref part="FB1" gate="G$1" pin="P$1"/> +<wire x1="-50.8" y1="-58.42" x2="-53.34" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="P+27" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="-7.62" y1="-58.42" x2="-7.62" y2="-48.26" width="0.1524" layer="91"/> +<label x="-12.7" y="-43.18" size="1.778" layer="95"/> +<pinref part="FB2" gate="G$1" pin="P$1"/> +<wire x1="-5.08" y1="-58.42" x2="-7.62" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="P+29" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="C82" gate="G$1" pin="1"/> +<wire x1="45.72" y1="-63.5" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="C83" gate="G$1" pin="1"/> +<wire x1="45.72" y1="-58.42" x2="45.72" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="53.34" y1="-63.5" x2="53.34" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="53.34" y1="-58.42" x2="45.72" y2="-58.42" width="0.1524" layer="91"/> +<junction x="45.72" y="-58.42"/> +<label x="38.1" y="-43.18" size="1.778" layer="95"/> +<pinref part="P+32" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="N$22" class="0"> +<segment> +<pinref part="C78" gate="G$1" pin="2"/> +<wire x1="-40.64" y1="-5.08" x2="-35.56" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="-5.08" x2="-35.56" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="XCSO"/> +<wire x1="-17.78" y1="-5.08" x2="-35.56" y2="-5.08" width="0.1524" layer="91"/> +<junction x="-35.56" y="-5.08"/> +<pinref part="Y1" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$13" class="0"> +<segment> +<pinref part="C75" gate="G$1" pin="2"/> +<wire x1="-45.72" y1="-5.08" x2="-50.8" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="-5.08" x2="-50.8" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="U8" gate="G$1" pin="XCSI"/> +<wire x1="-17.78" y1="2.54" x2="-50.8" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="2.54" x2="-50.8" y2="-5.08" width="0.1524" layer="91"/> +<junction x="-50.8" y="-5.08"/> +<pinref part="Y1" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FT_TXD" class="0"> +<segment> +<wire x1="73.66" y1="50.8" x2="76.2" y2="50.8" width="0.1524" layer="91"/> +<label x="81.28" y="50.8" size="1.27" layer="95" xref="yes"/> +<pinref part="R86" gate="G$1" pin="1"/> +<pinref part="R91" gate="G$1" pin="2"/> +<wire x1="76.2" y1="50.8" x2="81.28" y2="50.8" width="0.1524" layer="91"/> +<wire x1="76.2" y1="58.42" x2="76.2" y2="50.8" width="0.1524" layer="91"/> +<junction x="76.2" y="50.8"/> +</segment> +</net> +<net name="FT_RXD" class="0"> +<segment> +<label x="81.28" y="48.26" size="1.27" layer="95" xref="yes"/> +<pinref part="R87" gate="G$1" pin="1"/> +<wire x1="73.66" y1="48.26" x2="81.28" y2="48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_VPHY" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VPHY"/> +<wire x1="5.08" y1="58.42" x2="5.08" y2="66.04" width="0.1524" layer="91"/> +<wire x1="5.08" y1="66.04" x2="-11.43" y2="66.04" width="0.1524" layer="91"/> +<label x="-11.43" y="66.04" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="C79" gate="G$1" pin="1"/> +<wire x1="-40.64" y1="-58.42" x2="-27.94" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="-58.42" x2="-27.94" y2="-63.5" width="0.1524" layer="91"/> +<pinref part="C77" gate="G$1" pin="1"/> +<wire x1="-40.64" y1="-63.5" x2="-40.64" y2="-58.42" width="0.1524" layer="91"/> +<junction x="-40.64" y="-58.42"/> +<wire x1="-27.94" y1="-58.42" x2="-27.94" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-27.94" y="-58.42"/> +<label x="-30.48" y="-43.18" size="1.778" layer="95"/> +<pinref part="FB1" gate="G$1" pin="P$2"/> +<wire x1="-40.64" y1="-58.42" x2="-45.72" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="P+28" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FT_VPLL" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="VPLL"/> +<wire x1="7.62" y1="58.42" x2="7.62" y2="71.12" width="0.1524" layer="91"/> +<wire x1="7.62" y1="71.12" x2="-11.43" y2="71.12" width="0.1524" layer="91"/> +<label x="-11.43" y="71.12" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="C81" gate="G$1" pin="1"/> +<wire x1="5.08" y1="-58.42" x2="17.78" y2="-58.42" width="0.1524" layer="91"/> +<wire x1="17.78" y1="-58.42" x2="17.78" y2="-63.5" width="0.1524" layer="91"/> +<pinref part="C80" gate="G$1" pin="1"/> +<wire x1="5.08" y1="-63.5" x2="5.08" y2="-58.42" width="0.1524" layer="91"/> +<junction x="5.08" y="-58.42"/> +<wire x1="17.78" y1="-58.42" x2="17.78" y2="-48.26" width="0.1524" layer="91"/> +<junction x="17.78" y="-58.42"/> +<label x="12.7" y="-43.18" size="1.778" layer="95"/> +<pinref part="FB2" gate="G$1" pin="P$2"/> +<wire x1="5.08" y1="-58.42" x2="0" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="P+31" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FT_RTS" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="RTS#"/> +<wire x1="38.1" y1="45.72" x2="43.18" y2="45.72" width="0.1524" layer="91"/> +<label x="43.18" y="45.72" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_CTS" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="CTS#"/> +<wire x1="38.1" y1="43.18" x2="43.18" y2="43.18" width="0.1524" layer="91"/> +<label x="43.18" y="43.18" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_DTR" class="0"> +<segment> +<pinref part="U8" gate="G$1" pin="DTR#"/> +<wire x1="38.1" y1="40.64" x2="43.18" y2="40.64" width="0.1524" layer="91"/> +<label x="43.18" y="40.64" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="N$57" class="0"> +<segment> +<pinref part="IC5" gate="G$1" pin="IN1"/> +<wire x1="-152.4" y1="50.8" x2="-137.16" y2="50.8" width="0.1524" layer="91"/> +<pinref part="CN1" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$58" class="0"> +<segment> +<wire x1="-152.4" y1="48.26" x2="-144.78" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-144.78" y1="48.26" x2="-144.78" y2="45.72" width="0.1524" layer="91"/> +<pinref part="IC5" gate="G$1" pin="IN2"/> +<wire x1="-144.78" y1="45.72" x2="-137.16" y2="45.72" width="0.1524" layer="91"/> +<pinref part="CN1" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="FT_TXD1" class="0"> +<segment> +<pinref part="R86" gate="G$1" pin="2"/> +<pinref part="U8" gate="G$1" pin="TXD"/> +<wire x1="63.5" y1="50.8" x2="38.1" y2="50.8" width="0.1524" layer="91"/> +<label x="45.72" y="50.8" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="137.16" y1="-20.32" x2="132.08" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="J2" gate="G$1" pin="6"/> +<label x="139.7" y="-20.32" size="1.27" layer="95"/> +</segment> +</net> +<net name="FT_RXD1" class="0"> +<segment> +<pinref part="R87" gate="G$1" pin="2"/> +<pinref part="U8" gate="G$1" pin="RXD"/> +<wire x1="63.5" y1="48.26" x2="38.1" y2="48.26" width="0.1524" layer="91"/> +<label x="45.72" y="48.26" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="116.84" y1="-20.32" x2="111.76" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="J2" gate="G$1" pin="5"/> +<label x="101.6" y="-20.32" size="1.27" layer="95"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="134.62" y1="-15.24" x2="134.62" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="P+88" gate="VCC" pin="VCC"/> +<label x="129.54" y="5.08" size="1.778" layer="95"/> +<pinref part="C214" gate="G$1" pin="1"/> +<wire x1="134.62" y1="-5.08" x2="134.62" y2="0" width="0.1524" layer="91"/> +<wire x1="114.3" y1="-5.08" x2="134.62" y2="-5.08" width="0.1524" layer="91"/> +<junction x="134.62" y="-5.08"/> +<pinref part="J2" gate="G$1" pin="2"/> +<wire x1="132.08" y1="-15.24" x2="134.62" y2="-15.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+91" gate="VCC" pin="VCC"/> +<pinref part="R91" gate="G$1" pin="1"/> +<wire x1="76.2" y1="73.66" x2="76.2" y2="68.58" width="0.1524" layer="91"/> +<label x="81.28" y="73.66" size="1.778" layer="95"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>MGMT USB-UART</description> +<plain> +<text x="-73.66" y="68.58" size="1.778" layer="91">DS_FT232H.pdf +6.1 USB Bus Powered Configuration +copy of reference circuit</text> +<text x="-3.81" y="-46.99" size="1.27" layer="91">Place close to FT232</text> +<text x="-45.72" y="2.54" size="1.778" layer="91">CL 10pF</text> +<text x="-45.72" y="96.52" size="3.81" layer="91">Management access USB UART</text> +<text x="149.86" y="-109.22" size="2.54" layer="94">MGMT USB-UART</text> +<text x="147.32" y="-10.16" size="1.778" layer="91">If possible, line up with +corresponding header +for USB-UART and label +pins on silk screen</text> +</plain> +<instances> +<instance part="U9" gate="G$1" x="12.7" y="22.86"/> +<instance part="R27" gate="G$1" x="-22.86" y="30.48" rot="R180"> +<attribute name="TOLERANCE" x="-22.86" y="30.48" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="C91" gate="G$1" x="-43.18" y="35.56"/> +<instance part="C89" gate="G$1" x="-48.26" y="35.56" smashed="yes"> +<attribute name="NAME" x="-59.436" y="35.941" size="1.778" layer="95"/> +<attribute name="VALUE" x="-59.436" y="30.861" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY64" gate="GND" x="-45.72" y="20.32"/> +<instance part="SUPPLY68" gate="GND" x="15.24" y="-20.32"/> +<instance part="R26" gate="G$1" x="-33.02" y="25.4" smashed="yes" rot="R180"> +<attribute name="NAME" x="-36.83" y="20.5486" size="1.778" layer="95"/> +<attribute name="VALUE" x="-38.1" y="17.78" size="1.778" layer="96"/> +<attribute name="TOLERANCE" x="-30.48" y="17.78" size="1.778" layer="96"/> +</instance> +<instance part="R28" gate="G$1" x="50.8" y="22.86" smashed="yes" rot="R180"> +<attribute name="NAME" x="53.34" y="30.48" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="53.34" y="27.94" size="1.778" layer="96" rot="R180"/> +<attribute name="TOLERANCE" x="50.8" y="22.86" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R29" gate="G$1" x="50.8" y="20.32" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="50.8" y="20.32" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="53.34" y="17.78" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="53.34" y="15.24" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED7" gate="G$1" x="76.2" y="30.48" smashed="yes" rot="MR0"> +<attribute name="NAME" x="68.58" y="27.94" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="71.12" y="27.94" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="LED8" gate="G$1" x="81.28" y="30.48" smashed="yes" rot="MR0"> +<attribute name="NAME" x="86.36" y="27.94" size="1.778" layer="95" rot="MR90"/> +<attribute name="VALUE" x="88.9" y="27.94" size="1.778" layer="96" rot="MR90"/> +</instance> +<instance part="SUPPLY67" gate="GND" x="-15.24" y="-20.32"/> +<instance part="C93" gate="G$1" x="-33.02" y="-10.16" smashed="yes" rot="R180"> +<attribute name="DIELECTRIC" x="-30.48" y="-15.24" size="1.778" layer="96"/> +<attribute name="RATED_VOLTAGE" x="-33.02" y="-10.16" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-30.48" y="-10.16" size="1.778" layer="95"/> +<attribute name="VALUE" x="-30.48" y="-12.7" size="1.778" layer="96"/> +</instance> +<instance part="C90" gate="G$1" x="-48.26" y="-10.16" smashed="yes" rot="R180"> +<attribute name="NAME" x="-55.88" y="-10.16" size="1.778" layer="95"/> +<attribute name="VALUE" x="-55.88" y="-12.7" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="-55.88" y="-15.24" size="1.778" layer="96"/> +<attribute name="RATED_VOLTAGE" x="-48.26" y="-10.16" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SUPPLY63" gate="GND" x="-48.26" y="-20.32"/> +<instance part="SUPPLY65" gate="GND" x="-33.02" y="-20.32"/> +<instance part="P+39" gate="VCC" x="15.24" y="78.74" smashed="yes"/> +<instance part="P+42" gate="VCC" x="78.74" y="45.72" smashed="yes"/> +<instance part="C87" gate="G$1" x="-83.82" y="-63.5" smashed="yes"> +<attribute name="NAME" x="-86.36" y="-59.69" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="-86.36" y="-62.23" size="1.6764" layer="96" rot="R180"/> +<attribute name="DIELECTRIC" x="-83.82" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-83.82" y="-63.5" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="C88" gate="G$1" x="-76.2" y="-63.5" smashed="yes"> +<attribute name="NAME" x="-73.66" y="-60.96" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-73.66" y="-63.5" size="1.6764" layer="96"/> +<attribute name="DIELECTRIC" x="-76.2" y="-63.5" size="1.6764" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-76.2" y="-63.5" size="1.6764" layer="96" display="off"/> +</instance> +<instance part="SUPPLY62" gate="GND" x="-76.2" y="-76.2"/> +<instance part="C97" gate="G$1" x="48.26" y="-63.5" smashed="yes"> +<attribute name="NAME" x="45.72" y="-59.69" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="45.72" y="-62.23" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="C98" gate="G$1" x="55.88" y="-63.5" smashed="yes"> +<attribute name="NAME" x="58.42" y="-60.96" size="1.6764" layer="95"/> +<attribute name="VALUE" x="58.42" y="-63.5" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY70" gate="GND" x="55.88" y="-76.2"/> +<instance part="C94" gate="G$1" x="-25.4" y="-63.5" smashed="yes"> +<attribute name="NAME" x="-22.86" y="-66.04" size="1.6764" layer="95"/> +<attribute name="VALUE" x="-22.86" y="-68.58" size="1.6764" layer="96"/> +</instance> +<instance part="C92" gate="G$1" x="-38.1" y="-63.5" smashed="yes"> +<attribute name="NAME" x="-40.64" y="-64.77" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="-40.64" y="-67.31" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="SUPPLY66" gate="GND" x="-25.4" y="-76.2"/> +<instance part="C96" gate="G$1" x="20.32" y="-63.5" smashed="yes"> +<attribute name="NAME" x="22.86" y="-66.04" size="1.6764" layer="95"/> +<attribute name="VALUE" x="22.86" y="-68.58" size="1.6764" layer="96"/> +</instance> +<instance part="C95" gate="G$1" x="7.62" y="-63.5" smashed="yes"> +<attribute name="NAME" x="5.08" y="-63.5" size="1.6764" layer="95" rot="R180"/> +<attribute name="VALUE" x="5.08" y="-66.04" size="1.6764" layer="96" rot="R180"/> +</instance> +<instance part="SUPPLY69" gate="GND" x="20.32" y="-76.2"/> +<instance part="C99" gate="G$1" x="83.82" y="-63.5" smashed="yes"> +<attribute name="NAME" x="76.2" y="-66.04" size="1.778" layer="95"/> +<attribute name="VALUE" x="73.66" y="-68.58" size="1.778" layer="96"/> +</instance> +<instance part="C100" gate="G$1" x="93.98" y="-63.5" smashed="yes"> +<attribute name="NAME" x="86.36" y="-58.42" size="1.778" layer="95"/> +<attribute name="VALUE" x="88.9" y="-60.96" size="1.778" layer="96"/> +</instance> +<instance part="C101" gate="G$1" x="104.14" y="-63.5" smashed="yes"> +<attribute name="NAME" x="106.68" y="-66.04" size="1.6764" layer="95"/> +<attribute name="VALUE" x="106.68" y="-68.58" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY71" gate="GND" x="93.98" y="-76.2"/> +<instance part="P+43" gate="VCC" x="93.98" y="-43.18" smashed="yes"/> +<instance part="FB4" gate="G$1" x="0" y="-55.88"/> +<instance part="FB3" gate="G$1" x="-45.72" y="-55.88"/> +<instance part="CN2" gate="G$1" x="-160.02" y="50.8"/> +<instance part="SUPPLY61" gate="GND" x="-147.32" y="38.1"/> +<instance part="Y2" gate="G$1" x="-40.64" y="-2.54" smashed="yes"> +<attribute name="NAME" x="-41.91" y="0" size="1.778" layer="95"/> +<attribute name="VALUE" x="-44.45" y="-6.35" size="1.27" layer="96"/> +<attribute name="TOLERANCE" x="-44.45" y="-8.89" size="1.27" layer="96" display="off"/> +<attribute name="MPN" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="OC_FARNELL" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="SUPPLIER" x="-40.64" y="-2.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="FRAME11" gate="G$1" x="-193.04" y="-129.54"/> +<instance part="P+41" gate="VCC" x="48.26" y="-43.18" smashed="yes"/> +<instance part="P+35" gate="VCC" x="-83.82" y="-43.18" smashed="yes"/> +<instance part="P+36" gate="VCC" x="-50.8" y="-43.18" smashed="yes"/> +<instance part="P+37" gate="VCC" x="-25.4" y="-43.18" smashed="yes"/> +<instance part="P+38" gate="VCC" x="-5.08" y="-43.18" smashed="yes"/> +<instance part="P+40" gate="VCC" x="20.32" y="-43.18" smashed="yes"/> +<instance part="IC6" gate="G$1" x="-121.92" y="50.8"/> +<instance part="SUPPLY224" gate="GND" x="-101.6" y="38.1"/> +<instance part="R88" gate="G$1" x="71.12" y="53.34" smashed="yes" rot="R180"> +<attribute name="NAME" x="73.66" y="60.96" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="73.66" y="58.42" size="1.778" layer="96" rot="R180"/> +<attribute name="TOLERANCE" x="71.12" y="53.34" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="R89" gate="G$1" x="71.12" y="50.8" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="71.12" y="50.8" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="73.66" y="48.26" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="73.66" y="45.72" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="J3" gate="G$1" x="127" y="-15.24"/> +<instance part="P+90" gate="VCC" x="137.16" y="5.08" smashed="yes"/> +<instance part="C215" gate="G$1" x="116.84" y="-5.08" smashed="yes"> +<attribute name="NAME" x="106.68" y="-7.62" size="1.6764" layer="95"/> +<attribute name="VALUE" x="106.68" y="-10.16" size="1.6764" layer="96"/> +</instance> +<instance part="SUPPLY225" gate="GND" x="116.84" y="-25.4"/> +<instance part="R90" gate="G$1" x="78.74" y="66.04" smashed="yes" rot="R270"> +<attribute name="TOLERANCE" x="78.74" y="66.04" size="1.778" layer="96" rot="R270" display="off"/> +<attribute name="NAME" x="81.28" y="68.58" size="1.778" layer="95"/> +<attribute name="VALUE" x="81.28" y="66.04" size="1.778" layer="96"/> +</instance> +<instance part="P+89" gate="VCC" x="78.74" y="78.74" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="C91" gate="G$1" pin="2"/> +<pinref part="SUPPLY64" gate="GND" pin="GND"/> +<wire x1="-43.18" y1="30.48" x2="-43.18" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="25.4" x2="-43.18" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="22.86" x2="-45.72" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="22.86" x2="-48.26" y2="22.86" width="0.1524" layer="91"/> +<junction x="-45.72" y="22.86"/> +<pinref part="C89" gate="G$1" pin="2"/> +<wire x1="-48.26" y1="22.86" x2="-48.26" y2="30.48" width="0.1524" layer="91"/> +<pinref part="R26" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="25.4" x2="-43.18" y2="25.4" width="0.1524" layer="91"/> +<junction x="-43.18" y="25.4"/> +</segment> +<segment> +<pinref part="U9" gate="G$1" pin="GND@48"/> +<wire x1="27.94" y1="-15.24" x2="27.94" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="SUPPLY68" gate="GND" pin="GND"/> +<wire x1="27.94" y1="-17.78" x2="25.4" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="AGND@4"/> +<wire x1="25.4" y1="-17.78" x2="22.86" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="22.86" y1="-17.78" x2="20.32" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="20.32" y1="-17.78" x2="17.78" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="17.78" y1="-17.78" x2="15.24" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="2.54" y1="-15.24" x2="2.54" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="2.54" y1="-17.78" x2="5.08" y2="-17.78" width="0.1524" layer="91"/> +<junction x="15.24" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="AGND@9"/> +<wire x1="5.08" y1="-17.78" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-17.78" x2="10.16" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="10.16" y1="-17.78" x2="12.7" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="12.7" y1="-17.78" x2="15.24" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="5.08" y1="-15.24" x2="5.08" y2="-17.78" width="0.1524" layer="91"/> +<junction x="5.08" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="AGND@41"/> +<wire x1="7.62" y1="-15.24" x2="7.62" y2="-17.78" width="0.1524" layer="91"/> +<junction x="7.62" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@10"/> +<wire x1="10.16" y1="-15.24" x2="10.16" y2="-17.78" width="0.1524" layer="91"/> +<junction x="10.16" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@11"/> +<wire x1="12.7" y1="-15.24" x2="12.7" y2="-17.78" width="0.1524" layer="91"/> +<junction x="12.7" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@22"/> +<wire x1="15.24" y1="-15.24" x2="15.24" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="GND@23"/> +<wire x1="17.78" y1="-15.24" x2="17.78" y2="-17.78" width="0.1524" layer="91"/> +<junction x="17.78" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@35"/> +<wire x1="20.32" y1="-15.24" x2="20.32" y2="-17.78" width="0.1524" layer="91"/> +<junction x="20.32" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@36"/> +<wire x1="22.86" y1="-15.24" x2="22.86" y2="-17.78" width="0.1524" layer="91"/> +<junction x="22.86" y="-17.78"/> +<pinref part="U9" gate="G$1" pin="GND@47"/> +<wire x1="25.4" y1="-15.24" x2="25.4" y2="-17.78" width="0.1524" layer="91"/> +<junction x="25.4" y="-17.78"/> +</segment> +<segment> +<pinref part="U9" gate="G$1" pin="TEST"/> +<pinref part="SUPPLY67" gate="GND" pin="GND"/> +<wire x1="-15.24" y1="-7.62" x2="-15.24" y2="-17.78" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C90" gate="G$1" pin="1"/> +<wire x1="-48.26" y1="-12.7" x2="-48.26" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="SUPPLY63" gate="GND" pin="GND"/> +</segment> +<segment> +<wire x1="-33.02" y1="-12.7" x2="-33.02" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="SUPPLY65" gate="GND" pin="GND"/> +<pinref part="C93" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="SUPPLY62" gate="GND" pin="GND"/> +<pinref part="C88" gate="G$1" pin="2"/> +<wire x1="-76.2" y1="-68.58" x2="-76.2" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C87" gate="G$1" pin="2"/> +<wire x1="-76.2" y1="-71.12" x2="-76.2" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-68.58" x2="-83.82" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-71.12" x2="-76.2" y2="-71.12" width="0.1524" layer="91"/> +<junction x="-76.2" y="-71.12"/> +</segment> +<segment> +<pinref part="SUPPLY70" gate="GND" pin="GND"/> +<pinref part="C98" gate="G$1" pin="2"/> +<wire x1="55.88" y1="-68.58" x2="55.88" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C97" gate="G$1" pin="2"/> +<wire x1="55.88" y1="-71.12" x2="55.88" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-68.58" x2="48.26" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="48.26" y1="-71.12" x2="55.88" y2="-71.12" width="0.1524" layer="91"/> +<junction x="55.88" y="-71.12"/> +</segment> +<segment> +<pinref part="C94" gate="G$1" pin="2"/> +<pinref part="SUPPLY66" gate="GND" pin="GND"/> +<wire x1="-25.4" y1="-68.58" x2="-25.4" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C92" gate="G$1" pin="2"/> +<wire x1="-25.4" y1="-71.12" x2="-25.4" y2="-73.66" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="-68.58" x2="-38.1" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="-71.12" x2="-25.4" y2="-71.12" width="0.1524" layer="91"/> +<junction x="-25.4" y="-71.12"/> +</segment> +<segment> +<pinref part="C96" gate="G$1" pin="2"/> +<pinref part="SUPPLY69" gate="GND" pin="GND"/> +<wire x1="20.32" y1="-73.66" x2="20.32" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C95" gate="G$1" pin="2"/> +<wire x1="20.32" y1="-71.12" x2="20.32" y2="-68.58" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-68.58" x2="7.62" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="7.62" y1="-71.12" x2="20.32" y2="-71.12" width="0.1524" layer="91"/> +<junction x="20.32" y="-71.12"/> +</segment> +<segment> +<pinref part="C99" gate="G$1" pin="2"/> +<wire x1="83.82" y1="-68.58" x2="83.82" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-71.12" x2="93.98" y2="-71.12" width="0.1524" layer="91"/> +<pinref part="C101" gate="G$1" pin="2"/> +<wire x1="93.98" y1="-71.12" x2="104.14" y2="-71.12" width="0.1524" layer="91"/> +<wire x1="104.14" y1="-71.12" x2="104.14" y2="-68.58" width="0.1524" layer="91"/> +<pinref part="C100" gate="G$1" pin="2"/> +<wire x1="93.98" y1="-68.58" x2="93.98" y2="-71.12" width="0.1524" layer="91"/> +<junction x="93.98" y="-71.12"/> +<pinref part="SUPPLY71" gate="GND" pin="GND"/> +<wire x1="93.98" y1="-71.12" x2="93.98" y2="-73.66" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="-149.86" y1="45.72" x2="-147.32" y2="45.72" width="0.1524" layer="91"/> +<pinref part="CN2" gate="G$1" pin="GND"/> +<pinref part="SUPPLY61" gate="GND" pin="GND"/> +<wire x1="-147.32" y1="45.72" x2="-147.32" y2="40.64" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC6" gate="G$1" pin="GND"/> +<wire x1="-109.22" y1="50.8" x2="-101.6" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-101.6" y1="50.8" x2="-101.6" y2="40.64" width="0.1524" layer="91"/> +<pinref part="SUPPLY224" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="C215" gate="G$1" pin="2"/> +<pinref part="SUPPLY225" gate="GND" pin="GND"/> +<wire x1="116.84" y1="-10.16" x2="116.84" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="J3" gate="G$1" pin="1"/> +<wire x1="116.84" y1="-12.7" x2="116.84" y2="-22.86" width="0.1524" layer="91"/> +<wire x1="119.38" y1="-12.7" x2="116.84" y2="-12.7" width="0.1524" layer="91"/> +<junction x="116.84" y="-12.7"/> +</segment> +</net> +<net name="FT_RESET1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="!RESET"/> +<pinref part="R27" gate="G$1" pin="1"/> +<wire x1="-15.24" y1="30.48" x2="-17.78" y2="30.48" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_VCCA1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VCCA"/> +<wire x1="-15.24" y1="43.18" x2="-43.18" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="43.18" x2="-43.18" y2="38.1" width="0.1524" layer="91"/> +<pinref part="C91" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FT_VCCORE1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VCCORE"/> +<wire x1="-15.24" y1="45.72" x2="-48.26" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="45.72" x2="-48.26" y2="38.1" width="0.1524" layer="91"/> +<pinref part="C89" gate="G$1" pin="1"/> +</segment> +</net> +<net name="USB_MGMT_DM" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="DM"/> +<wire x1="-15.24" y1="38.1" x2="-17.78" y2="38.1" width="0.1524" layer="91"/> +<label x="-30.48" y="38.1" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="-109.22" y1="48.26" x2="-97.79" y2="48.26" width="0.1524" layer="91"/> +<pinref part="IC6" gate="G$1" pin="OUT2"/> +<label x="-96.52" y="48.26" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="134.62" y1="-15.24" x2="139.7" y2="-15.24" width="0.1524" layer="91"/> +<label x="142.24" y="-15.24" size="1.27" layer="95"/> +<pinref part="J3" gate="G$1" pin="4"/> +</segment> +</net> +<net name="FT_MGMT_VREGIN" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VREGIN"/> +<wire x1="-15.24" y1="53.34" x2="-48.26" y2="53.34" width="0.1524" layer="91"/> +<label x="-48.26" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="C88" gate="G$1" pin="1"/> +<wire x1="-76.2" y1="-60.96" x2="-76.2" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="-55.88" x2="-83.82" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C87" gate="G$1" pin="1"/> +<wire x1="-83.82" y1="-55.88" x2="-83.82" y2="-60.96" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-55.88" x2="-83.82" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-83.82" y="-55.88"/> +<label x="-88.9" y="-40.64" size="1.778" layer="95"/> +<pinref part="P+35" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="-149.86" y1="55.88" x2="-137.16" y2="55.88" width="0.1524" layer="91"/> +<pinref part="IC6" gate="G$1" pin="VCC"/> +<wire x1="-137.16" y1="55.88" x2="-137.16" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-137.16" y1="50.8" x2="-134.62" y2="50.8" width="0.1524" layer="91"/> +<pinref part="CN2" gate="G$1" pin="VBUS"/> +</segment> +</net> +<net name="FT_REF1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="REF"/> +<wire x1="-15.24" y1="25.4" x2="-27.94" y2="25.4" width="0.1524" layer="91"/> +<pinref part="R26" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$6" class="0"> +<segment> +<pinref part="R28" gate="G$1" pin="1"/> +<wire x1="55.88" y1="22.86" x2="76.2" y2="22.86" width="0.1524" layer="91"/> +<pinref part="LED7" gate="G$1" pin="C"/> +<wire x1="76.2" y1="22.86" x2="76.2" y2="25.4" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$7" class="0"> +<segment> +<pinref part="R29" gate="G$1" pin="1"/> +<wire x1="55.88" y1="20.32" x2="81.28" y2="20.32" width="0.1524" layer="91"/> +<pinref part="LED8" gate="G$1" pin="C"/> +<wire x1="81.28" y1="25.4" x2="81.28" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_RXLED1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="RXLED#"/> +<pinref part="R28" gate="G$1" pin="2"/> +<wire x1="40.64" y1="22.86" x2="45.72" y2="22.86" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_TXLED1" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="TXLED#"/> +<pinref part="R29" gate="G$1" pin="2"/> +<wire x1="40.64" y1="20.32" x2="45.72" y2="20.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_MGMT_VCC3V3" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VCCD"/> +<wire x1="-15.24" y1="48.26" x2="-33.02" y2="48.26" width="0.1524" layer="91"/> +<label x="-48.26" y="48.26" size="1.778" layer="95"/> +<pinref part="R27" gate="G$1" pin="2"/> +<wire x1="-33.02" y1="48.26" x2="-48.26" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="30.48" x2="-33.02" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="30.48" x2="-33.02" y2="48.26" width="0.1524" layer="91"/> +<junction x="-33.02" y="48.26"/> +</segment> +<segment> +<pinref part="P+42" gate="VCC" pin="VCC"/> +<wire x1="78.74" y1="43.18" x2="78.74" y2="38.1" width="0.1524" layer="91"/> +<pinref part="LED7" gate="G$1" pin="A"/> +<wire x1="76.2" y1="33.02" x2="76.2" y2="38.1" width="0.1524" layer="91"/> +<wire x1="76.2" y1="38.1" x2="78.74" y2="38.1" width="0.1524" layer="91"/> +<pinref part="LED8" gate="G$1" pin="A"/> +<wire x1="78.74" y1="38.1" x2="81.28" y2="38.1" width="0.1524" layer="91"/> +<wire x1="81.28" y1="38.1" x2="81.28" y2="33.02" width="0.1524" layer="91"/> +<junction x="78.74" y="38.1"/> +<label x="81.28" y="43.18" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+39" gate="VCC" pin="VCC"/> +<wire x1="15.24" y1="76.2" x2="15.24" y2="68.58" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="VCCIO@46"/> +<wire x1="17.78" y1="60.96" x2="17.78" y2="68.58" width="0.1524" layer="91"/> +<wire x1="17.78" y1="68.58" x2="15.24" y2="68.58" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="VCCIO@24"/> +<wire x1="15.24" y1="68.58" x2="15.24" y2="60.96" width="0.1524" layer="91"/> +<junction x="15.24" y="68.58"/> +<pinref part="U9" gate="G$1" pin="VCCIO@12"/> +<wire x1="12.7" y1="60.96" x2="12.7" y2="68.58" width="0.1524" layer="91"/> +<wire x1="12.7" y1="68.58" x2="15.24" y2="68.58" width="0.1524" layer="91"/> +<label x="17.78" y="76.2" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+43" gate="VCC" pin="VCC"/> +<wire x1="93.98" y1="-45.72" x2="93.98" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C99" gate="G$1" pin="1"/> +<wire x1="83.82" y1="-60.96" x2="83.82" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-55.88" x2="93.98" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C100" gate="G$1" pin="1"/> +<wire x1="93.98" y1="-55.88" x2="93.98" y2="-60.96" width="0.1524" layer="91"/> +<junction x="93.98" y="-55.88"/> +<pinref part="C101" gate="G$1" pin="1"/> +<wire x1="104.14" y1="-60.96" x2="104.14" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="104.14" y1="-55.88" x2="93.98" y2="-55.88" width="0.1524" layer="91"/> +<label x="91.44" y="-40.64" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-50.8" y1="-55.88" x2="-50.8" y2="-45.72" width="0.1524" layer="91"/> +<label x="-55.88" y="-40.64" size="1.778" layer="95"/> +<pinref part="FB3" gate="G$1" pin="P$1"/> +<wire x1="-48.26" y1="-55.88" x2="-50.8" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="P+36" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="-5.08" y1="-55.88" x2="-5.08" y2="-45.72" width="0.1524" layer="91"/> +<label x="-10.16" y="-40.64" size="1.778" layer="95"/> +<pinref part="FB4" gate="G$1" pin="P$1"/> +<wire x1="-2.54" y1="-55.88" x2="-5.08" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="P+38" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="C97" gate="G$1" pin="1"/> +<wire x1="48.26" y1="-60.96" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C98" gate="G$1" pin="1"/> +<wire x1="48.26" y1="-55.88" x2="48.26" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="55.88" y1="-60.96" x2="55.88" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="55.88" y1="-55.88" x2="48.26" y2="-55.88" width="0.1524" layer="91"/> +<junction x="48.26" y="-55.88"/> +<label x="40.64" y="-40.64" size="1.778" layer="95"/> +<pinref part="P+41" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="N$8" class="0"> +<segment> +<pinref part="C93" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="-2.54" x2="-33.02" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="-2.54" x2="-33.02" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="XCSO"/> +<wire x1="-15.24" y1="-2.54" x2="-33.02" y2="-2.54" width="0.1524" layer="91"/> +<junction x="-33.02" y="-2.54"/> +<pinref part="Y2" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$9" class="0"> +<segment> +<pinref part="C90" gate="G$1" pin="2"/> +<wire x1="-43.18" y1="-2.54" x2="-48.26" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="-2.54" x2="-48.26" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="U9" gate="G$1" pin="XCSI"/> +<wire x1="-15.24" y1="5.08" x2="-48.26" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-48.26" y1="5.08" x2="-48.26" y2="-2.54" width="0.1524" layer="91"/> +<junction x="-48.26" y="-2.54"/> +<pinref part="Y2" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FT_MGMT_VPLL" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VPLL"/> +<wire x1="10.16" y1="60.96" x2="10.16" y2="73.66" width="0.1524" layer="91"/> +<wire x1="10.16" y1="73.66" x2="-8.89" y2="73.66" width="0.1524" layer="91"/> +<label x="-8.89" y="73.66" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="C96" gate="G$1" pin="1"/> +<wire x1="7.62" y1="-55.88" x2="20.32" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="20.32" y1="-55.88" x2="20.32" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C95" gate="G$1" pin="1"/> +<wire x1="7.62" y1="-60.96" x2="7.62" y2="-55.88" width="0.1524" layer="91"/> +<junction x="7.62" y="-55.88"/> +<wire x1="20.32" y1="-55.88" x2="20.32" y2="-45.72" width="0.1524" layer="91"/> +<junction x="20.32" y="-55.88"/> +<label x="15.24" y="-40.64" size="1.778" layer="95"/> +<pinref part="FB4" gate="G$1" pin="P$2"/> +<wire x1="7.62" y1="-55.88" x2="2.54" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="P+40" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="USB_MGMT_DP" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="DP"/> +<wire x1="-15.24" y1="35.56" x2="-17.78" y2="35.56" width="0.1524" layer="91"/> +<label x="-30.48" y="35.56" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="-97.79" y1="53.34" x2="-109.22" y2="53.34" width="0.1524" layer="91"/> +<pinref part="IC6" gate="G$1" pin="OUT1"/> +<label x="-96.52" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="114.3" y1="-15.24" x2="119.38" y2="-15.24" width="0.1524" layer="91"/> +<label x="99.06" y="-15.24" size="1.27" layer="95"/> +<pinref part="J3" gate="G$1" pin="3"/> +</segment> +</net> +<net name="FT_MGMT_VPHY" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="VPHY"/> +<wire x1="7.62" y1="60.96" x2="7.62" y2="68.58" width="0.1524" layer="91"/> +<wire x1="7.62" y1="68.58" x2="-8.89" y2="68.58" width="0.1524" layer="91"/> +<label x="-8.89" y="68.58" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="C94" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-55.88" x2="-25.4" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-60.96" width="0.1524" layer="91"/> +<pinref part="C92" gate="G$1" pin="1"/> +<wire x1="-38.1" y1="-60.96" x2="-38.1" y2="-55.88" width="0.1524" layer="91"/> +<junction x="-38.1" y="-55.88"/> +<wire x1="-25.4" y1="-55.88" x2="-25.4" y2="-45.72" width="0.1524" layer="91"/> +<junction x="-25.4" y="-55.88"/> +<label x="-27.94" y="-35.56" size="1.778" layer="95"/> +<pinref part="FB3" gate="G$1" pin="P$2"/> +<wire x1="-38.1" y1="-55.88" x2="-43.18" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="P+37" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FT_MGMT_TXD" class="0"> +<segment> +<wire x1="76.2" y1="53.34" x2="78.74" y2="53.34" width="0.1524" layer="91"/> +<label x="83.82" y="53.34" size="1.27" layer="95" xref="yes"/> +<pinref part="R88" gate="G$1" pin="1"/> +<pinref part="R90" gate="G$1" pin="2"/> +<wire x1="78.74" y1="53.34" x2="83.82" y2="53.34" width="0.1524" layer="91"/> +<wire x1="78.74" y1="60.96" x2="78.74" y2="53.34" width="0.1524" layer="91"/> +<junction x="78.74" y="53.34"/> +</segment> +</net> +<net name="FT_MGMT_RXD" class="0"> +<segment> +<label x="83.82" y="50.8" size="1.27" layer="95" xref="yes"/> +<pinref part="R89" gate="G$1" pin="1"/> +<wire x1="76.2" y1="50.8" x2="83.82" y2="50.8" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FT_MGMT_RTS" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="RTS#"/> +<wire x1="40.64" y1="48.26" x2="45.72" y2="48.26" width="0.1524" layer="91"/> +<label x="45.72" y="48.26" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_CTS" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="CTS#"/> +<wire x1="40.64" y1="45.72" x2="45.72" y2="45.72" width="0.1524" layer="91"/> +<label x="45.72" y="45.72" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FT_MGMT_DTR" class="0"> +<segment> +<pinref part="U9" gate="G$1" pin="DTR#"/> +<wire x1="40.64" y1="43.18" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<label x="45.72" y="43.18" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="N$59" class="0"> +<segment> +<pinref part="IC6" gate="G$1" pin="IN1"/> +<wire x1="-149.86" y1="53.34" x2="-134.62" y2="53.34" width="0.1524" layer="91"/> +<pinref part="CN2" gate="G$1" pin="D+"/> +</segment> +</net> +<net name="N$60" class="0"> +<segment> +<wire x1="-149.86" y1="50.8" x2="-142.24" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="50.8" x2="-142.24" y2="48.26" width="0.1524" layer="91"/> +<pinref part="IC6" gate="G$1" pin="IN2"/> +<wire x1="-142.24" y1="48.26" x2="-134.62" y2="48.26" width="0.1524" layer="91"/> +<pinref part="CN2" gate="G$1" pin="D-"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="137.16" y1="-12.7" x2="137.16" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="P+90" gate="VCC" pin="VCC"/> +<label x="132.08" y="10.16" size="1.778" layer="95"/> +<pinref part="C215" gate="G$1" pin="1"/> +<wire x1="137.16" y1="-2.54" x2="137.16" y2="2.54" width="0.1524" layer="91"/> +<wire x1="116.84" y1="-2.54" x2="137.16" y2="-2.54" width="0.1524" layer="91"/> +<junction x="137.16" y="-2.54"/> +<pinref part="J3" gate="G$1" pin="2"/> +<wire x1="137.16" y1="-12.7" x2="134.62" y2="-12.7" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="P+89" gate="VCC" pin="VCC"/> +<pinref part="R90" gate="G$1" pin="1"/> +<wire x1="78.74" y1="76.2" x2="78.74" y2="71.12" width="0.1524" layer="91"/> +<label x="83.82" y="76.2" size="1.778" layer="95"/> +</segment> +</net> +<net name="FT_MGMT_TXD1" class="0"> +<segment> +<pinref part="R88" gate="G$1" pin="2"/> +<wire x1="66.04" y1="53.34" x2="40.64" y2="53.34" width="0.1524" layer="91"/> +<label x="48.26" y="53.34" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="139.7" y1="-17.78" x2="134.62" y2="-17.78" width="0.1524" layer="91"/> +<label x="142.24" y="-17.78" size="1.27" layer="95"/> +<pinref part="J3" gate="G$1" pin="6"/> +</segment> +</net> +<net name="FT_MGMT_RXD1" class="0"> +<segment> +<pinref part="R89" gate="G$1" pin="2"/> +<wire x1="66.04" y1="50.8" x2="40.64" y2="50.8" width="0.1524" layer="91"/> +<label x="48.26" y="50.8" size="1.27" layer="95"/> +</segment> +<segment> +<wire x1="119.38" y1="-17.78" x2="114.3" y2="-17.78" width="0.1524" layer="91"/> +<label x="99.06" y="-17.78" size="1.27" layer="95"/> +<pinref part="J3" gate="G$1" pin="5"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>AVR Tamper circuit</description> +<plain> +<text x="-81.28" y="63.5" size="3.81" layer="91">AVR Tiny Tamper Detect MCU</text> +<text x="121.92" y="43.18" size="2.54" layer="91">Panic button</text> +<text x="137.16" y="-12.7" size="2.54" layer="91">Expansion GPIO</text> +<text x="121.92" y="93.98" size="1.778" layer="91">Connector for external 3V3 battery. + +Place a jumper between pins 1-2 +to "emulate" having a battery present.</text> +<text x="-93.98" y="-35.56" size="1.778" layer="91">AVR_GPIO* AVR_LED* and AVR_PANIC can be swapped.</text> +<text x="152.4" y="-109.22" size="2.54" layer="94">AVR Tamper circuit</text> +</plain> +<instances> +<instance part="U10" gate="A" x="-43.18" y="12.7"/> +<instance part="FRAME12" gate="G$1" x="-190.5" y="-129.54"/> +<instance part="P+44" gate="VCC" x="-109.22" y="53.34" smashed="yes"/> +<instance part="SUPPLY73" gate="GND" x="-109.22" y="-30.48"/> +<instance part="JP3" gate="G$1" x="66.04" y="-12.7" smashed="yes"> +<attribute name="NAME" x="61.722" y="-6.858" size="1.778" layer="95"/> +<attribute name="VALUE" x="41.656" y="-22.86" size="1.778" layer="96"/> +</instance> +<instance part="P+46" gate="VCC" x="78.74" y="0" smashed="yes"/> +<instance part="R30" gate="G$1" x="45.72" y="25.4" rot="R90"/> +<instance part="P+45" gate="VCC" x="45.72" y="40.64" smashed="yes"/> +<instance part="SUPPLY74" gate="GND" x="78.74" y="-30.48"/> +<instance part="C102" gate="G$1" x="-149.86" y="30.48" smashed="yes"> +<attribute name="NAME" x="-157.48" y="30.48" size="1.27" layer="95"/> +<attribute name="VALUE" x="-157.48" y="27.94" size="1.27" layer="96"/> +<attribute name="DIELECTRIC" x="-149.86" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-149.86" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C104" gate="G$1" x="-134.62" y="30.48" smashed="yes"> +<attribute name="NAME" x="-132.08" y="30.48" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="-132.08" y="27.94" size="1.27" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="-134.62" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-134.62" y="30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C103" gate="G$1" x="-142.24" y="30.48" smashed="yes"> +<attribute name="DIELECTRIC" x="-142.24" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-142.24" y="30.48" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="-142.24" y="33.02" size="1.27" layer="95"/> +<attribute name="VALUE" x="-142.24" y="30.48" size="1.27" layer="96"/> +</instance> +<instance part="SUPPLY72" gate="GND" x="-142.24" y="17.78"/> +<instance part="LED11" gate="G$1" x="157.48" y="-78.74" smashed="yes" rot="R90"> +<attribute name="NAME" x="177.292" y="-77.724" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="189.992" y="-78.105" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED9" gate="G$1" x="152.4" y="-81.28" smashed="yes" rot="R90"> +<attribute name="NAME" x="177.292" y="-80.264" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="189.992" y="-80.645" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED12" gate="G$1" x="157.48" y="-83.82" smashed="yes" rot="R90"> +<attribute name="NAME" x="177.292" y="-82.804" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="189.992" y="-83.185" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="LED10" gate="G$1" x="152.4" y="-86.36" smashed="yes" rot="R90"> +<attribute name="NAME" x="177.292" y="-85.344" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="189.992" y="-85.725" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="SUPPLY79" gate="GND" x="165.1" y="-93.98"/> +<instance part="R31" gate="A" x="137.16" y="-86.36" rot="R180"/> +<instance part="JP5" gate="G$1" x="165.1" y="-40.64" rot="R180"/> +<instance part="SUPPLY77" gate="GND" x="149.86" y="-50.8"/> +<instance part="P+47" gate="VCC" x="127" y="-17.78"/> +<instance part="S2" gate="A" x="144.78" y="22.86"/> +<instance part="SUPPLY78" gate="GND" x="162.56" y="5.08"/> +<instance part="JP4" gate="J$1" x="162.56" y="78.74" rot="R180"/> +<instance part="SUPPLY76" gate="GND" x="149.86" y="68.58"/> +<instance part="P+48" gate="VCC" x="142.24" y="88.9" smashed="yes"/> +<instance part="P+49" gate="VCC" x="149.86" y="88.9" smashed="yes"/> +<instance part="C105" gate="G$1" x="127" y="-33.02" smashed="yes"> +<attribute name="NAME" x="121.92" y="-33.02" size="1.27" layer="95" font="vector" rot="R180"/> +<attribute name="VALUE" x="121.92" y="-35.56" size="1.27" layer="96" font="vector" rot="R180"/> +<attribute name="DIELECTRIC" x="127" y="-33.02" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="127" y="-33.02" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY75" gate="GND" x="127" y="-50.8"/> +<instance part="R82" gate="G$1" x="127" y="22.86" smashed="yes" rot="R90"> +<attribute name="NAME" x="123.19" y="23.9014" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="123.19" y="21.082" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="P+86" gate="VCC" x="127" y="33.02" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U10" gate="A" pin="GND_2"/> +<pinref part="SUPPLY73" gate="GND" pin="GND"/> +<wire x1="-99.06" y1="-15.24" x2="-109.22" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-109.22" y1="-15.24" x2="-109.22" y2="-17.78" width="0.1524" layer="91"/> +<pinref part="U10" gate="A" pin="GND"/> +<wire x1="-109.22" y1="-17.78" x2="-109.22" y2="-27.94" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="-17.78" x2="-109.22" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-109.22" y="-17.78"/> +</segment> +<segment> +<pinref part="JP3" gate="G$1" pin="6"/> +<pinref part="SUPPLY74" gate="GND" pin="GND"/> +<wire x1="76.2" y1="-15.24" x2="78.74" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-15.24" x2="78.74" y2="-27.94" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C102" gate="G$1" pin="2"/> +<wire x1="-149.86" y1="25.4" x2="-149.86" y2="22.86" width="0.1524" layer="91"/> +<pinref part="SUPPLY72" gate="GND" pin="GND"/> +<wire x1="-149.86" y1="22.86" x2="-142.24" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="22.86" x2="-142.24" y2="20.32" width="0.1524" layer="91"/> +<pinref part="C104" gate="G$1" pin="2"/> +<wire x1="-134.62" y1="25.4" x2="-134.62" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="22.86" x2="-142.24" y2="22.86" width="0.1524" layer="91"/> +<junction x="-142.24" y="22.86"/> +<pinref part="C103" gate="G$1" pin="2"/> +<wire x1="-142.24" y1="25.4" x2="-142.24" y2="22.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="LED11" gate="G$1" pin="C"/> +<wire x1="162.56" y1="-78.74" x2="165.1" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="LED9" gate="G$1" pin="C"/> +<wire x1="165.1" y1="-86.36" x2="165.1" y2="-83.82" width="0.1524" layer="91"/> +<wire x1="165.1" y1="-83.82" x2="165.1" y2="-81.28" width="0.1524" layer="91"/> +<wire x1="165.1" y1="-81.28" x2="165.1" y2="-78.74" width="0.1524" layer="91"/> +<wire x1="157.48" y1="-81.28" x2="165.1" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="LED10" gate="G$1" pin="C"/> +<wire x1="157.48" y1="-86.36" x2="165.1" y2="-86.36" width="0.1524" layer="91"/> +<pinref part="LED12" gate="G$1" pin="C"/> +<wire x1="162.56" y1="-83.82" x2="165.1" y2="-83.82" width="0.1524" layer="91"/> +<junction x="165.1" y="-83.82"/> +<junction x="165.1" y="-81.28"/> +<pinref part="SUPPLY79" gate="GND" pin="GND"/> +<wire x1="165.1" y1="-91.44" x2="165.1" y2="-86.36" width="0.1524" layer="91"/> +<junction x="165.1" y="-86.36"/> +</segment> +<segment> +<pinref part="JP5" gate="G$1" pin="10"/> +<wire x1="154.94" y1="-45.72" x2="149.86" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="149.86" y1="-45.72" x2="149.86" y2="-48.26" width="0.1524" layer="91"/> +<pinref part="SUPPLY77" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="S2" gate="A" pin="G1"/> +<pinref part="SUPPLY78" gate="GND" pin="GND"/> +<wire x1="160.02" y1="25.4" x2="162.56" y2="25.4" width="0.1524" layer="91"/> +<wire x1="162.56" y1="25.4" x2="162.56" y2="20.32" width="0.1524" layer="91"/> +<pinref part="S2" gate="A" pin="G2"/> +<wire x1="162.56" y1="20.32" x2="162.56" y2="12.7" width="0.1524" layer="91"/> +<wire x1="162.56" y1="12.7" x2="162.56" y2="7.62" width="0.1524" layer="91"/> +<wire x1="160.02" y1="20.32" x2="162.56" y2="20.32" width="0.1524" layer="91"/> +<junction x="162.56" y="20.32"/> +<pinref part="S2" gate="A" pin="B2"/> +<wire x1="152.4" y1="12.7" x2="162.56" y2="12.7" width="0.1524" layer="91"/> +<junction x="162.56" y="12.7"/> +<pinref part="S2" gate="A" pin="B1"/> +<wire x1="152.4" y1="33.02" x2="162.56" y2="33.02" width="0.1524" layer="91"/> +<wire x1="162.56" y1="33.02" x2="162.56" y2="25.4" width="0.1524" layer="91"/> +<junction x="162.56" y="25.4"/> +</segment> +<segment> +<pinref part="JP4" gate="J$1" pin="3"/> +<wire x1="154.94" y1="76.2" x2="149.86" y2="76.2" width="0.1524" layer="91"/> +<pinref part="SUPPLY76" gate="GND" pin="GND"/> +<wire x1="149.86" y1="76.2" x2="149.86" y2="71.12" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C105" gate="G$1" pin="2"/> +<wire x1="127" y1="-38.1" x2="127" y2="-48.26" width="0.1524" layer="91"/> +<pinref part="SUPPLY75" gate="GND" pin="GND"/> +</segment> +</net> +<net name="AVR_RESET" class="0"> +<segment> +<pinref part="JP3" gate="G$1" pin="5"/> +<wire x1="58.42" y1="-15.24" x2="45.72" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="45.72" y1="-15.24" x2="45.72" y2="10.16" width="0.1524" layer="91"/> +<pinref part="U10" gate="A" pin="PD2_(!PCINT26/ADC26/RESET/DW)"/> +<wire x1="45.72" y1="10.16" x2="12.7" y2="10.16" width="0.1524" layer="91"/> +<wire x1="45.72" y1="10.16" x2="45.72" y2="20.32" width="0.1524" layer="91"/> +<junction x="45.72" y="10.16"/> +<pinref part="R30" gate="G$1" pin="1"/> +</segment> +</net> +<net name="3V3_BATT" class="0"> +<segment> +<pinref part="JP3" gate="G$1" pin="2"/> +<pinref part="P+46" gate="VCC" pin="VCC"/> +<wire x1="76.2" y1="-10.16" x2="78.74" y2="-10.16" width="0.1524" layer="91"/> +<wire x1="78.74" y1="-10.16" x2="78.74" y2="-2.54" width="0.1524" layer="91"/> +<label x="76.2" y="0" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="R30" gate="G$1" pin="2"/> +<pinref part="P+45" gate="VCC" pin="VCC"/> +<wire x1="45.72" y1="30.48" x2="45.72" y2="38.1" width="0.1524" layer="91"/> +<label x="48.26" y="40.64" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="U10" gate="A" pin="VCC"/> +<wire x1="-99.06" y1="35.56" x2="-109.22" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-109.22" y1="35.56" x2="-109.22" y2="38.1" width="0.1524" layer="91"/> +<pinref part="U10" gate="A" pin="AVCC"/> +<wire x1="-109.22" y1="38.1" x2="-109.22" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="38.1" x2="-109.22" y2="38.1" width="0.1524" layer="91"/> +<junction x="-109.22" y="38.1"/> +<pinref part="P+44" gate="VCC" pin="VCC"/> +<pinref part="C102" gate="G$1" pin="1"/> +<wire x1="-109.22" y1="38.1" x2="-134.62" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-134.62" y1="38.1" x2="-142.24" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-142.24" y1="38.1" x2="-149.86" y2="38.1" width="0.1524" layer="91"/> +<wire x1="-149.86" y1="38.1" x2="-149.86" y2="33.02" width="0.1524" layer="91"/> +<pinref part="C103" gate="G$1" pin="1"/> +<wire x1="-142.24" y1="38.1" x2="-142.24" y2="33.02" width="0.1524" layer="91"/> +<junction x="-142.24" y="38.1"/> +<pinref part="C104" gate="G$1" pin="1"/> +<wire x1="-134.62" y1="38.1" x2="-134.62" y2="33.02" width="0.1524" layer="91"/> +<junction x="-134.62" y="38.1"/> +<label x="-106.68" y="53.34" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="JP4" gate="J$1" pin="2"/> +<pinref part="P+48" gate="VCC" pin="VCC"/> +<wire x1="154.94" y1="78.74" x2="142.24" y2="78.74" width="0.1524" layer="91"/> +<wire x1="142.24" y1="78.74" x2="142.24" y2="86.36" width="0.1524" layer="91"/> +<label x="139.7" y="88.9" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="R82" gate="G$1" pin="2"/> +<pinref part="P+86" gate="VCC" pin="VCC"/> +<wire x1="127" y1="27.94" x2="127" y2="30.48" width="0.1524" layer="91"/> +<label x="116.84" y="33.02" size="1.27" layer="95"/> +</segment> +</net> +<net name="MKM_CONTROL_AVR_ENA" class="0"> +<segment> +<wire x1="-104.14" y1="15.24" x2="-99.06" y2="15.24" width="0.1524" layer="91"/> +<label x="-104.14" y="15.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="(PCINT6/ADC6)_PA6"/> +</segment> +</net> +<net name="MKM_AVR_SCK" class="0"> +<segment> +<pinref part="U10" gate="A" pin="PD3_(PCINT27/ADC27/SCL/SCK)"/> +<wire x1="17.78" y1="7.62" x2="48.26" y2="7.62" width="0.1524" layer="91"/> +<wire x1="48.26" y1="7.62" x2="48.26" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="JP3" gate="G$1" pin="3"/> +<wire x1="58.42" y1="-12.7" x2="48.26" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="12.7" y1="7.62" x2="17.78" y2="7.62" width="0.1524" layer="91"/> +<wire x1="17.78" y1="7.62" x2="17.78" y2="2.54" width="0.1524" layer="91"/> +<junction x="17.78" y="7.62"/> +<label x="17.78" y="2.54" size="1.27" layer="95" rot="R270" xref="yes"/> +</segment> +</net> +<net name="MKM_AVR_CS_N" class="0"> +<segment> +<wire x1="-99.06" y1="17.78" x2="-104.14" y2="17.78" width="0.1524" layer="91"/> +<label x="-104.14" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="(PC!INT5/ADC5)_PA5"/> +</segment> +</net> +<net name="MKM_AVR_MOSI" class="0"> +<segment> +<pinref part="U10" gate="A" pin="PD0_(PCINT24/ADC24/SDA/MOSI)"/> +<wire x1="12.7" y1="15.24" x2="22.86" y2="15.24" width="0.1524" layer="91"/> +<pinref part="JP3" gate="G$1" pin="4"/> +<wire x1="22.86" y1="15.24" x2="83.82" y2="15.24" width="0.1524" layer="91"/> +<wire x1="83.82" y1="15.24" x2="83.82" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="83.82" y1="-12.7" x2="76.2" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="22.86" y1="15.24" x2="22.86" y2="2.54" width="0.1524" layer="91"/> +<junction x="22.86" y="15.24"/> +<label x="22.86" y="2.54" size="1.27" layer="95" rot="R270" xref="yes"/> +</segment> +</net> +<net name="MKM_AVR_MISO" class="0"> +<segment> +<pinref part="JP3" gate="G$1" pin="1"/> +<wire x1="58.42" y1="-10.16" x2="50.8" y2="-10.16" width="0.1524" layer="91"/> +<pinref part="U10" gate="A" pin="PD1_(PCINT25/ADC25/MISO)"/> +<wire x1="50.8" y1="-10.16" x2="50.8" y2="12.7" width="0.1524" layer="91"/> +<wire x1="50.8" y1="12.7" x2="20.32" y2="12.7" width="0.1524" layer="91"/> +<wire x1="20.32" y1="12.7" x2="12.7" y2="12.7" width="0.1524" layer="91"/> +<wire x1="20.32" y1="12.7" x2="20.32" y2="2.54" width="0.1524" layer="91"/> +<junction x="20.32" y="12.7"/> +<label x="20.32" y="2.54" size="1.27" layer="95" rot="R270" xref="yes"/> +</segment> +</net> +<net name="N$4" class="0"> +<segment> +<pinref part="LED11" gate="G$1" pin="A"/> +<wire x1="147.32" y1="-78.74" x2="154.94" y2="-78.74" width="0.1524" layer="91"/> +<pinref part="R31" gate="A" pin="4"/> +</segment> +</net> +<net name="AVR_LED1" class="0"> +<segment> +<wire x1="127" y1="-78.74" x2="121.92" y2="-78.74" width="0.1524" layer="91"/> +<label x="121.92" y="-78.74" size="1.27" layer="95" rot="R180"/> +<pinref part="R31" gate="A" pin="5"/> +</segment> +<segment> +<wire x1="-99.06" y1="30.48" x2="-101.6" y2="30.48" width="0.1524" layer="91"/> +<label x="-111.76" y="30.48" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT0/ADC0)_PA0"/> +</segment> +</net> +<net name="N$5" class="0"> +<segment> +<pinref part="LED9" gate="G$1" pin="A"/> +<wire x1="147.32" y1="-81.28" x2="149.86" y2="-81.28" width="0.1524" layer="91"/> +<pinref part="R31" gate="A" pin="3"/> +</segment> +</net> +<net name="AVR_LED2" class="0"> +<segment> +<wire x1="127" y1="-81.28" x2="121.92" y2="-81.28" width="0.1524" layer="91"/> +<label x="121.92" y="-81.28" size="1.27" layer="95" rot="R180"/> +<pinref part="R31" gate="A" pin="6"/> +</segment> +<segment> +<wire x1="-99.06" y1="27.94" x2="-101.6" y2="27.94" width="0.1524" layer="91"/> +<label x="-111.76" y="27.94" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT1/ADC1/AIN0)_PA1"/> +</segment> +</net> +<net name="N$15" class="0"> +<segment> +<pinref part="LED12" gate="G$1" pin="A"/> +<wire x1="147.32" y1="-83.82" x2="154.94" y2="-83.82" width="0.1524" layer="91"/> +<pinref part="R31" gate="A" pin="2"/> +</segment> +</net> +<net name="AVR_LED3" class="0"> +<segment> +<wire x1="127" y1="-83.82" x2="121.92" y2="-83.82" width="0.1524" layer="91"/> +<label x="121.92" y="-83.82" size="1.27" layer="95" rot="R180"/> +<pinref part="R31" gate="A" pin="7"/> +</segment> +<segment> +<wire x1="-99.06" y1="25.4" x2="-101.6" y2="25.4" width="0.1524" layer="91"/> +<label x="-111.76" y="25.4" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT2/ADC2/AIN1)_PA2"/> +</segment> +</net> +<net name="N$16" class="0"> +<segment> +<pinref part="LED10" gate="G$1" pin="A"/> +<wire x1="147.32" y1="-86.36" x2="149.86" y2="-86.36" width="0.1524" layer="91"/> +<pinref part="R31" gate="A" pin="1"/> +</segment> +</net> +<net name="AVR_LED4" class="0"> +<segment> +<wire x1="127" y1="-86.36" x2="121.92" y2="-86.36" width="0.1524" layer="91"/> +<label x="121.92" y="-86.36" size="1.27" layer="95" rot="R180"/> +<pinref part="R31" gate="A" pin="8"/> +</segment> +<segment> +<wire x1="-99.06" y1="22.86" x2="-101.6" y2="22.86" width="0.1524" layer="91"/> +<label x="-111.76" y="22.86" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT3/ADC3)_PA3"/> +</segment> +</net> +<net name="AVR_GPIO_0" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="2"/> +<wire x1="154.94" y1="-25.4" x2="149.86" y2="-25.4" width="0.1524" layer="91"/> +<label x="149.86" y="-25.4" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="38.1" x2="17.78" y2="38.1" width="0.1524" layer="91"/> +<label x="17.78" y="38.1" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="PC0_(PCINT16/ADC16/TOCC0/SS/XCK)"/> +</segment> +</net> +<net name="AVR_GPIO_1" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="3"/> +<wire x1="154.94" y1="-27.94" x2="149.86" y2="-27.94" width="0.1524" layer="91"/> +<label x="149.86" y="-27.94" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="35.56" x2="17.78" y2="35.56" width="0.1524" layer="91"/> +<label x="17.78" y="35.56" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="PC1_(PCINT17/ADC17/TOCC1/INT0/CLKO)"/> +</segment> +</net> +<net name="AVR_GPIO_2" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="4"/> +<wire x1="154.94" y1="-30.48" x2="149.86" y2="-30.48" width="0.1524" layer="91"/> +<label x="149.86" y="-30.48" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="33.02" x2="17.78" y2="33.02" width="0.1524" layer="91"/> +<label x="17.78" y="33.02" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT18/ADC18/TOCC2/RXD/INT1)_PC2"/> +</segment> +</net> +<net name="AVR_GPIO_3" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="5"/> +<wire x1="154.94" y1="-33.02" x2="149.86" y2="-33.02" width="0.1524" layer="91"/> +<label x="149.86" y="-33.02" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="30.48" x2="17.78" y2="30.48" width="0.1524" layer="91"/> +<label x="17.78" y="30.48" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT19/ADC19/TOCC3/TXD)_PC3"/> +</segment> +</net> +<net name="AVR_GPIO_4" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="6"/> +<wire x1="154.94" y1="-35.56" x2="149.86" y2="-35.56" width="0.1524" layer="91"/> +<label x="149.86" y="-35.56" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="27.94" x2="17.78" y2="27.94" width="0.1524" layer="91"/> +<label x="17.78" y="27.94" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT20/ADC20/TOCC4)_PC4"/> +</segment> +</net> +<net name="AVR_GPIO_5" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="7"/> +<wire x1="154.94" y1="-38.1" x2="149.86" y2="-38.1" width="0.1524" layer="91"/> +<label x="149.86" y="-38.1" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="25.4" x2="17.78" y2="25.4" width="0.1524" layer="91"/> +<label x="17.78" y="25.4" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT21/ADC21/TOCC5/ICP1/T0)_PC5"/> +</segment> +</net> +<net name="AVR_GPIO_6" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="8"/> +<wire x1="154.94" y1="-40.64" x2="149.86" y2="-40.64" width="0.1524" layer="91"/> +<label x="149.86" y="-40.64" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="22.86" x2="17.78" y2="22.86" width="0.1524" layer="91"/> +<label x="17.78" y="22.86" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT22/ADC22/CLKI/TOCC6)_PC6"/> +</segment> +</net> +<net name="AVR_GPIO_7" class="0"> +<segment> +<pinref part="JP5" gate="G$1" pin="9"/> +<wire x1="154.94" y1="-43.18" x2="149.86" y2="-43.18" width="0.1524" layer="91"/> +<label x="149.86" y="-43.18" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<wire x1="12.7" y1="20.32" x2="17.78" y2="20.32" width="0.1524" layer="91"/> +<label x="17.78" y="20.32" size="1.27" layer="95"/> +<pinref part="U10" gate="A" pin="(PCINT23/ADC23/TOCC7/T1)_PC7"/> +</segment> +</net> +<net name="AVR_PANIC" class="0"> +<segment> +<wire x1="137.16" y1="12.7" x2="127" y2="12.7" width="0.1524" layer="91"/> +<label x="116.84" y="12.7" size="1.27" layer="95" rot="R180"/> +<pinref part="S2" gate="A" pin="A2"/> +<pinref part="R82" gate="G$1" pin="1"/> +<wire x1="127" y1="12.7" x2="119.38" y2="12.7" width="0.1524" layer="91"/> +<wire x1="127" y1="17.78" x2="127" y2="12.7" width="0.1524" layer="91"/> +<junction x="127" y="12.7"/> +</segment> +<segment> +<wire x1="-99.06" y1="20.32" x2="-101.6" y2="20.32" width="0.1524" layer="91"/> +<label x="-111.76" y="20.32" size="1.27" layer="95"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="JP4" gate="J$1" pin="1"/> +<wire x1="154.94" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/> +<pinref part="P+49" gate="VCC" pin="VCC"/> +<wire x1="149.86" y1="81.28" x2="149.86" y2="86.36" width="0.1524" layer="91"/> +<label x="162.56" y="88.9" size="1.27" layer="95" rot="R180"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_0" class="0"> +<segment> +<wire x1="-99.06" y1="7.62" x2="-101.6" y2="7.62" width="0.1524" layer="91"/> +<label x="-101.6" y="7.62" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="PB0_(PCINT8/ADC8)"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_1" class="0"> +<segment> +<wire x1="-99.06" y1="5.08" x2="-101.6" y2="5.08" width="0.1524" layer="91"/> +<label x="-101.6" y="5.08" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="PB1_(PCINT9/ADC9)"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_0" class="0"> +<segment> +<wire x1="-99.06" y1="-2.54" x2="-101.6" y2="-2.54" width="0.1524" layer="91"/> +<label x="-101.6" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_1" class="0"> +<segment> +<wire x1="-99.06" y1="-5.08" x2="-101.6" y2="-5.08" width="0.1524" layer="91"/> +<label x="-101.6" y="-5.08" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<wire x1="127" y1="-22.86" x2="127" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="JP5" gate="G$1" pin="1"/> +<wire x1="154.94" y1="-22.86" x2="127" y2="-22.86" width="0.1524" layer="91"/> +<label x="129.54" y="-17.78" size="1.778" layer="95"/> +<pinref part="P+47" gate="VCC" pin="VCC"/> +<pinref part="C105" gate="G$1" pin="1"/> +<wire x1="127" y1="-22.86" x2="127" y2="-30.48" width="0.1524" layer="91"/> +<junction x="127" y="-22.86"/> +</segment> +</net> +<net name="MKM_CONTROL_FPGA_DIS" class="0"> +<segment> +<wire x1="-104.14" y1="12.7" x2="-99.06" y2="12.7" width="0.1524" layer="91"/> +<label x="-104.14" y="12.7" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_2" class="0"> +<segment> +<wire x1="-99.06" y1="2.54" x2="-101.6" y2="2.54" width="0.1524" layer="91"/> +<label x="-101.6" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_ARM_3" class="0"> +<segment> +<wire x1="-99.06" y1="0" x2="-101.6" y2="0" width="0.1524" layer="91"/> +<label x="-101.6" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_2" class="0"> +<segment> +<wire x1="-99.06" y1="-7.62" x2="-101.6" y2="-7.62" width="0.1524" layer="91"/> +<label x="-101.6" y="-7.62" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="PB6_(PCINT14/ADC14)"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_3" class="0"> +<segment> +<wire x1="-99.06" y1="-10.16" x2="-101.6" y2="-10.16" width="0.1524" layer="91"/> +<label x="-101.6" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="U10" gate="A" pin="PB7_(PCINT15/ADC15)"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>Master Key Memory</description> +<plain> +<text x="205.74" y="55.88" size="1.27" layer="91">CS pull-up to disable MKM by +default (allows programming +of AVR)</text> +<text x="172.72" y="101.6" size="2.54" layer="91">Master Key Memory</text> +<text x="-30.48" y="129.54" size="2.54" layer="91">SPI mux controlling access to the MKM. + +Normally, the FPGA has R/W access to the MKM but on a +tamper event the tamper detect MCU (AVR) will grab access +to the MKM and erase the contents.</text> +<text x="81.28" y="43.18" size="1.27" layer="91">Make AVR unable to read the +MKM by installing this jumper</text> +<text x="-17.78" y="48.26" size="1.27" layer="91">AVR access default +disabled through pull-up</text> +<text x="-20.32" y="20.32" size="1.27" layer="91">FPGA access default +enabled through pull-down</text> +<text x="236.22" y="-50.8" size="2.54" layer="94">Master Key Memory</text> +</plain> +<instances> +<instance part="U12" gate="A" x="190.5" y="55.88"/> +<instance part="SUPPLY83" gate="GND" x="170.18" y="30.48"/> +<instance part="P+52" gate="VCC" x="170.18" y="93.98" smashed="yes"/> +<instance part="R33" gate="G$1" x="160.02" y="76.2" smashed="yes" rot="R270"> +<attribute name="NAME" x="153.67" y="77.6986" size="1.778" layer="95"/> +<attribute name="VALUE" x="158.75" y="76.962" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="P+50" gate="VCC" x="-33.02" y="96.52" smashed="yes"/> +<instance part="R34" gate="G$1" x="149.86" y="76.2" smashed="yes" rot="R90"> +<attribute name="NAME" x="146.05" y="79.7814" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="146.05" y="76.962" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="P+51" gate="VCC" x="160.02" y="93.98" smashed="yes"/> +<instance part="C106" gate="G$1" x="-43.18" y="78.74" smashed="yes"> +<attribute name="NAME" x="-53.34" y="76.2" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="-53.34" y="78.74" size="1.27" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="-43.18" y="78.74" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-43.18" y="78.74" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C107" gate="G$1" x="175.26" y="86.36" smashed="yes"> +<attribute name="NAME" x="177.8" y="88.9" size="1.27" layer="95" font="vector"/> +<attribute name="VALUE" x="177.8" y="86.36" size="1.27" layer="96" font="vector"/> +<attribute name="DIELECTRIC" x="175.26" y="86.36" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="175.26" y="86.36" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY84" gate="GND" x="175.26" y="76.2"/> +<instance part="JP6" gate="A" x="76.2" y="45.72"/> +<instance part="SUPPLY80" gate="GND" x="76.2" y="33.02"/> +<instance part="FRAME13" gate="G$1" x="-106.68" y="-71.12"/> +<instance part="IC4" gate="A" x="30.48" y="60.96"/> +<instance part="IC4" gate="B" x="30.48" y="33.02"/> +<instance part="IC4" gate="P" x="-33.02" y="78.74"/> +<instance part="R79" gate="G$1" x="45.72" y="76.2" rot="R90"> +<attribute name="TOLERANCE" x="45.72" y="76.2" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY44" gate="GND" x="-33.02" y="63.5"/> +<instance part="R80" gate="G$1" x="10.16" y="76.2" rot="R90"> +<attribute name="TOLERANCE" x="10.16" y="76.2" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R81" gate="G$1" x="10.16" y="15.24" rot="R270"> +<attribute name="TOLERANCE" x="10.16" y="15.24" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="SUPPLY222" gate="GND" x="10.16" y="5.08"/> +<instance part="P+5" gate="VCC" x="10.16" y="96.52" smashed="yes"/> +<instance part="P+13" gate="VCC" x="45.72" y="96.52" smashed="yes"/> +<instance part="P+85" gate="VCC" x="149.86" y="93.98" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY83" gate="GND" pin="GND"/> +<wire x1="170.18" y1="43.18" x2="170.18" y2="33.02" width="0.1524" layer="91"/> +<pinref part="U12" gate="A" pin="VSS"/> +<wire x1="170.18" y1="43.18" x2="172.72" y2="43.18" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C107" gate="G$1" pin="2"/> +<pinref part="SUPPLY84" gate="GND" pin="GND"/> +<wire x1="175.26" y1="81.28" x2="175.26" y2="78.74" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="JP6" gate="A" pin="1"/> +<pinref part="SUPPLY80" gate="GND" pin="GND"/> +<wire x1="76.2" y1="38.1" x2="76.2" y2="35.56" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC4" gate="P" pin="GND"/> +<wire x1="-33.02" y1="66.04" x2="-33.02" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="68.58" x2="-33.02" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="73.66" x2="-43.18" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="68.58" x2="-33.02" y2="68.58" width="0.1524" layer="91"/> +<junction x="-33.02" y="68.58"/> +<pinref part="SUPPLY44" gate="GND" pin="GND"/> +<pinref part="C106" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="R81" gate="G$1" pin="2"/> +<wire x1="10.16" y1="10.16" x2="10.16" y2="7.62" width="0.1524" layer="91"/> +<pinref part="SUPPLY222" gate="GND" pin="GND"/> +</segment> +</net> +<net name="N$31" class="0"> +<segment> +<pinref part="U12" gate="A" pin="!HOLD"/> +<pinref part="R33" gate="G$1" pin="2"/> +<wire x1="172.72" y1="53.34" x2="160.02" y2="53.34" width="0.1524" layer="91"/> +<wire x1="160.02" y1="53.34" x2="160.02" y2="71.12" width="0.1524" layer="91"/> +</segment> +</net> +<net name="MKM_SCK" class="0"> +<segment> +<pinref part="U12" gate="A" pin="SCK"/> +<wire x1="172.72" y1="55.88" x2="139.7" y2="55.88" width="0.1524" layer="91"/> +<label x="139.7" y="55.88" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="IC4" gate="A" pin="Y2"/> +<wire x1="43.18" y1="63.5" x2="48.26" y2="63.5" width="0.1524" layer="91"/> +<wire x1="48.26" y1="63.5" x2="48.26" y2="35.56" width="0.1524" layer="91"/> +<pinref part="IC4" gate="B" pin="Y2"/> +<wire x1="48.26" y1="35.56" x2="43.18" y2="35.56" width="0.1524" layer="91"/> +<wire x1="48.26" y1="63.5" x2="60.96" y2="63.5" width="0.1524" layer="91"/> +<junction x="48.26" y="63.5"/> +<label x="60.96" y="63.5" size="1.27" layer="95"/> +</segment> +</net> +<net name="MKM_MOSI" class="0"> +<segment> +<pinref part="U12" gate="A" pin="SI"/> +<wire x1="139.7" y1="58.42" x2="172.72" y2="58.42" width="0.1524" layer="91"/> +<label x="139.7" y="58.42" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="IC4" gate="B" pin="Y3"/> +<wire x1="43.18" y1="33.02" x2="50.8" y2="33.02" width="0.1524" layer="91"/> +<wire x1="50.8" y1="33.02" x2="50.8" y2="60.96" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="Y3"/> +<wire x1="43.18" y1="60.96" x2="50.8" y2="60.96" width="0.1524" layer="91"/> +<junction x="50.8" y="60.96"/> +<wire x1="50.8" y1="60.96" x2="60.96" y2="60.96" width="0.1524" layer="91"/> +<label x="60.96" y="60.96" size="1.27" layer="95"/> +</segment> +</net> +<net name="MKM_CS_N" class="0"> +<segment> +<pinref part="U12" gate="A" pin="!CS"/> +<wire x1="172.72" y1="60.96" x2="149.86" y2="60.96" width="0.1524" layer="91"/> +<pinref part="R34" gate="G$1" pin="1"/> +<wire x1="149.86" y1="60.96" x2="139.7" y2="60.96" width="0.1524" layer="91"/> +<wire x1="149.86" y1="71.12" x2="149.86" y2="60.96" width="0.1524" layer="91"/> +<junction x="149.86" y="60.96"/> +<label x="139.7" y="60.96" size="1.27" layer="95" rot="R180"/> +</segment> +<segment> +<pinref part="IC4" gate="B" pin="Y1"/> +<wire x1="43.18" y1="38.1" x2="45.72" y2="38.1" width="0.1524" layer="91"/> +<wire x1="45.72" y1="38.1" x2="45.72" y2="66.04" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="Y1"/> +<wire x1="45.72" y1="66.04" x2="43.18" y2="66.04" width="0.1524" layer="91"/> +<junction x="45.72" y="66.04"/> +<label x="60.96" y="66.04" size="1.27" layer="95"/> +<pinref part="R79" gate="G$1" pin="1"/> +<wire x1="45.72" y1="66.04" x2="60.96" y2="66.04" width="0.1524" layer="91"/> +<wire x1="45.72" y1="71.12" x2="45.72" y2="66.04" width="0.1524" layer="91"/> +<junction x="45.72" y="66.04"/> +</segment> +</net> +<net name="MKM_MISO" class="0"> +<segment> +<pinref part="U12" gate="A" pin="SO"/> +<wire x1="210.82" y1="66.04" x2="208.28" y2="66.04" width="0.1524" layer="91"/> +<label x="213.36" y="68.58" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="IC4" gate="B" pin="A4"/> +<wire x1="17.78" y1="30.48" x2="15.24" y2="30.48" width="0.1524" layer="91"/> +<wire x1="15.24" y1="30.48" x2="15.24" y2="58.42" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="A4"/> +<wire x1="17.78" y1="58.42" x2="15.24" y2="58.42" width="0.1524" layer="91"/> +<wire x1="15.24" y1="58.42" x2="5.08" y2="58.42" width="0.1524" layer="91"/> +<junction x="15.24" y="58.42"/> +<label x="2.54" y="58.42" size="1.27" layer="95" rot="R180"/> +</segment> +</net> +<net name="3V3_BATT" class="0"> +<segment> +<pinref part="U12" gate="A" pin="VCC"/> +<pinref part="P+52" gate="VCC" pin="VCC"/> +<wire x1="172.72" y1="66.04" x2="170.18" y2="66.04" width="0.1524" layer="91"/> +<wire x1="170.18" y1="66.04" x2="170.18" y2="88.9" width="0.1524" layer="91"/> +<wire x1="170.18" y1="88.9" x2="170.18" y2="91.44" width="0.1524" layer="91"/> +<pinref part="C107" gate="G$1" pin="1"/> +<wire x1="175.26" y1="88.9" x2="170.18" y2="88.9" width="0.1524" layer="91"/> +<junction x="170.18" y="88.9"/> +<label x="167.64" y="96.52" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="P+50" gate="VCC" pin="VCC"/> +<wire x1="-33.02" y1="88.9" x2="-33.02" y2="93.98" width="0.1524" layer="91"/> +<wire x1="-33.02" y1="88.9" x2="-43.18" y2="88.9" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="88.9" x2="-43.18" y2="81.28" width="0.1524" layer="91"/> +<pinref part="C106" gate="G$1" pin="1"/> +<label x="-35.56" y="99.06" size="1.27" layer="95"/> +<pinref part="IC4" gate="P" pin="VCC"/> +<wire x1="-33.02" y1="88.9" x2="-33.02" y2="86.36" width="0.1524" layer="91"/> +<junction x="-33.02" y="88.9"/> +</segment> +<segment> +<pinref part="R33" gate="G$1" pin="1"/> +<pinref part="P+51" gate="VCC" pin="VCC"/> +<wire x1="160.02" y1="81.28" x2="160.02" y2="91.44" width="0.1524" layer="91"/> +<label x="154.94" y="96.52" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="R80" gate="G$1" pin="2"/> +<pinref part="P+5" gate="VCC" pin="VCC"/> +<wire x1="10.16" y1="81.28" x2="10.16" y2="93.98" width="0.1524" layer="91"/> +<label x="5.08" y="99.06" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="R79" gate="G$1" pin="2"/> +<pinref part="P+13" gate="VCC" pin="VCC"/> +<wire x1="45.72" y1="81.28" x2="45.72" y2="93.98" width="0.1524" layer="91"/> +<label x="43.18" y="99.06" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="R34" gate="G$1" pin="2"/> +<wire x1="149.86" y1="81.28" x2="149.86" y2="91.44" width="0.1524" layer="91"/> +<pinref part="P+85" gate="VCC" pin="VCC"/> +<label x="142.24" y="96.52" size="1.27" layer="95"/> +</segment> +</net> +<net name="MKM_CONTROL_AVR_ENA" class="0"> +<segment> +<wire x1="10.16" y1="53.34" x2="5.08" y2="53.34" width="0.1524" layer="91"/> +<pinref part="IC4" gate="A" pin="G"/> +<wire x1="17.78" y1="53.34" x2="10.16" y2="53.34" width="0.1524" layer="91"/> +<pinref part="R80" gate="G$1" pin="1"/> +<wire x1="10.16" y1="71.12" x2="10.16" y2="53.34" width="0.1524" layer="91"/> +<junction x="10.16" y="53.34"/> +<label x="5.08" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_AVR_SCK" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="A2"/> +<wire x1="17.78" y1="63.5" x2="5.08" y2="63.5" width="0.1524" layer="91"/> +<label x="5.08" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_CS_N" class="0"> +<segment> +<pinref part="IC4" gate="B" pin="A1"/> +<wire x1="17.78" y1="38.1" x2="5.08" y2="38.1" width="0.1524" layer="91"/> +<label x="5.08" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_AVR_CS_N" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="A1"/> +<wire x1="17.78" y1="66.04" x2="5.08" y2="66.04" width="0.1524" layer="91"/> +<label x="5.08" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_MOSI" class="0"> +<segment> +<pinref part="IC4" gate="B" pin="A3"/> +<wire x1="17.78" y1="33.02" x2="5.08" y2="33.02" width="0.1524" layer="91"/> +<label x="5.08" y="33.02" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_AVR_MOSI" class="0"> +<segment> +<pinref part="IC4" gate="A" pin="A3"/> +<wire x1="17.78" y1="60.96" x2="5.08" y2="60.96" width="0.1524" layer="91"/> +<label x="5.08" y="60.96" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_MISO" class="0"> +<segment> +<wire x1="43.18" y1="30.48" x2="48.26" y2="30.48" width="0.1524" layer="91"/> +<label x="48.26" y="30.48" size="1.27" layer="95" xref="yes"/> +<pinref part="IC4" gate="B" pin="Y4"/> +</segment> +</net> +<net name="MKM_AVR_MISO" class="0"> +<segment> +<wire x1="43.18" y1="58.42" x2="76.2" y2="58.42" width="0.1524" layer="91"/> +<label x="81.28" y="58.42" size="1.27" layer="95" xref="yes"/> +<pinref part="JP6" gate="A" pin="2"/> +<wire x1="76.2" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/> +<wire x1="76.2" y1="53.34" x2="76.2" y2="58.42" width="0.1524" layer="91"/> +<junction x="76.2" y="58.42"/> +<pinref part="IC4" gate="A" pin="Y4"/> +</segment> +</net> +<net name="MKM_FPGA_SCK" class="0"> +<segment> +<pinref part="IC4" gate="B" pin="A2"/> +<wire x1="17.78" y1="35.56" x2="5.08" y2="35.56" width="0.1524" layer="91"/> +<label x="5.08" y="35.56" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="MKM_CONTROL_FPGA_DIS" class="0"> +<segment> +<pinref part="IC4" gate="B" pin="G"/> +<wire x1="17.78" y1="25.4" x2="10.16" y2="25.4" width="0.1524" layer="91"/> +<pinref part="R81" gate="G$1" pin="1"/> +<wire x1="10.16" y1="25.4" x2="10.16" y2="20.32" width="0.1524" layer="91"/> +<wire x1="10.16" y1="25.4" x2="5.08" y2="25.4" width="0.1524" layer="91"/> +<junction x="10.16" y="25.4"/> +<label x="5.08" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA configuration interface</description> +<plain> +<text x="-129.54" y="160.02" size="1.778" layer="91">*) Configuration Interface</text> +<text x="-132.08" y="48.26" size="1.778" layer="91">M[2:0] == 3'b001 => Master SPI</text> +<text x="-139.7" y="81.28" size="1.778" layer="91">*) Since VCCO is 3.3V, CFGBVS must be tied High. + +*) Battery is not used + +*) PROG_B is dedicated input -- can be driven by STM32 directly + +*) INIT_B is bi-directional open-drain, must be driven with MOSFET to ground</text> +<text x="-63.5" y="20.32" size="1.778" layer="91">*) "Not DONE" LED, should be of red color</text> +<text x="66.04" y="17.78" size="1.6764" layer="94">FPGA configuration interface</text> +</plain> +<instances> +<instance part="U13" gate="B0" x="-111.76" y="132.08"> +<attribute name="MFR" x="-111.76" y="132.08" size="1.778" layer="96" display="off"/> +<attribute name="MPN" x="-111.76" y="132.08" size="1.778" layer="96" display="off"/> +<attribute name="OC_DIGIKEY" x="-111.76" y="132.08" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY86" gate="GND" x="-101.6" y="106.68"/> +<instance part="R35" gate="G$1" x="-119.38" y="30.48" rot="R90"> +<attribute name="TOLERANCE" x="-119.38" y="30.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY85" gate="GND" x="-119.38" y="17.78"/> +<instance part="SUPPLY87" gate="GND" x="-99.06" y="17.78"/> +<instance part="FRAME14" gate="G$1" x="-149.86" y="-2.54"/> +<instance part="R36" gate="G$1" x="-99.06" y="30.48" rot="R90"> +<attribute name="TOLERANCE" x="-99.06" y="30.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R37" gate="G$1" x="-78.74" y="50.8" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="-78.74" y="50.8" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="-74.93" y="52.2986" size="1.778" layer="95"/> +<attribute name="VALUE" x="-74.93" y="47.498" size="1.778" layer="96"/> +</instance> +<instance part="R41" gate="G$1" x="0" y="149.86" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="0" y="149.86" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="8.89" y="153.4414" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="8.89" y="148.082" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R40" gate="G$1" x="-10.16" y="149.86" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="-10.16" y="149.86" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="-13.97" y="153.4414" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-13.97" y="148.082" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="Q4" gate="G$1" x="0" y="129.54" rot="MR0"/> +<instance part="SUPPLY88" gate="GND" x="-10.16" y="104.14"/> +<instance part="R42" gate="G$1" x="10.16" y="116.84" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="10.16" y="116.84" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="13.97" y="115.7986" size="1.778" layer="95"/> +<attribute name="VALUE" x="13.97" y="110.998" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY89" gate="GND" x="10.16" y="104.14"/> +<instance part="LED13" gate="G$1" x="-38.1" y="35.56" smashed="yes"> +<attribute name="NAME" x="-35.052" y="37.084" size="1.778" layer="95"/> +<attribute name="VALUE" x="-35.052" y="32.385" size="1.778" layer="96"/> +</instance> +<instance part="R38" gate="G$1" x="-38.1" y="48.26" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="-38.1" y="48.26" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="-34.29" y="49.7586" size="1.778" layer="95"/> +<attribute name="VALUE" x="-34.29" y="44.958" size="1.778" layer="96"/> +</instance> +<instance part="R39" gate="G$1" x="-25.4" y="27.94" rot="R180"> +<attribute name="TOLERANCE" x="-25.4" y="27.94" size="1.778" layer="96" rot="R180" display="off"/> +</instance> +<instance part="SV1" gate="1" x="86.36" y="48.26" rot="R180"/> +<instance part="SUPPLY91" gate="GND" x="73.66" y="30.48"/> +<instance part="SUPPLY90" gate="GND" x="38.1" y="30.48"/> +<instance part="C108" gate="G$1" x="38.1" y="45.72"> +<attribute name="DIELECTRIC" x="38.1" y="45.72" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="38.1" y="45.72" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="38.1" y="45.72" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R43" gate="G$1" x="66.04" y="66.04" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="66.04" y="66.04" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="74.93" y="70.0786" size="1.778" layer="95"/> +</instance> +<instance part="R44" gate="G$1" x="68.58" y="66.04" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="68.58" y="66.04" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="74.93" y="67.5386" size="1.778" layer="95"/> +</instance> +<instance part="R45" gate="G$1" x="71.12" y="66.04" smashed="yes" rot="R90"> +<attribute name="TOLERANCE" x="71.12" y="66.04" size="1.778" layer="96" rot="R90" display="off"/> +<attribute name="NAME" x="74.93" y="64.9986" size="1.778" layer="95"/> +<attribute name="VALUE" x="74.93" y="62.738" size="1.778" layer="96"/> +</instance> +<instance part="P+54" gate="VCC" x="-78.74" y="63.5" smashed="yes"/> +<instance part="P+55" gate="VCC" x="-38.1" y="63.5" smashed="yes"/> +<instance part="P+57" gate="VCC" x="38.1" y="63.5" smashed="yes"/> +<instance part="P+58" gate="VCC" x="68.58" y="83.82" smashed="yes"/> +<instance part="P+53" gate="VCC" x="-96.52" y="157.48" smashed="yes"/> +<instance part="P+56" gate="VCC" x="-5.08" y="167.64" smashed="yes"/> +<instance part="R62" gate="G$1" x="-91.44" y="137.16" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-91.44" y="137.16" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-93.98" y="139.7" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-101.6" y="139.7" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R63" gate="G$1" x="-91.44" y="134.62" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-91.44" y="134.62" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-93.98" y="137.16" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-101.6" y="137.16" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R71" gate="G$1" x="-91.44" y="132.08" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-91.44" y="132.08" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-93.98" y="134.62" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-101.6" y="134.62" size="1.778" layer="96" rot="R180"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY86" gate="GND" pin="GND"/> +<wire x1="-101.6" y1="109.22" x2="-101.6" y2="149.86" width="0.1524" layer="91"/> +<pinref part="U13" gate="B0" pin="VCCBATT_0"/> +<wire x1="-101.6" y1="149.86" x2="-106.68" y2="149.86" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R35" gate="G$1" pin="1"/> +<pinref part="SUPPLY85" gate="GND" pin="GND"/> +<wire x1="-119.38" y1="25.4" x2="-119.38" y2="20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<wire x1="-99.06" y1="25.4" x2="-99.06" y2="20.32" width="0.1524" layer="91"/> +<pinref part="SUPPLY87" gate="GND" pin="GND"/> +<pinref part="R36" gate="G$1" pin="1"/> +</segment> +<segment> +<pinref part="Q4" gate="G$1" pin="S"/> +<pinref part="SUPPLY88" gate="GND" pin="GND"/> +<wire x1="-5.08" y1="127" x2="-10.16" y2="127" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="127" x2="-10.16" y2="106.68" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="R42" gate="G$1" pin="1"/> +<pinref part="SUPPLY89" gate="GND" pin="GND"/> +<wire x1="10.16" y1="111.76" x2="10.16" y2="106.68" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY91" gate="GND" pin="GND"/> +<wire x1="73.66" y1="33.02" x2="73.66" y2="38.1" width="0.1524" layer="91"/> +<pinref part="SV1" gate="1" pin="8"/> +<wire x1="73.66" y1="38.1" x2="78.74" y2="38.1" width="0.1524" layer="91"/> +<pinref part="SV1" gate="1" pin="7"/> +<wire x1="78.74" y1="40.64" x2="73.66" y2="40.64" width="0.1524" layer="91"/> +<wire x1="73.66" y1="40.64" x2="73.66" y2="38.1" width="0.1524" layer="91"/> +<junction x="73.66" y="38.1"/> +<pinref part="SV1" gate="1" pin="6"/> +<wire x1="78.74" y1="43.18" x2="73.66" y2="43.18" width="0.1524" layer="91"/> +<wire x1="73.66" y1="43.18" x2="73.66" y2="40.64" width="0.1524" layer="91"/> +<junction x="73.66" y="40.64"/> +</segment> +<segment> +<pinref part="SUPPLY90" gate="GND" pin="GND"/> +<wire x1="38.1" y1="33.02" x2="38.1" y2="40.64" width="0.1524" layer="91"/> +<pinref part="C108" gate="G$1" pin="2"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="-78.74" y1="55.88" x2="-78.74" y2="60.96" width="0.1524" layer="91"/> +<label x="-93.98" y="60.96" size="1.778" layer="95"/> +<pinref part="R37" gate="G$1" pin="2"/> +<pinref part="P+54" gate="VCC" pin="VCC"/> +</segment> +<segment> +<label x="-53.34" y="60.96" size="1.778" layer="95"/> +<pinref part="R38" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="53.34" x2="-38.1" y2="60.96" width="0.1524" layer="91"/> +<pinref part="P+55" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="R43" gate="G$1" pin="2"/> +<wire x1="66.04" y1="71.12" x2="66.04" y2="73.66" width="0.1524" layer="91"/> +<wire x1="66.04" y1="73.66" x2="68.58" y2="73.66" width="0.1524" layer="91"/> +<pinref part="R45" gate="G$1" pin="2"/> +<wire x1="68.58" y1="73.66" x2="71.12" y2="73.66" width="0.1524" layer="91"/> +<wire x1="71.12" y1="73.66" x2="71.12" y2="71.12" width="0.1524" layer="91"/> +<label x="71.12" y="81.28" size="1.778" layer="95"/> +<pinref part="R44" gate="G$1" pin="2"/> +<wire x1="68.58" y1="71.12" x2="68.58" y2="73.66" width="0.1524" layer="91"/> +<junction x="68.58" y="73.66"/> +<pinref part="P+58" gate="VCC" pin="VCC"/> +<wire x1="68.58" y1="73.66" x2="68.58" y2="81.28" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SV1" gate="1" pin="1"/> +<wire x1="78.74" y1="55.88" x2="38.1" y2="55.88" width="0.1524" layer="91"/> +<wire x1="38.1" y1="55.88" x2="38.1" y2="60.96" width="0.1524" layer="91"/> +<wire x1="38.1" y1="48.26" x2="38.1" y2="55.88" width="0.1524" layer="91"/> +<junction x="38.1" y="55.88"/> +<label x="40.64" y="58.42" size="1.778" layer="95"/> +<pinref part="C108" gate="G$1" pin="1"/> +<pinref part="P+57" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="R41" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="160.02" x2="-5.08" y2="160.02" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="160.02" x2="0" y2="160.02" width="0.1524" layer="91"/> +<wire x1="0" y1="154.94" x2="0" y2="160.02" width="0.1524" layer="91"/> +<pinref part="R40" gate="G$1" pin="2"/> +<wire x1="-10.16" y1="154.94" x2="-10.16" y2="160.02" width="0.1524" layer="91"/> +<pinref part="P+56" gate="VCC" pin="VCC"/> +<wire x1="-5.08" y1="165.1" x2="-5.08" y2="160.02" width="0.1524" layer="91"/> +<junction x="-5.08" y="160.02"/> +<label x="-2.54" y="165.1" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="U13" gate="B0" pin="VCCO_0@0"/> +<wire x1="-106.68" y1="147.32" x2="-96.52" y2="147.32" width="0.1524" layer="91"/> +<pinref part="U13" gate="B0" pin="VCCO_0@1"/> +<wire x1="-106.68" y1="144.78" x2="-96.52" y2="144.78" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="144.78" x2="-96.52" y2="147.32" width="0.1524" layer="91"/> +<junction x="-96.52" y="147.32"/> +<label x="-93.98" y="154.94" size="1.778" layer="95"/> +<pinref part="U13" gate="B0" pin="CFGBVS_0"/> +<wire x1="-106.68" y1="142.24" x2="-96.52" y2="142.24" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="142.24" x2="-96.52" y2="144.78" width="0.1524" layer="91"/> +<junction x="-96.52" y="144.78"/> +<pinref part="P+53" gate="VCC" pin="VCC"/> +<wire x1="-96.52" y1="154.94" x2="-96.52" y2="147.32" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_M2" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="M2_0"/> +<wire x1="-106.68" y1="124.46" x2="-71.12" y2="124.46" width="0.1524" layer="91"/> +<label x="-83.82" y="124.46" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="R35" gate="G$1" pin="2"/> +<wire x1="-119.38" y1="35.56" x2="-119.38" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="40.64" x2="-134.62" y2="40.64" width="0.1524" layer="91"/> +<label x="-132.08" y="41.91" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_JTAG_TCK" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="TCK_0"/> +<wire x1="-106.68" y1="121.92" x2="-71.12" y2="121.92" width="0.1524" layer="91"/> +<label x="-71.12" y="121.92" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="1" pin="2"/> +<wire x1="78.74" y1="53.34" x2="71.12" y2="53.34" width="0.1524" layer="91"/> +<label x="63.5" y="53.34" size="1.27" layer="95" rot="R180"/> +<pinref part="R45" gate="G$1" pin="1"/> +<wire x1="71.12" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/> +<wire x1="71.12" y1="60.96" x2="71.12" y2="53.34" width="0.1524" layer="91"/> +<junction x="71.12" y="53.34"/> +</segment> +</net> +<net name="FPGA_JTAG_TDI" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="TDI_0"/> +<wire x1="-106.68" y1="119.38" x2="-71.12" y2="119.38" width="0.1524" layer="91"/> +<label x="-71.12" y="119.38" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="1" pin="4"/> +<wire x1="78.74" y1="48.26" x2="66.04" y2="48.26" width="0.1524" layer="91"/> +<label x="63.5" y="48.26" size="1.27" layer="95" rot="R180"/> +<pinref part="R43" gate="G$1" pin="1"/> +<wire x1="66.04" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/> +<wire x1="66.04" y1="60.96" x2="66.04" y2="48.26" width="0.1524" layer="91"/> +<junction x="66.04" y="48.26"/> +</segment> +</net> +<net name="FPGA_JTAG_TDO" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="TDO_0"/> +<wire x1="-106.68" y1="116.84" x2="-71.12" y2="116.84" width="0.1524" layer="91"/> +<label x="-71.12" y="116.84" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="1" pin="5"/> +<wire x1="78.74" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/> +<label x="63.5" y="45.72" size="1.27" layer="95" rot="R180"/> +</segment> +</net> +<net name="FPGA_JTAG_TMS" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="TMS_0"/> +<wire x1="-106.68" y1="114.3" x2="-71.12" y2="114.3" width="0.1524" layer="91"/> +<label x="-71.12" y="114.3" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="SV1" gate="1" pin="3"/> +<wire x1="78.74" y1="50.8" x2="68.58" y2="50.8" width="0.1524" layer="91"/> +<label x="63.5" y="50.8" size="1.27" layer="95" rot="R180"/> +<pinref part="R44" gate="G$1" pin="1"/> +<wire x1="68.58" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/> +<wire x1="68.58" y1="60.96" x2="68.58" y2="50.8" width="0.1524" layer="91"/> +<junction x="68.58" y="50.8"/> +</segment> +</net> +<net name="FPGA_PROGRAM_B" class="0"> +<segment> +<pinref part="R41" gate="G$1" pin="1"/> +<wire x1="0" y1="144.78" x2="0" y2="139.7" width="0.1524" layer="91"/> +<wire x1="0" y1="139.7" x2="35.56" y2="139.7" width="0.1524" layer="91"/> +<label x="35.56" y="139.7" size="1.778" layer="95" xref="yes"/> +</segment> +<segment> +<wire x1="-86.36" y1="134.62" x2="-68.58" y2="134.62" width="0.1524" layer="91"/> +<label x="-83.82" y="134.62" size="1.778" layer="95"/> +<pinref part="R63" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_DONE_INT" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="DONE_0"/> +<wire x1="-106.68" y1="139.7" x2="-71.12" y2="139.7" width="0.1524" layer="91"/> +<label x="-83.82" y="139.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="LED13" gate="G$1" pin="C"/> +<wire x1="-38.1" y1="30.48" x2="-38.1" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="27.94" x2="-63.5" y2="27.94" width="0.1524" layer="91"/> +<pinref part="R39" gate="G$1" pin="2"/> +<wire x1="-38.1" y1="27.94" x2="-30.48" y2="27.94" width="0.1524" layer="91"/> +<junction x="-38.1" y="27.94"/> +<label x="-63.5" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_M0" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="M0_0"/> +<wire x1="-106.68" y1="129.54" x2="-71.12" y2="129.54" width="0.1524" layer="91"/> +<label x="-83.82" y="129.54" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-93.98" y1="40.64" x2="-78.74" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="40.64" x2="-78.74" y2="45.72" width="0.1524" layer="91"/> +<label x="-91.44" y="41.91" size="1.778" layer="95"/> +<pinref part="R37" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_M1" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="M1_0"/> +<wire x1="-106.68" y1="127" x2="-71.12" y2="127" width="0.1524" layer="91"/> +<label x="-83.82" y="127" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-114.3" y1="40.64" x2="-99.06" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="40.64" x2="-99.06" y2="35.56" width="0.1524" layer="91"/> +<label x="-113.03" y="41.91" size="1.778" layer="95"/> +<pinref part="R36" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_INIT_B_INT" class="0"> +<segment> +<pinref part="R40" gate="G$1" pin="1"/> +<wire x1="-10.16" y1="144.78" x2="-10.16" y2="132.08" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="132.08" x2="-35.56" y2="132.08" width="0.1524" layer="91"/> +<pinref part="Q4" gate="G$1" pin="D"/> +<wire x1="-5.08" y1="132.08" x2="-10.16" y2="132.08" width="0.1524" layer="91"/> +<junction x="-10.16" y="132.08"/> +<label x="-35.56" y="132.08" size="1.778" layer="95"/> +</segment> +<segment> +<wire x1="-86.36" y1="137.16" x2="-68.58" y2="137.16" width="0.1524" layer="91"/> +<label x="-83.82" y="137.16" size="1.778" layer="95"/> +<pinref part="R62" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_INIT_B" class="0"> +<segment> +<label x="35.56" y="127" size="1.778" layer="95" xref="yes"/> +<pinref part="Q4" gate="G$1" pin="G"/> +<wire x1="5.08" y1="127" x2="10.16" y2="127" width="0.1524" layer="91"/> +<pinref part="R42" gate="G$1" pin="2"/> +<wire x1="10.16" y1="127" x2="10.16" y2="121.92" width="0.1524" layer="91"/> +<junction x="10.16" y="127"/> +<wire x1="10.16" y1="127" x2="35.56" y2="127" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$34" class="0"> +<segment> +<pinref part="R38" gate="G$1" pin="1"/> +<pinref part="LED13" gate="G$1" pin="A"/> +<wire x1="-38.1" y1="43.18" x2="-38.1" y2="38.1" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_DONE" class="0"> +<segment> +<pinref part="R39" gate="G$1" pin="1"/> +<wire x1="-20.32" y1="27.94" x2="-12.7" y2="27.94" width="0.1524" layer="91"/> +<label x="-12.7" y="27.94" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_SCLK" class="0"> +<segment> +<wire x1="-86.36" y1="132.08" x2="-68.58" y2="132.08" width="0.1524" layer="91"/> +<label x="-68.58" y="132.08" size="1.27" layer="95" xref="yes"/> +<pinref part="R71" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_INIT_B_INT1" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="INIT_B_0"/> +<wire x1="-106.68" y1="137.16" x2="-96.52" y2="137.16" width="0.1524" layer="91"/> +<pinref part="R62" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_PROGRAM_B1" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="PROGRAM_B_0"/> +<wire x1="-106.68" y1="134.62" x2="-96.52" y2="134.62" width="0.1524" layer="91"/> +<pinref part="R63" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_CFG_SCLK1" class="0"> +<segment> +<pinref part="U13" gate="B0" pin="CCLK_0"/> +<wire x1="-106.68" y1="132.08" x2="-96.52" y2="132.08" width="0.1524" layer="91"/> +<pinref part="R71" gate="G$1" pin="2"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA unused</description> +<plain> +<text x="22.86" y="78.74" size="1.778" layer="91">*) Temperature Sensor [NOT USED]</text> +<text x="-35.56" y="78.74" size="1.778" layer="91">*) XADC [NOT USED]</text> +<text x="-139.7" y="81.28" size="1.778" layer="91">*) Transceivers [NOT USED]</text> +<text x="55.88" y="-60.96" size="2.54" layer="94">FPGA unused</text> +</plain> +<instances> +<instance part="U13" gate="B216" x="-119.38" y="-12.7"/> +<instance part="U13" gate="BMGTAVCC" x="-119.38" y="60.96"/> +<instance part="U13" gate="BMGTAVTT" x="-119.38" y="35.56"/> +<instance part="U13" gate="BTDIODE" x="43.18" y="68.58"/> +<instance part="U13" gate="BXADC" x="-33.02" y="63.5"/> +<instance part="SUPPLY94" gate="GND" x="53.34" y="58.42"/> +<instance part="SUPPLY92" gate="GND" x="-22.86" y="48.26"/> +<instance part="SUPPLY93" gate="GND" x="-12.7" y="48.26"/> +<instance part="FRAME15" gate="G$1" x="-160.02" y="-81.28"/> +<instance part="C109" gate="G$1" x="-12.7" y="60.96"> +<attribute name="DIELECTRIC" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-12.7" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+59" gate="VCC" x="-12.7" y="76.2" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U13" gate="BXADC" pin="GNDADC_0"/> +<wire x1="-27.94" y1="55.88" x2="-22.86" y2="55.88" width="0.1524" layer="91"/> +<pinref part="SUPPLY92" gate="GND" pin="GND"/> +<wire x1="-22.86" y1="55.88" x2="-22.86" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U13" gate="BXADC" pin="VREFN_0"/> +<wire x1="-27.94" y1="58.42" x2="-22.86" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="58.42" x2="-22.86" y2="55.88" width="0.1524" layer="91"/> +<junction x="-22.86" y="55.88"/> +<pinref part="U13" gate="BXADC" pin="VREFP_0"/> +<wire x1="-27.94" y1="60.96" x2="-22.86" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-22.86" y1="60.96" x2="-22.86" y2="58.42" width="0.1524" layer="91"/> +<junction x="-22.86" y="58.42"/> +</segment> +<segment> +<pinref part="SUPPLY93" gate="GND" pin="GND"/> +<wire x1="-12.7" y1="55.88" x2="-12.7" y2="50.8" width="0.1524" layer="91"/> +<pinref part="C109" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="U13" gate="BTDIODE" pin="DXN_0"/> +<wire x1="48.26" y1="66.04" x2="53.34" y2="66.04" width="0.1524" layer="91"/> +<pinref part="SUPPLY94" gate="GND" pin="GND"/> +<wire x1="53.34" y1="66.04" x2="53.34" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U13" gate="BTDIODE" pin="DXP_0"/> +<wire x1="48.26" y1="68.58" x2="53.34" y2="68.58" width="0.1524" layer="91"/> +<wire x1="53.34" y1="68.58" x2="53.34" y2="66.04" width="0.1524" layer="91"/> +<junction x="53.34" y="66.04"/> +</segment> +</net> +<net name="FPGA_VCCAUX_1V8" class="0"> +<segment> +<pinref part="U13" gate="BXADC" pin="VCCADC_0"/> +<wire x1="-27.94" y1="68.58" x2="-12.7" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="68.58" x2="-12.7" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-12.7" y1="68.58" x2="-12.7" y2="73.66" width="0.1524" layer="91"/> +<junction x="-12.7" y="68.58"/> +<label x="-10.16" y="73.66" size="1.778" layer="95"/> +<pinref part="C109" gate="G$1" pin="1"/> +<pinref part="P+59" gate="VCC" pin="VCC"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA supporting components</description> +<plain> +<text x="38.1" y="58.42" size="1.778" layer="91">*) HOLD feature not used + +*) PROM is write-protected by default, to disable +write protection (such as during firmware update), +jumper must be inserted</text> +<text x="-20.32" y="-35.56" size="2.54" layer="91">FPGA clock</text> +<text x="38.1" y="76.2" size="2.54" layer="91">FPGA config memory, 128 Mbit</text> +<text x="-119.38" y="73.66" size="2.54" layer="91">SPI mux to let ARM override access to +FPGA config memory (to reprogram FPGA)</text> +<text x="-111.76" y="12.7" size="1.27" layer="91">Install this jumper to allow +ARM to configure the FPGA</text> +<text x="-96.52" y="43.18" size="1.27" layer="91">ARM access default +disabled through pull-up</text> +<text x="-96.52" y="-25.4" size="1.27" layer="91">FPGA access default +enabled through pull-down</text> +<text x="-111.76" y="-15.24" size="1.27" layer="91">Install this jumper to allow +ARM to configure the FPGA</text> +<text x="81.28" y="-68.58" size="1.778" layer="94">FPGA supporting components</text> +</plain> +<instances> +<instance part="IC3" gate="A" x="71.12" y="16.51"/> +<instance part="SUPPLY100" gate="GND" x="50.8" y="-5.08"/> +<instance part="R51" gate="G$1" x="50.8" y="33.02" rot="R90"> +<attribute name="TOLERANCE" x="50.8" y="33.02" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="JP9" gate="A" x="27.94" y="33.02"/> +<instance part="R50" gate="G$1" x="27.94" y="7.62" rot="R90"> +<attribute name="TOLERANCE" x="27.94" y="7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY99" gate="GND" x="27.94" y="-5.08"/> +<instance part="SUPPLY101" gate="GND" x="111.76" y="-5.08"/> +<instance part="Q5" gate="G$1" x="0" y="-58.42"/> +<instance part="C111" gate="G$1" x="-30.48" y="-60.96"> +<attribute name="DIELECTRIC" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="-60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY98" gate="GND" x="-15.24" y="-73.66"/> +<instance part="SUPPLY97" gate="GND" x="-30.48" y="-73.66"/> +<instance part="R49" gate="G$1" x="0" y="-43.18" rot="R180"/> +<instance part="C112" gate="G$1" x="111.76" y="10.16" smashed="yes"> +<attribute name="DIELECTRIC" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="111.76" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="103.124" y="5.461" size="1.778" layer="95"/> +<attribute name="VALUE" x="100.584" y="2.921" size="1.778" layer="96"/> +</instance> +<instance part="P+64" gate="VCC" x="27.94" y="53.34" smashed="yes"/> +<instance part="P+63" gate="VCC" x="-30.48" y="-40.64" smashed="yes"/> +<instance part="JP7" gate="A" x="-73.66" y="17.78" rot="R90"/> +<instance part="IC2" gate="A" x="-45.72" y="25.4"/> +<instance part="IC2" gate="B" x="-45.72" y="-2.54"/> +<instance part="IC2" gate="P" x="-109.22" y="43.18"/> +<instance part="P+60" gate="VCC" x="-109.22" y="58.42" smashed="yes"/> +<instance part="C110" gate="G$1" x="-119.38" y="43.18" smashed="yes"> +<attribute name="NAME" x="-117.856" y="43.561" size="1.778" layer="95"/> +<attribute name="VALUE" x="-117.856" y="38.481" size="1.778" layer="96"/> +<attribute name="DIELECTRIC" x="-119.38" y="43.18" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-119.38" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="R48" gate="G$1" x="-30.48" y="40.64" rot="R90"> +<attribute name="TOLERANCE" x="-30.48" y="40.64" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="P+62" gate="VCC" x="-30.48" y="53.34" smashed="yes"/> +<instance part="SUPPLY95" gate="GND" x="-109.22" y="27.94"/> +<instance part="R46" gate="G$1" x="-66.04" y="40.64" rot="R90"> +<attribute name="TOLERANCE" x="-66.04" y="40.64" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="P+61" gate="VCC" x="-66.04" y="53.34" smashed="yes"/> +<instance part="R47" gate="G$1" x="-66.04" y="-20.32" rot="R270"> +<attribute name="TOLERANCE" x="-66.04" y="-20.32" size="1.778" layer="96" rot="R270" display="off"/> +</instance> +<instance part="SUPPLY96" gate="GND" x="-66.04" y="-30.48"/> +<instance part="JP8" gate="A" x="-73.66" y="-10.16" rot="R90"/> +<instance part="FRAME16" gate="G$1" x="-134.62" y="-88.9"/> +<instance part="R4" gate="G$1" x="22.86" y="-58.42" rot="R180"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY100" gate="GND" pin="GND"/> +<wire x1="50.8" y1="-2.54" x2="50.8" y2="15.24" width="0.1524" layer="91"/> +<pinref part="IC3" gate="A" pin="VSS"/> +<wire x1="50.8" y1="15.24" x2="53.34" y2="15.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY99" gate="GND" pin="GND"/> +<pinref part="R50" gate="G$1" pin="1"/> +<wire x1="27.94" y1="-2.54" x2="27.94" y2="2.54" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="SUPPLY101" gate="GND" pin="GND"/> +<wire x1="111.76" y1="-2.54" x2="111.76" y2="5.08" width="0.1524" layer="91"/> +<pinref part="C112" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY98" gate="GND" pin="GND"/> +<wire x1="-15.24" y1="-71.12" x2="-15.24" y2="-63.5" width="0.1524" layer="91"/> +<pinref part="Q5" gate="G$1" pin="GND"/> +<wire x1="-15.24" y1="-63.5" x2="-12.7" y2="-63.5" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C111" gate="G$1" pin="2"/> +<pinref part="SUPPLY97" gate="GND" pin="GND"/> +<wire x1="-30.48" y1="-66.04" x2="-30.48" y2="-71.12" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC2" gate="P" pin="GND"/> +<wire x1="-109.22" y1="30.48" x2="-109.22" y2="33.02" width="0.1524" layer="91"/> +<pinref part="C110" gate="G$1" pin="2"/> +<wire x1="-109.22" y1="33.02" x2="-109.22" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="38.1" x2="-119.38" y2="33.02" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="33.02" x2="-109.22" y2="33.02" width="0.1524" layer="91"/> +<junction x="-109.22" y="33.02"/> +<pinref part="SUPPLY95" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="R47" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="-25.4" x2="-66.04" y2="-27.94" width="0.1524" layer="91"/> +<pinref part="SUPPLY96" gate="GND" pin="GND"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="R51" gate="G$1" pin="2"/> +<wire x1="50.8" y1="38.1" x2="50.8" y2="43.18" width="0.1524" layer="91"/> +<wire x1="50.8" y1="43.18" x2="27.94" y2="43.18" width="0.1524" layer="91"/> +<label x="30.48" y="50.8" size="1.778" layer="95"/> +<pinref part="IC3" gate="A" pin="VCC"/> +<wire x1="27.94" y1="43.18" x2="27.94" y2="50.8" width="0.1524" layer="91"/> +<wire x1="90.17" y1="22.86" x2="96.52" y2="22.86" width="0.1524" layer="91"/> +<wire x1="96.52" y1="22.86" x2="96.52" y2="43.18" width="0.1524" layer="91"/> +<wire x1="96.52" y1="43.18" x2="50.8" y2="43.18" width="0.1524" layer="91"/> +<junction x="50.8" y="43.18"/> +<pinref part="IC3" gate="A" pin="!HOLD!/DQ3"/> +<wire x1="90.17" y1="20.32" x2="96.52" y2="20.32" width="0.1524" layer="91"/> +<wire x1="96.52" y1="20.32" x2="96.52" y2="22.86" width="0.1524" layer="91"/> +<junction x="96.52" y="22.86"/> +<pinref part="JP9" gate="A" pin="2"/> +<wire x1="27.94" y1="40.64" x2="27.94" y2="43.18" width="0.1524" layer="91"/> +<junction x="27.94" y="43.18"/> +<wire x1="111.76" y1="20.32" x2="111.76" y2="12.7" width="0.1524" layer="91"/> +<wire x1="96.52" y1="20.32" x2="111.76" y2="20.32" width="0.1524" layer="91"/> +<junction x="96.52" y="20.32"/> +<pinref part="C112" gate="G$1" pin="1"/> +<pinref part="P+64" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="C111" gate="G$1" pin="1"/> +<wire x1="-30.48" y1="-58.42" x2="-30.48" y2="-53.34" width="0.1524" layer="91"/> +<pinref part="Q5" gate="G$1" pin="VCC"/> +<wire x1="-30.48" y1="-53.34" x2="-15.24" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-53.34" x2="-12.7" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="-53.34" x2="-30.48" y2="-43.18" width="0.1524" layer="91"/> +<junction x="-30.48" y="-53.34"/> +<label x="-45.72" y="-48.26" size="1.778" layer="95"/> +<pinref part="R49" gate="G$1" pin="2"/> +<wire x1="-5.08" y1="-43.18" x2="-15.24" y2="-43.18" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="-43.18" x2="-15.24" y2="-53.34" width="0.1524" layer="91"/> +<junction x="-15.24" y="-53.34"/> +<pinref part="P+63" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="IC2" gate="P" pin="VCC"/> +<pinref part="P+60" gate="VCC" pin="VCC"/> +<wire x1="-109.22" y1="50.8" x2="-109.22" y2="53.34" width="0.1524" layer="91"/> +<pinref part="C110" gate="G$1" pin="1"/> +<wire x1="-109.22" y1="53.34" x2="-109.22" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="45.72" x2="-119.38" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-119.38" y1="53.34" x2="-109.22" y2="53.34" width="0.1524" layer="91"/> +<junction x="-109.22" y="53.34"/> +<label x="-106.68" y="58.42" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+62" gate="VCC" pin="VCC"/> +<pinref part="R48" gate="G$1" pin="2"/> +<wire x1="-30.48" y1="50.8" x2="-30.48" y2="45.72" width="0.1524" layer="91"/> +<label x="-27.94" y="53.34" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="P+61" gate="VCC" pin="VCC"/> +<pinref part="R46" gate="G$1" pin="2"/> +<wire x1="-66.04" y1="50.8" x2="-66.04" y2="45.72" width="0.1524" layer="91"/> +<label x="-63.5" y="53.34" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_SCLK" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="C"/> +<wire x1="90.17" y1="17.78" x2="93.98" y2="17.78" width="0.1524" layer="91"/> +<label x="93.98" y="17.78" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="Y2"/> +<wire x1="-33.02" y1="27.94" x2="-27.94" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="27.94" x2="-27.94" y2="0" width="0.1524" layer="91"/> +<pinref part="IC2" gate="B" pin="Y2"/> +<wire x1="-27.94" y1="0" x2="-33.02" y2="0" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="27.94" x2="-20.32" y2="27.94" width="0.1524" layer="91"/> +<junction x="-27.94" y="27.94"/> +<label x="-20.32" y="27.94" size="1.27" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_MOSI" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="DQ0"/> +<wire x1="90.17" y1="15.24" x2="93.98" y2="15.24" width="0.1524" layer="91"/> +<label x="93.98" y="15.24" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="B" pin="Y3"/> +<wire x1="-33.02" y1="-2.54" x2="-25.4" y2="-2.54" width="0.1524" layer="91"/> +<wire x1="-25.4" y1="-2.54" x2="-25.4" y2="25.4" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="Y3"/> +<wire x1="-33.02" y1="25.4" x2="-25.4" y2="25.4" width="0.1524" layer="91"/> +<junction x="-25.4" y="25.4"/> +<wire x1="-25.4" y1="25.4" x2="-20.32" y2="25.4" width="0.1524" layer="91"/> +<label x="-20.32" y="25.4" size="1.27" layer="95"/> +</segment> +</net> +<net name="FPGA_PROM_CS_N" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="!S"/> +<wire x1="53.34" y1="22.86" x2="50.8" y2="22.86" width="0.1524" layer="91"/> +<pinref part="R51" gate="G$1" pin="1"/> +<wire x1="50.8" y1="22.86" x2="50.8" y2="27.94" width="0.1524" layer="91"/> +<label x="33.02" y="22.86" size="1.27" layer="95"/> +<wire x1="50.8" y1="22.86" x2="33.02" y2="22.86" width="0.1524" layer="91"/> +<junction x="50.8" y="22.86"/> +</segment> +<segment> +<pinref part="IC2" gate="B" pin="Y1"/> +<wire x1="-33.02" y1="2.54" x2="-30.48" y2="2.54" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="2.54" x2="-30.48" y2="30.48" width="0.1524" layer="91"/> +<pinref part="IC2" gate="A" pin="Y1"/> +<wire x1="-30.48" y1="30.48" x2="-33.02" y2="30.48" width="0.1524" layer="91"/> +<junction x="-30.48" y="30.48"/> +<label x="-20.32" y="30.48" size="1.27" layer="95"/> +<pinref part="R48" gate="G$1" pin="1"/> +<wire x1="-30.48" y1="30.48" x2="-20.32" y2="30.48" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="35.56" x2="-30.48" y2="30.48" width="0.1524" layer="91"/> +<junction x="-30.48" y="30.48"/> +</segment> +</net> +<net name="FPGA_PROM_MISO" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="DQ1"/> +<wire x1="53.34" y1="20.32" x2="33.02" y2="20.32" width="0.1524" layer="91"/> +<label x="33.02" y="20.32" size="1.27" layer="95"/> +</segment> +<segment> +<pinref part="IC2" gate="A" pin="A4"/> +<wire x1="-58.42" y1="22.86" x2="-60.96" y2="22.86" width="0.1524" layer="91"/> +<pinref part="IC2" gate="B" pin="A4"/> +<wire x1="-60.96" y1="22.86" x2="-71.12" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-58.42" y1="-5.08" x2="-60.96" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="-5.08" x2="-60.96" y2="22.86" width="0.1524" layer="91"/> +<junction x="-60.96" y="22.86"/> +<label x="-71.12" y="22.86" size="1.27" layer="95" rot="R180"/> +</segment> +</net> +<net name="FPGA_PROM_W_N" class="0"> +<segment> +<pinref part="IC3" gate="A" pin="!W!/VPP/DQ2"/> +<wire x1="53.34" y1="17.78" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R50" gate="G$1" pin="2"/> +<wire x1="27.94" y1="12.7" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +<junction x="27.94" y="17.78"/> +<pinref part="JP9" gate="A" pin="1"/> +<wire x1="27.94" y1="25.4" x2="27.94" y2="17.78" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_GCLK" class="0"> +<segment> +<wire x1="27.94" y1="-58.42" x2="35.56" y2="-58.42" width="0.1524" layer="91"/> +<label x="35.56" y="-58.42" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="N$33" class="0"> +<segment> +<pinref part="Q5" gate="G$1" pin="OE"/> +<wire x1="12.7" y1="-53.34" x2="15.24" y2="-53.34" width="0.1524" layer="91"/> +<wire x1="15.24" y1="-53.34" x2="15.24" y2="-43.18" width="0.1524" layer="91"/> +<pinref part="R49" gate="G$1" pin="1"/> +<wire x1="15.24" y1="-43.18" x2="5.08" y2="-43.18" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_CFG_SCLK" class="0"> +<segment> +<pinref part="IC2" gate="B" pin="A2"/> +<wire x1="-58.42" y1="0" x2="-71.12" y2="0" width="0.1524" layer="91"/> +<label x="-71.12" y="0" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_MOSI" class="0"> +<segment> +<pinref part="IC2" gate="B" pin="A3"/> +<wire x1="-58.42" y1="-2.54" x2="-71.12" y2="-2.54" width="0.1524" layer="91"/> +<label x="-71.12" y="-2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_CS_N" class="0"> +<segment> +<pinref part="IC2" gate="B" pin="A1"/> +<wire x1="-58.42" y1="2.54" x2="-71.12" y2="2.54" width="0.1524" layer="91"/> +<label x="-71.12" y="2.54" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_MISO" class="0"> +<segment> +<pinref part="IC2" gate="B" pin="Y4"/> +<wire x1="-33.02" y1="-5.08" x2="-20.32" y2="-5.08" width="0.1524" layer="91"/> +<label x="-20.32" y="-5.08" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_CS_N" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="A1"/> +<wire x1="-58.42" y1="30.48" x2="-71.12" y2="30.48" width="0.1524" layer="91"/> +<label x="-71.12" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_MOSI" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="A3"/> +<wire x1="-58.42" y1="25.4" x2="-71.12" y2="25.4" width="0.1524" layer="91"/> +<label x="-71.12" y="25.4" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_MISO" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="Y4"/> +<wire x1="-33.02" y1="22.86" x2="-20.32" y2="22.86" width="0.1524" layer="91"/> +<label x="-20.32" y="22.86" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="ARM_FPGA_CFG_SCLK" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="A2"/> +<wire x1="-58.42" y1="27.94" x2="-71.12" y2="27.94" width="0.1524" layer="91"/> +<label x="-71.12" y="27.94" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_ARM_ENA" class="0"> +<segment> +<pinref part="JP7" gate="A" pin="2"/> +<wire x1="-81.28" y1="17.78" x2="-83.82" y2="17.78" width="0.1524" layer="91"/> +<label x="-83.82" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="SPI_A_TRISTATE" class="0"> +<segment> +<pinref part="IC2" gate="A" pin="G"/> +<wire x1="-58.42" y1="17.78" x2="-66.04" y2="17.78" width="0.1524" layer="91"/> +<pinref part="R46" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="35.56" x2="-66.04" y2="17.78" width="0.1524" layer="91"/> +<junction x="-66.04" y="17.78"/> +<pinref part="JP7" gate="A" pin="1"/> +</segment> +</net> +<net name="SPI_B_TRISTATE" class="0"> +<segment> +<pinref part="IC2" gate="B" pin="G"/> +<wire x1="-58.42" y1="-10.16" x2="-66.04" y2="-10.16" width="0.1524" layer="91"/> +<pinref part="R47" gate="G$1" pin="1"/> +<wire x1="-66.04" y1="-10.16" x2="-66.04" y2="-15.24" width="0.1524" layer="91"/> +<junction x="-66.04" y="-10.16"/> +<pinref part="JP8" gate="A" pin="1"/> +</segment> +</net> +<net name="FPGA_CFG_CTRL_FPGA_DIS" class="0"> +<segment> +<pinref part="JP8" gate="A" pin="2"/> +<wire x1="-81.28" y1="-10.16" x2="-83.82" y2="-10.16" width="0.1524" layer="91"/> +<label x="-83.82" y="-10.16" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="N$3" class="0"> +<segment> +<pinref part="Q5" gate="G$1" pin="FO"/> +<wire x1="12.7" y1="-58.42" x2="17.78" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="R4" gate="G$1" pin="2"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA unused banks</description> +<plain> +<text x="-119.38" y="83.82" size="1.778" layer="91">*) Middle Right Bank</text> +<text x="-35.56" y="86.36" size="1.778" layer="91">*) Upper Left Bank</text> +<text x="-96.52" y="66.04" size="1.778" layer="91">*) Completely unused banks +still must be powered</text> +<text x="-7.62" y="68.58" size="1.778" layer="91">*) Completely unused banks +still must be powered</text> +<text x="68.58" y="-60.96" size="2.54" layer="94">FPGA unused banks</text> +</plain> +<instances> +<instance part="U13" gate="B15" x="-109.22" y="5.08"/> +<instance part="U13" gate="B35" x="-20.32" y="7.62"/> +<instance part="FRAME17" gate="G$1" x="-147.32" y="-81.28"/> +<instance part="P+65" gate="VCC" x="-99.06" y="81.28" smashed="yes"/> +<instance part="P+66" gate="VCC" x="-10.16" y="83.82" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="-104.14" y1="73.66" x2="-99.06" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="73.66" x2="-99.06" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="71.12" x2="-99.06" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="68.58" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="66.04" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<junction x="-99.06" y="66.04"/> +<wire x1="-104.14" y1="68.58" x2="-99.06" y2="68.58" width="0.1524" layer="91"/> +<junction x="-99.06" y="68.58"/> +<wire x1="-104.14" y1="71.12" x2="-99.06" y2="71.12" width="0.1524" layer="91"/> +<junction x="-99.06" y="71.12"/> +<junction x="-99.06" y="73.66"/> +<wire x1="-99.06" y1="73.66" x2="-99.06" y2="78.74" width="0.1524" layer="91"/> +<label x="-96.52" y="73.66" size="1.778" layer="95"/> +<pinref part="U13" gate="B15" pin="VCCO_15@5"/> +<wire x1="-104.14" y1="60.96" x2="-99.06" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-99.06" y1="60.96" x2="-99.06" y2="63.5" width="0.1524" layer="91"/> +<pinref part="U13" gate="B15" pin="VCCO_15@4"/> +<wire x1="-99.06" y1="63.5" x2="-99.06" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="63.5" x2="-99.06" y2="63.5" width="0.1524" layer="91"/> +<junction x="-99.06" y="63.5"/> +<pinref part="U13" gate="B15" pin="VCCO_15@0"/> +<pinref part="U13" gate="B15" pin="VCCO_15@1"/> +<pinref part="U13" gate="B15" pin="VCCO_15@2"/> +<pinref part="U13" gate="B15" pin="VCCO_15@3"/> +<pinref part="P+65" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="-15.24" y1="76.2" x2="-10.16" y2="76.2" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="76.2" x2="-10.16" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="73.66" x2="-10.16" y2="71.12" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="71.12" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="68.58" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<junction x="-10.16" y="68.58"/> +<wire x1="-15.24" y1="71.12" x2="-10.16" y2="71.12" width="0.1524" layer="91"/> +<junction x="-10.16" y="71.12"/> +<wire x1="-15.24" y1="73.66" x2="-10.16" y2="73.66" width="0.1524" layer="91"/> +<junction x="-10.16" y="73.66"/> +<junction x="-10.16" y="76.2"/> +<wire x1="-10.16" y1="76.2" x2="-10.16" y2="81.28" width="0.1524" layer="91"/> +<label x="-7.62" y="76.2" size="1.778" layer="95"/> +<wire x1="-15.24" y1="63.5" x2="-10.16" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="63.5" x2="-10.16" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="66.04" x2="-10.16" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="66.04" x2="-10.16" y2="66.04" width="0.1524" layer="91"/> +<junction x="-10.16" y="66.04"/> +<pinref part="U13" gate="B35" pin="VCCO_35@0"/> +<pinref part="U13" gate="B35" pin="VCCO_35@1"/> +<pinref part="U13" gate="B35" pin="VCCO_35@2"/> +<pinref part="U13" gate="B35" pin="VCCO_35@3"/> +<pinref part="U13" gate="B35" pin="VCCO_35@4"/> +<pinref part="U13" gate="B35" pin="VCCO_35@5"/> +<pinref part="P+66" gate="VCC" pin="VCC"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA FMC interface</description> +<plain> +<text x="21.59" y="63.5" size="1.778" layer="91">*) Bottom Bank</text> +<text x="-106.68" y="73.66" size="1.778" layer="91">*) Lower Left Bank</text> +<text x="72.39" y="38.1" size="1.778" layer="91"><-- FMC_A[...] signals can be swapped</text> +<text x="72.39" y="-36.83" size="1.778" layer="91"><-- FMC_CLK signal _MUST_ go +into either W11 or V13 (i.e. into +one of the two positive (master) +sides of the two available +MRCC differential pairs)</text> +<text x="-53.34" y="45.72" size="1.778" layer="91"><-- FMC_D[...] signals can be swapped</text> +<text x="-58.42" y="-43.18" size="1.778" layer="91"><-- FMC_* control signals + can be swapped</text> +<text x="91.44" y="-73.66" size="2.54" layer="94">FPGA FMC interface</text> +</plain> +<instances> +<instance part="U13" gate="B13" x="34.29" y="2.54"/> +<instance part="U13" gate="B34" x="-91.44" y="-7.62"/> +<instance part="FRAME18" gate="G$1" x="-124.46" y="-93.98"/> +<instance part="P+67" gate="VCC" x="-81.28" y="68.58" smashed="yes"/> +<instance part="P+68" gate="VCC" x="45.72" y="60.96" smashed="yes"/> +</instances> +<busses> +<bus name="FMC_A[0..25]"> +<segment> +<wire x1="69.85" y1="43.18" x2="85.09" y2="43.18" width="0.762" layer="92"/> +<wire x1="69.85" y1="43.18" x2="69.85" y2="-27.94" width="0.762" layer="92"/> +<label x="69.85" y="45.72" size="1.778" layer="95"/> +</segment> +</bus> +<bus name="FMC_D[0..31]"> +<segment> +<wire x1="-55.88" y1="-33.02" x2="-55.88" y2="50.8" width="0.762" layer="92"/> +<wire x1="-55.88" y1="50.8" x2="-40.64" y2="50.8" width="0.762" layer="92"/> +<label x="-55.88" y="53.34" size="1.778" layer="95"/> +</segment> +</bus> +</busses> +<nets> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="VCCO_34@5"/> +<wire x1="-86.36" y1="48.26" x2="-81.28" y2="48.26" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="48.26" x2="-81.28" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U13" gate="B34" pin="VCCO_34@0"/> +<wire x1="-81.28" y1="50.8" x2="-81.28" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="53.34" x2="-81.28" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="55.88" x2="-81.28" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="58.42" x2="-81.28" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-81.28" y1="60.96" x2="-86.36" y2="60.96" width="0.1524" layer="91"/> +<pinref part="U13" gate="B34" pin="VCCO_34@1"/> +<wire x1="-86.36" y1="58.42" x2="-81.28" y2="58.42" width="0.1524" layer="91"/> +<junction x="-81.28" y="58.42"/> +<pinref part="U13" gate="B34" pin="VCCO_34@2"/> +<wire x1="-86.36" y1="55.88" x2="-81.28" y2="55.88" width="0.1524" layer="91"/> +<junction x="-81.28" y="55.88"/> +<pinref part="U13" gate="B34" pin="VCCO_34@3"/> +<wire x1="-86.36" y1="53.34" x2="-81.28" y2="53.34" width="0.1524" layer="91"/> +<junction x="-81.28" y="53.34"/> +<pinref part="U13" gate="B34" pin="VCCO_34@4"/> +<wire x1="-86.36" y1="50.8" x2="-81.28" y2="50.8" width="0.1524" layer="91"/> +<junction x="-81.28" y="50.8"/> +<junction x="-81.28" y="60.96"/> +<wire x1="-81.28" y1="60.96" x2="-81.28" y2="66.04" width="0.1524" layer="91"/> +<label x="-78.74" y="66.04" size="1.778" layer="95"/> +<pinref part="P+67" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="39.37" y1="50.8" x2="45.72" y2="50.8" width="0.1524" layer="91"/> +<label x="49.53" y="58.42" size="1.778" layer="95"/> +<pinref part="U13" gate="B13" pin="VCCO_13@0"/> +<pinref part="U13" gate="B13" pin="VCCO_13@1"/> +<wire x1="45.72" y1="50.8" x2="45.72" y2="58.42" width="0.1524" layer="91"/> +<wire x1="39.37" y1="48.26" x2="45.72" y2="48.26" width="0.1524" layer="91"/> +<wire x1="45.72" y1="48.26" x2="45.72" y2="50.8" width="0.1524" layer="91"/> +<junction x="45.72" y="50.8"/> +<pinref part="U13" gate="B13" pin="VCCO_13@2"/> +<wire x1="39.37" y1="45.72" x2="45.72" y2="45.72" width="0.1524" layer="91"/> +<wire x1="45.72" y1="45.72" x2="45.72" y2="48.26" width="0.1524" layer="91"/> +<junction x="45.72" y="48.26"/> +<pinref part="U13" gate="B13" pin="VCCO_13@3"/> +<wire x1="39.37" y1="43.18" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<wire x1="45.72" y1="43.18" x2="45.72" y2="45.72" width="0.1524" layer="91"/> +<junction x="45.72" y="45.72"/> +<pinref part="U13" gate="B13" pin="VCCO_13@4"/> +<wire x1="39.37" y1="40.64" x2="45.72" y2="40.64" width="0.1524" layer="91"/> +<wire x1="45.72" y1="40.64" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<junction x="45.72" y="43.18"/> +<pinref part="P+68" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FMC_CLK" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L12P_T1_MRCC_13"/> +<wire x1="39.37" y1="-20.32" x2="73.66" y2="-20.32" width="0.1524" layer="91"/> +<label x="73.66" y="-20.32" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_D0" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_0_34"/> +<wire x1="-55.88" y1="45.72" x2="-86.36" y2="45.72" width="0.1524" layer="91"/> +<label x="-73.66" y="45.72" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D1" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L1P_T0_34"/> +<wire x1="-55.88" y1="43.18" x2="-86.36" y2="43.18" width="0.1524" layer="91"/> +<label x="-73.66" y="43.18" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D2" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L1N_T0_34"/> +<wire x1="-55.88" y1="40.64" x2="-86.36" y2="40.64" width="0.1524" layer="91"/> +<label x="-73.66" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D3" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L2P_T0_34"/> +<wire x1="-55.88" y1="38.1" x2="-86.36" y2="38.1" width="0.1524" layer="91"/> +<label x="-73.66" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D4" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L2N_T0_34"/> +<wire x1="-55.88" y1="35.56" x2="-86.36" y2="35.56" width="0.1524" layer="91"/> +<label x="-73.66" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D5" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L3P_T0_DQS_34"/> +<wire x1="-55.88" y1="33.02" x2="-86.36" y2="33.02" width="0.1524" layer="91"/> +<label x="-73.66" y="33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D6" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L3N_T0_DQS_34"/> +<wire x1="-55.88" y1="30.48" x2="-86.36" y2="30.48" width="0.1524" layer="91"/> +<label x="-73.66" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D7" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L4P_T0_34"/> +<wire x1="-55.88" y1="27.94" x2="-86.36" y2="27.94" width="0.1524" layer="91"/> +<label x="-73.66" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D8" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L4N_T0_34"/> +<wire x1="-55.88" y1="25.4" x2="-86.36" y2="25.4" width="0.1524" layer="91"/> +<label x="-73.66" y="25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D9" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L5P_T0_34"/> +<wire x1="-55.88" y1="22.86" x2="-86.36" y2="22.86" width="0.1524" layer="91"/> +<label x="-73.66" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D10" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L5N_T0_34"/> +<wire x1="-55.88" y1="20.32" x2="-86.36" y2="20.32" width="0.1524" layer="91"/> +<label x="-73.66" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D11" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L6P_T0_34"/> +<wire x1="-55.88" y1="17.78" x2="-86.36" y2="17.78" width="0.1524" layer="91"/> +<label x="-73.66" y="17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D12" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L6N_T0_VREF_34"/> +<wire x1="-55.88" y1="15.24" x2="-86.36" y2="15.24" width="0.1524" layer="91"/> +<label x="-73.66" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D13" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L7P_T1_34"/> +<wire x1="-55.88" y1="12.7" x2="-86.36" y2="12.7" width="0.1524" layer="91"/> +<label x="-73.66" y="12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D14" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L7N_T1_34"/> +<wire x1="-55.88" y1="10.16" x2="-86.36" y2="10.16" width="0.1524" layer="91"/> +<label x="-73.66" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D15" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L8P_T1_34"/> +<wire x1="-55.88" y1="7.62" x2="-86.36" y2="7.62" width="0.1524" layer="91"/> +<label x="-73.66" y="7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D16" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L8N_T1_34"/> +<wire x1="-55.88" y1="5.08" x2="-86.36" y2="5.08" width="0.1524" layer="91"/> +<label x="-73.66" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D17" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L9P_T1_DQS_34"/> +<wire x1="-55.88" y1="2.54" x2="-86.36" y2="2.54" width="0.1524" layer="91"/> +<label x="-73.66" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D18" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L9N_T1_DQS_34"/> +<wire x1="-55.88" y1="0" x2="-86.36" y2="0" width="0.1524" layer="91"/> +<label x="-73.66" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D19" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L10P_T1_34"/> +<wire x1="-55.88" y1="-2.54" x2="-86.36" y2="-2.54" width="0.1524" layer="91"/> +<label x="-73.66" y="-2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D20" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L10N_T1_34"/> +<wire x1="-55.88" y1="-5.08" x2="-86.36" y2="-5.08" width="0.1524" layer="91"/> +<label x="-73.66" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D21" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L11P_T1_SRCC_34"/> +<wire x1="-55.88" y1="-7.62" x2="-86.36" y2="-7.62" width="0.1524" layer="91"/> +<label x="-73.66" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D22" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L11N_T1_SRCC_34"/> +<wire x1="-55.88" y1="-10.16" x2="-86.36" y2="-10.16" width="0.1524" layer="91"/> +<label x="-73.66" y="-10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D23" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L12P_T1_MRCC_34"/> +<wire x1="-55.88" y1="-12.7" x2="-86.36" y2="-12.7" width="0.1524" layer="91"/> +<label x="-73.66" y="-12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D24" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L12N_T1_MRCC_34"/> +<wire x1="-55.88" y1="-15.24" x2="-86.36" y2="-15.24" width="0.1524" layer="91"/> +<label x="-73.66" y="-15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D25" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L13P_T2_MRCC_34"/> +<wire x1="-55.88" y1="-17.78" x2="-86.36" y2="-17.78" width="0.1524" layer="91"/> +<label x="-73.66" y="-17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D26" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L13N_T2_MRCC_34"/> +<wire x1="-55.88" y1="-20.32" x2="-86.36" y2="-20.32" width="0.1524" layer="91"/> +<label x="-73.66" y="-20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D27" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L14P_T2_SRCC_34"/> +<wire x1="-55.88" y1="-22.86" x2="-86.36" y2="-22.86" width="0.1524" layer="91"/> +<label x="-73.66" y="-22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D28" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L14N_T2_SRCC_34"/> +<wire x1="-55.88" y1="-25.4" x2="-86.36" y2="-25.4" width="0.1524" layer="91"/> +<label x="-73.66" y="-25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D29" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L15P_T2_DQS_34"/> +<wire x1="-55.88" y1="-27.94" x2="-86.36" y2="-27.94" width="0.1524" layer="91"/> +<label x="-73.66" y="-27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D30" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L15N_T2_DQS_34"/> +<wire x1="-55.88" y1="-30.48" x2="-86.36" y2="-30.48" width="0.1524" layer="91"/> +<label x="-73.66" y="-30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_D31" class="2"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L16P_T2_34"/> +<wire x1="-55.88" y1="-33.02" x2="-86.36" y2="-33.02" width="0.1524" layer="91"/> +<label x="-73.66" y="-33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_NE1" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L16N_T2_34"/> +<wire x1="-81.28" y1="-35.56" x2="-86.36" y2="-35.56" width="0.1524" layer="91"/> +<label x="-81.28" y="-35.56" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NL" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L17P_T2_34"/> +<wire x1="-81.28" y1="-38.1" x2="-86.36" y2="-38.1" width="0.1524" layer="91"/> +<label x="-81.28" y="-38.1" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NOE" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L17N_T2_34"/> +<wire x1="-81.28" y1="-40.64" x2="-86.36" y2="-40.64" width="0.1524" layer="91"/> +<label x="-81.28" y="-40.64" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NWAIT" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L18P_T2_34"/> +<wire x1="-81.28" y1="-43.18" x2="-86.36" y2="-43.18" width="0.1524" layer="91"/> +<label x="-81.28" y="-43.18" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_NWE" class="0"> +<segment> +<pinref part="U13" gate="B34" pin="IO_L18N_T2_34"/> +<wire x1="-81.28" y1="-45.72" x2="-86.36" y2="-45.72" width="0.1524" layer="91"/> +<label x="-81.28" y="-45.72" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FMC_A0" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_0_13"/> +<wire x1="69.85" y1="38.1" x2="39.37" y2="38.1" width="0.1524" layer="91"/> +<label x="50.8" y="38.1" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A1" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L1P_T0_13"/> +<wire x1="69.85" y1="35.56" x2="39.37" y2="35.56" width="0.1524" layer="91"/> +<label x="50.8" y="35.56" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A2" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L1N_T0_13"/> +<wire x1="69.85" y1="33.02" x2="39.37" y2="33.02" width="0.1524" layer="91"/> +<label x="50.8" y="33.02" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A3" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L2P_T0_13"/> +<wire x1="69.85" y1="30.48" x2="39.37" y2="30.48" width="0.1524" layer="91"/> +<label x="50.8" y="30.48" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A4" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L2N_T0_13"/> +<wire x1="69.85" y1="27.94" x2="39.37" y2="27.94" width="0.1524" layer="91"/> +<label x="50.8" y="27.94" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A5" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L3P_T0_DQS_13"/> +<wire x1="69.85" y1="25.4" x2="39.37" y2="25.4" width="0.1524" layer="91"/> +<label x="50.8" y="25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A6" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L3N_T0_DQS_13"/> +<wire x1="69.85" y1="22.86" x2="39.37" y2="22.86" width="0.1524" layer="91"/> +<label x="50.8" y="22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A7" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L4P_T0_13"/> +<wire x1="69.85" y1="20.32" x2="39.37" y2="20.32" width="0.1524" layer="91"/> +<label x="50.8" y="20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A8" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L4N_T0_13"/> +<wire x1="69.85" y1="17.78" x2="39.37" y2="17.78" width="0.1524" layer="91"/> +<label x="50.8" y="17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A9" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L5P_T0_13"/> +<wire x1="69.85" y1="15.24" x2="39.37" y2="15.24" width="0.1524" layer="91"/> +<label x="50.8" y="15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A10" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L5N_T0_13"/> +<wire x1="69.85" y1="12.7" x2="39.37" y2="12.7" width="0.1524" layer="91"/> +<label x="50.8" y="12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A11" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L6P_T0_13"/> +<wire x1="69.85" y1="10.16" x2="39.37" y2="10.16" width="0.1524" layer="91"/> +<label x="50.8" y="10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A12" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L6N_T0_VREF_13"/> +<wire x1="69.85" y1="7.62" x2="39.37" y2="7.62" width="0.1524" layer="91"/> +<label x="50.8" y="7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A13" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L7P_T1_13"/> +<wire x1="69.85" y1="5.08" x2="39.37" y2="5.08" width="0.1524" layer="91"/> +<label x="50.8" y="5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A14" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L7N_T1_13"/> +<wire x1="69.85" y1="2.54" x2="39.37" y2="2.54" width="0.1524" layer="91"/> +<label x="50.8" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A15" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L8P_T1_13"/> +<wire x1="69.85" y1="0" x2="39.37" y2="0" width="0.1524" layer="91"/> +<label x="50.8" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A16" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L8N_T1_13"/> +<wire x1="69.85" y1="-2.54" x2="39.37" y2="-2.54" width="0.1524" layer="91"/> +<label x="50.8" y="-2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A17" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L9P_T1_DQS_13"/> +<wire x1="69.85" y1="-5.08" x2="39.37" y2="-5.08" width="0.1524" layer="91"/> +<label x="50.8" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A18" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L9N_T1_DQS_13"/> +<wire x1="69.85" y1="-7.62" x2="39.37" y2="-7.62" width="0.1524" layer="91"/> +<label x="50.8" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A19" class="3"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L10P_T1_13"/> +<wire x1="69.85" y1="-10.16" x2="39.37" y2="-10.16" width="0.1524" layer="91"/> +<label x="50.8" y="-10.16" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A20" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L10N_T1_13"/> +<wire x1="69.85" y1="-12.7" x2="39.37" y2="-12.7" width="0.1524" layer="91"/> +<label x="50.8" y="-12.7" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A21" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L11P_T1_SRCC_13"/> +<wire x1="69.85" y1="-15.24" x2="39.37" y2="-15.24" width="0.1524" layer="91"/> +<label x="50.8" y="-15.24" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A22" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L11N_T1_SRCC_13"/> +<wire x1="69.85" y1="-17.78" x2="39.37" y2="-17.78" width="0.1524" layer="91"/> +<label x="50.8" y="-17.78" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A23" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L12N_T1_MRCC_13"/> +<wire x1="69.85" y1="-22.86" x2="39.37" y2="-22.86" width="0.1524" layer="91"/> +<label x="50.8" y="-22.86" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A24" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L13P_T2_MRCC_13"/> +<wire x1="69.85" y1="-25.4" x2="39.37" y2="-25.4" width="0.1524" layer="91"/> +<label x="50.8" y="-25.4" size="1.778" layer="95"/> +</segment> +</net> +<net name="FMC_A25" class="0"> +<segment> +<pinref part="U13" gate="B13" pin="IO_L13N_T2_MRCC_13"/> +<wire x1="69.85" y1="-27.94" x2="39.37" y2="-27.94" width="0.1524" layer="91"/> +<label x="50.8" y="-27.94" size="1.778" layer="95"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA voltage regulators</description> +<plain> +<text x="-17.78" y="78.74" size="1.778" layer="91">*) FPGA Power Subsystem -- AUX and I/O</text> +<text x="53.34" y="53.34" size="1.778" layer="91">*) VCCAUX = 0.75V x (1 + 205 / 147) = 1.796V + +*) VCCO = 0.75V x (1 + 205 / 59) = 3.356 + +*) Minimal load current is 2 mA: +1.8V / 470 Ohm = ~4mA +3.3V / 470 Ohm = ~7mA + +*) Light-load mode is enabled +</text> +<text x="33.02" y="-33.02" size="1.778" layer="91">This is the 3V3 rail that powers +both the FPGA and the ARM as well +as various other components.</text> +<text x="86.36" y="-68.58" size="1.9304" layer="94">FPGA voltage regulators</text> +</plain> +<instances> +<instance part="FRAME19" gate="G$1" x="-129.54" y="-88.9"/> +<instance part="SUPPLY108" gate="GND" x="-63.5" y="10.16"/> +<instance part="SUPPLY110" gate="GND" x="-53.34" y="10.16"/> +<instance part="SUPPLY106" gate="GND" x="-83.82" y="10.16"/> +<instance part="C113" gate="G$1" x="-109.22" y="50.8"> +<attribute name="DIELECTRIC" x="-109.22" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-109.22" y="50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-109.22" y="50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY102" gate="GND" x="-109.22" y="38.1"/> +<instance part="R53" gate="G$1" x="-96.52" y="20.32" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="20.32" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY104" gate="GND" x="-96.52" y="10.16"/> +<instance part="R52" gate="G$1" x="-96.52" y="50.8" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="50.8" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R56" gate="G$1" x="-27.94" y="53.34" rot="R90"> +<attribute name="TOLERANCE" x="-27.94" y="53.34" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R57" gate="G$1" x="-27.94" y="38.1" rot="R90"> +<attribute name="TOLERANCE" x="-27.94" y="38.1" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="U14" gate="G$1" x="-58.42" y="43.18"/> +<instance part="SUPPLY112" gate="GND" x="-27.94" y="27.94"/> +<instance part="SUPPLY114" gate="GND" x="-10.16" y="27.94"/> +<instance part="R60" gate="G$1" x="2.54" y="40.64" rot="R90"> +<attribute name="TOLERANCE" x="2.54" y="40.64" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY116" gate="GND" x="2.54" y="27.94"/> +<instance part="FB5" gate="G$1" x="10.16" y="58.42" smashed="yes"> +<attribute name="NAME" x="6.35" y="63.5" size="1.778" layer="95"/> +</instance> +<instance part="SUPPLY109" gate="GND" x="-63.5" y="-71.12"/> +<instance part="SUPPLY111" gate="GND" x="-53.34" y="-71.12"/> +<instance part="SUPPLY107" gate="GND" x="-83.82" y="-71.12"/> +<instance part="C114" gate="G$1" x="-109.22" y="-30.48"> +<attribute name="DIELECTRIC" x="-109.22" y="-30.48" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-109.22" y="-30.48" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-109.22" y="-30.48" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY103" gate="GND" x="-109.22" y="-43.18"/> +<instance part="R55" gate="G$1" x="-96.52" y="-60.96" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="-60.96" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY105" gate="GND" x="-96.52" y="-71.12"/> +<instance part="R54" gate="G$1" x="-96.52" y="-30.48" rot="R90"> +<attribute name="TOLERANCE" x="-96.52" y="-30.48" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R58" gate="G$1" x="-27.94" y="-27.94" rot="R90"> +<attribute name="TOLERANCE" x="-27.94" y="-27.94" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R59" gate="G$1" x="-27.94" y="-43.18" rot="R90"> +<attribute name="TOLERANCE" x="-27.94" y="-43.18" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="U15" gate="G$1" x="-58.42" y="-38.1"/> +<instance part="SUPPLY113" gate="GND" x="-27.94" y="-53.34"/> +<instance part="SUPPLY115" gate="GND" x="-10.16" y="-53.34"/> +<instance part="R61" gate="G$1" x="2.54" y="-40.64" rot="R90"> +<attribute name="TOLERANCE" x="2.54" y="-40.64" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY117" gate="GND" x="2.54" y="-53.34"/> +<instance part="FB6" gate="G$1" x="10.16" y="-22.86" smashed="yes"> +<attribute name="NAME" x="6.35" y="-17.78" size="1.778" layer="95"/> +</instance> +<instance part="C115" gate="G$1" x="-83.82" y="20.32"> +<attribute name="RATED_VOLTAGE" x="-83.82" y="20.32" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-83.82" y="20.32" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-83.82" y="20.32" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C116" 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x2="2.54" y2="-45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_VCCAUX_1V8" class="0"> +<segment> +<pinref part="FB5" gate="G$1" pin="2"/> +<wire x1="15.24" y1="60.96" x2="40.64" y2="60.96" width="0.1524" layer="91"/> +<label x="17.78" y="60.96" size="1.778" layer="95"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<pinref part="FB6" gate="G$1" pin="2"/> +<wire x1="15.24" y1="-20.32" x2="40.64" y2="-20.32" width="0.1524" layer="91"/> +<label x="17.78" y="-20.32" size="1.778" layer="95"/> +</segment> +</net> +<net name="N$35" class="0"> +<segment> +<wire x1="-83.82" y1="22.86" x2="-83.82" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="25.4" x2="-78.74" y2="25.4" width="0.1524" layer="91"/> +<pinref part="U14" gate="G$1" pin="SS"/> +<pinref part="C115" gate="G$1" pin="1"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<wire x1="-78.74" y1="60.96" x2="-83.82" y2="60.96" width="0.1524" layer="91"/> +<label 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pin="VCC"/> +</segment> +</net> +<net name="PWR_ENA_VCCAUX" class="0"> +<segment> +<wire x1="-78.74" y1="50.8" x2="-88.9" y2="50.8" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="50.8" x2="-88.9" y2="73.66" width="0.1524" layer="91"/> +<label x="-88.9" y="73.66" size="1.778" layer="95" rot="R180" xref="yes"/> +<pinref part="U14" gate="G$1" pin="ENABLE"/> +</segment> +</net> +<net name="N$36" class="0"> +<segment> +<pinref part="R53" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="25.4" x2="-96.52" y2="35.56" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="35.56" x2="-78.74" y2="35.56" width="0.1524" layer="91"/> +<pinref part="U14" gate="G$1" pin="RLLM"/> +</segment> +</net> +<net name="N$37" class="0"> +<segment> +<wire x1="-78.74" y1="40.64" x2="-96.52" y2="40.64" width="0.1524" layer="91"/> +<pinref part="R52" gate="G$1" pin="1"/> +<wire x1="-96.52" y1="40.64" x2="-96.52" y2="45.72" width="0.1524" layer="91"/> +<pinref part="U14" gate="G$1" pin="LLM/SYNC"/> +</segment> +</net> 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width="0.1524" layer="91"/> +<junction x="2.54" y="60.96"/> +<pinref part="C117" gate="G$1" pin="1"/> +<pinref part="C119" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$39" class="0"> +<segment> +<pinref part="R56" gate="G$1" pin="1"/> +<wire x1="-27.94" y1="48.26" x2="-27.94" y2="45.72" width="0.1524" layer="91"/> +<pinref part="U14" gate="G$1" pin="VFB"/> +<wire x1="-27.94" y1="45.72" x2="-38.1" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="50.8" x2="-20.32" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="45.72" x2="-27.94" y2="45.72" width="0.1524" layer="91"/> +<junction x="-27.94" y="45.72"/> +<pinref part="R57" gate="G$1" pin="2"/> +<wire x1="-27.94" y1="43.18" x2="-27.94" y2="45.72" width="0.1524" layer="91"/> +<pinref part="C117" gate="G$1" pin="2"/> +</segment> +</net> +<net name="N$40" class="0"> +<segment> +<wire x1="-83.82" y1="-58.42" x2="-83.82" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="-55.88" x2="-78.74" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="U15" gate="G$1" pin="SS"/> +<pinref part="C116" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$41" class="0"> +<segment> +<pinref part="R55" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="-55.88" x2="-96.52" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-45.72" x2="-78.74" y2="-45.72" width="0.1524" layer="91"/> +<pinref part="U15" gate="G$1" pin="RLLM"/> +</segment> +</net> +<net name="N$42" class="0"> +<segment> +<wire x1="-78.74" y1="-40.64" x2="-96.52" y2="-40.64" width="0.1524" layer="91"/> +<pinref part="R54" gate="G$1" pin="1"/> +<wire x1="-96.52" y1="-40.64" x2="-96.52" y2="-35.56" width="0.1524" layer="91"/> +<pinref part="U15" gate="G$1" pin="LLM/SYNC"/> +</segment> +</net> +<net name="N$43" class="0"> +<segment> +<pinref part="U15" gate="G$1" pin="VOUT"/> +<wire x1="-38.1" y1="-20.32" x2="-27.94" y2="-20.32" width="0.1524" layer="91"/> +<pinref part="R58" gate="G$1" pin="2"/> +<wire x1="-27.94" y1="-20.32" x2="-27.94" y2="-22.86" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-22.86" x2="-20.32" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-20.32" x2="-27.94" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-27.94" y="-20.32"/> +<wire x1="-10.16" y1="-35.56" x2="-10.16" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-10.16" y1="-20.32" x2="-20.32" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-20.32" y="-20.32"/> +<pinref part="R61" gate="G$1" pin="2"/> +<wire x1="2.54" y1="-35.56" x2="2.54" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="2.54" y1="-20.32" x2="-10.16" y2="-20.32" width="0.1524" layer="91"/> +<junction x="-10.16" y="-20.32"/> +<pinref part="FB6" gate="G$1" pin="1"/> +<wire x1="5.08" y1="-20.32" x2="2.54" y2="-20.32" width="0.1524" layer="91"/> +<junction x="2.54" y="-20.32"/> +<pinref part="C118" gate="G$1" pin="1"/> +<pinref part="C120" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$44" class="0"> +<segment> +<pinref part="R58" gate="G$1" pin="1"/> +<wire x1="-27.94" y1="-33.02" x2="-27.94" y2="-35.56" width="0.1524" layer="91"/> +<pinref part="U15" gate="G$1" pin="VFB"/> +<wire x1="-27.94" y1="-35.56" x2="-38.1" y2="-35.56" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-30.48" x2="-20.32" y2="-35.56" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-35.56" x2="-27.94" y2="-35.56" width="0.1524" layer="91"/> +<junction x="-27.94" y="-35.56"/> +<pinref part="R59" gate="G$1" pin="2"/> +<wire x1="-27.94" y1="-38.1" x2="-27.94" y2="-35.56" width="0.1524" layer="91"/> +<pinref part="C118" gate="G$1" pin="2"/> +</segment> +</net> +<net name="PWR_ENA_VCCO" class="0"> +<segment> +<wire x1="-78.74" y1="-30.48" x2="-88.9" y2="-30.48" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="-30.48" x2="-88.9" y2="-7.62" width="0.1524" layer="91"/> +<label x="-91.44" y="-7.62" size="1.778" layer="95" rot="R180" xref="yes"/> +<pinref part="U15" gate="G$1" pin="ENABLE"/> +<wire x1="-88.9" y1="-7.62" x2="-91.44" y2="-7.62" width="0.1524" layer="91"/> +</segment> +</net> +<net name="POK_VCCAUX" class="0"> +<segment> +<pinref part="U14" gate="G$1" pin="POK"/> +<wire x1="-38.1" y1="25.4" x2="-35.56" y2="25.4" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="25.4" x2="-35.56" y2="17.78" width="0.1524" layer="91"/> +<label x="-35.56" y="17.78" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +<net name="POK_VCCO" class="0"> +<segment> +<pinref part="U15" gate="G$1" pin="POK"/> +<wire x1="-38.1" y1="-55.88" x2="-35.56" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-35.56" y1="-55.88" x2="-35.56" y2="-63.5" width="0.1524" layer="91"/> +<label x="-35.56" y="-63.5" size="1.778" layer="95" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA GPIO</description> +<plain> +<text x="-111.76" y="76.2" size="1.778" layer="91">*) Upper Right Bank</text> +<text x="-86.36" y="-17.78" size="1.778" layer="91">*) FPGA_GCLK signal _MUST_ go into either D17 or C18 +(i.e. into one of the two positive (master) sides +of the two available MRCC differential pairs)</text> +<text x="-86.36" y="-22.86" size="1.778" layer="91">*) FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped</text> +<text x="22.86" y="72.39" size="1.778" layer="91">*) Signals, that are allowed to be swapped, can be be swapped +with each other and/or moved to different pins within their bank.</text> +<text x="-53.34" y="12.7" size="1.778" layer="91">NOTE: One of the FPGA_GPIO_* pins +should be connected to one of the +MRCC pins. + +The non-MRCC GPIO signals should be +length matched to within 500 ps of +the MRCC signal.</text> +<text x="86.36" y="-71.12" size="2.54" layer="94">FPGA GPIO</text> +</plain> +<instances> +<instance part="U13" gate="B16" x="-93.98" y="-2.54"/> +<instance part="FRAME20" gate="G$1" x="-129.54" y="-91.44"/> +<instance part="SV2" gate="G$1" x="86.36" y="50.8" rot="R180"/> +<instance part="SUPPLY118" gate="GND" x="45.72" y="33.02"/> +<instance part="SUPPLY120" gate="GND" x="76.2" y="33.02"/> +<instance part="SUPPLY122" gate="GND" x="96.52" y="33.02"/> +<instance part="SV3" gate="G$1" x="86.36" y="2.54" rot="R180"/> +<instance part="SUPPLY119" gate="GND" x="45.72" y="-15.24"/> +<instance part="SUPPLY121" gate="GND" x="76.2" y="-15.24"/> +<instance part="SUPPLY123" gate="GND" x="96.52" y="-15.24"/> +<instance part="C121" gate="G$1" x="45.72" y="48.26"> +<attribute name="DIELECTRIC" x="45.72" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="45.72" y="48.26" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="45.72" y="48.26" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C122" gate="G$1" x="45.72" y="0"> +<attribute name="DIELECTRIC" x="45.72" y="0" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="45.72" y="0" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="45.72" y="0" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+71" gate="VCC" x="-83.82" y="73.66" smashed="yes"/> +<instance part="P+72" gate="VCC" x="45.72" y="71.12" smashed="yes"/> +<instance part="P+73" gate="VCC" x="45.72" y="22.86" smashed="yes"/> +<instance part="LED17" gate="G$1" x="91.44" y="-48.26" smashed="yes" rot="R90"> +<attribute name="NAME" x="121.412" y="-47.244" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="102.108" y="-48.895" size="1.778" layer="96"/> +</instance> +<instance part="LED15" gate="G$1" x="86.36" y="-45.72" smashed="yes" rot="R90"> +<attribute name="NAME" x="121.412" y="-44.704" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="102.108" y="-46.355" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY124" gate="GND" x="99.06" y="-55.88"/> +<instance part="LED16" gate="G$1" x="91.44" y="-43.18" smashed="yes" rot="R90"> +<attribute name="NAME" x="121.412" y="-42.164" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="102.108" y="-43.815" size="1.778" layer="96"/> +</instance> +<instance part="LED14" gate="G$1" x="86.36" y="-40.64" smashed="yes" rot="R90"> +<attribute name="NAME" x="121.412" y="-39.624" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="102.108" y="-41.275" size="1.778" layer="96"/> +</instance> +<instance part="R64" gate="A" x="71.12" y="-40.64"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY118" gate="GND" pin="GND"/> +<wire x1="45.72" y1="35.56" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<pinref part="C121" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY120" gate="GND" pin="GND"/> +<wire x1="76.2" y1="35.56" x2="76.2" y2="45.72" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="11"/> +<wire x1="76.2" y1="45.72" x2="78.74" y2="45.72" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="5"/> +<wire x1="78.74" y1="53.34" x2="76.2" y2="53.34" width="0.1524" layer="91"/> +<wire x1="76.2" y1="53.34" x2="76.2" y2="45.72" width="0.1524" layer="91"/> +<junction x="76.2" y="45.72"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="12"/> +<wire x1="93.98" y1="45.72" x2="96.52" y2="45.72" width="0.1524" layer="91"/> +<pinref part="SUPPLY122" gate="GND" pin="GND"/> +<wire x1="96.52" y1="45.72" x2="96.52" y2="35.56" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="6"/> +<wire x1="93.98" y1="53.34" x2="96.52" y2="53.34" width="0.1524" layer="91"/> +<wire x1="96.52" y1="53.34" x2="96.52" y2="45.72" width="0.1524" layer="91"/> +<junction x="96.52" y="45.72"/> +</segment> +<segment> +<pinref part="SUPPLY119" gate="GND" pin="GND"/> +<wire x1="45.72" y1="-12.7" x2="45.72" y2="-5.08" width="0.1524" layer="91"/> +<pinref part="C122" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY121" gate="GND" pin="GND"/> +<wire x1="76.2" y1="-12.7" x2="76.2" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="SV3" gate="G$1" pin="11"/> +<wire x1="76.2" y1="-2.54" x2="78.74" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="SV3" gate="G$1" pin="5"/> +<wire x1="78.74" y1="5.08" x2="76.2" y2="5.08" width="0.1524" layer="91"/> +<wire x1="76.2" y1="5.08" x2="76.2" y2="-2.54" width="0.1524" layer="91"/> +<junction x="76.2" y="-2.54"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="12"/> +<wire x1="93.98" y1="-2.54" x2="96.52" y2="-2.54" width="0.1524" layer="91"/> +<pinref part="SUPPLY123" gate="GND" pin="GND"/> +<wire x1="96.52" y1="-2.54" x2="96.52" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="SV3" gate="G$1" pin="6"/> +<wire x1="93.98" y1="5.08" x2="96.52" y2="5.08" width="0.1524" layer="91"/> +<wire x1="96.52" y1="5.08" x2="96.52" y2="-2.54" width="0.1524" layer="91"/> +<junction x="96.52" y="-2.54"/> +</segment> +<segment> +<pinref part="SUPPLY124" gate="GND" pin="GND"/> +<pinref part="LED17" gate="G$1" pin="C"/> +<wire x1="99.06" y1="-53.34" x2="99.06" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-48.26" x2="96.52" y2="-48.26" width="0.1524" layer="91"/> +<pinref part="LED15" gate="G$1" pin="C"/> +<wire x1="99.06" y1="-45.72" x2="91.44" y2="-45.72" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-45.72" x2="99.06" y2="-48.26" width="0.1524" layer="91"/> +<junction x="99.06" y="-48.26"/> +<pinref part="LED16" gate="G$1" pin="C"/> +<wire x1="99.06" y1="-43.18" x2="96.52" y2="-43.18" width="0.1524" layer="91"/> +<junction x="99.06" y="-45.72"/> +<pinref part="LED14" gate="G$1" pin="C"/> +<wire x1="99.06" y1="-40.64" x2="91.44" y2="-40.64" width="0.1524" layer="91"/> +<wire x1="99.06" y1="-40.64" x2="99.06" y2="-43.18" width="0.1524" layer="91"/> +<junction x="99.06" y="-43.18"/> +<wire x1="99.06" y1="-43.18" x2="99.06" y2="-45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="-88.9" y1="66.04" x2="-83.82" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="66.04" x2="-83.82" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="63.5" x2="-83.82" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="60.96" x2="-83.82" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="58.42" x2="-83.82" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="55.88" x2="-88.9" y2="55.88" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="58.42" x2="-83.82" y2="58.42" width="0.1524" layer="91"/> +<junction x="-83.82" y="58.42"/> +<wire x1="-88.9" y1="60.96" x2="-83.82" y2="60.96" width="0.1524" layer="91"/> +<junction x="-83.82" y="60.96"/> +<wire x1="-88.9" y1="63.5" x2="-83.82" y2="63.5" width="0.1524" layer="91"/> +<junction x="-83.82" y="63.5"/> +<junction x="-83.82" y="66.04"/> +<wire x1="-83.82" y1="66.04" x2="-83.82" y2="71.12" width="0.1524" layer="91"/> +<label x="-81.28" y="66.04" size="1.778" layer="95"/> +<pinref part="U13" gate="B16" pin="VCCO_16@5"/> +<wire x1="-88.9" y1="53.34" x2="-83.82" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-83.82" y1="53.34" x2="-83.82" y2="55.88" width="0.1524" layer="91"/> +<junction x="-83.82" y="55.88"/> +<pinref part="U13" gate="B16" pin="VCCO_16@4"/> +<pinref part="U13" gate="B16" pin="VCCO_16@3"/> +<pinref part="U13" gate="B16" pin="VCCO_16@2"/> +<pinref part="U13" gate="B16" pin="VCCO_16@1"/> +<pinref part="U13" gate="B16" pin="VCCO_16@0"/> +<pinref part="P+71" gate="VCC" pin="VCC"/> +</segment> +<segment> +<label x="48.26" y="66.04" size="1.778" layer="95"/> +<wire x1="76.2" y1="63.5" x2="45.72" y2="63.5" width="0.1524" layer="91"/> +<wire x1="45.72" y1="63.5" x2="45.72" y2="68.58" width="0.1524" layer="91"/> +<wire x1="45.72" y1="50.8" x2="45.72" y2="63.5" width="0.1524" layer="91"/> +<junction x="45.72" y="63.5"/> +<pinref part="SV2" gate="G$1" pin="3"/> +<wire x1="78.74" y1="55.88" x2="76.2" y2="55.88" width="0.1524" layer="91"/> +<wire x1="76.2" y1="55.88" x2="76.2" y2="58.42" width="0.1524" layer="91"/> +<junction x="76.2" y="63.5"/> +<pinref part="SV2" gate="G$1" pin="2"/> +<wire x1="76.2" y1="58.42" x2="76.2" y2="63.5" width="0.1524" layer="91"/> +<wire x1="93.98" y1="58.42" x2="96.52" y2="58.42" width="0.1524" layer="91"/> +<wire x1="96.52" y1="58.42" x2="96.52" y2="63.5" width="0.1524" layer="91"/> +<wire x1="96.52" y1="63.5" x2="76.2" y2="63.5" width="0.1524" layer="91"/> +<pinref part="SV2" gate="G$1" pin="4"/> +<wire x1="93.98" y1="55.88" x2="96.52" y2="55.88" width="0.1524" layer="91"/> +<wire x1="96.52" y1="55.88" x2="96.52" y2="58.42" width="0.1524" layer="91"/> +<junction x="96.52" y="58.42"/> +<pinref part="SV2" gate="G$1" pin="1"/> +<wire x1="78.74" y1="58.42" x2="76.2" y2="58.42" width="0.1524" layer="91"/> +<junction x="76.2" y="58.42"/> +<pinref part="C121" gate="G$1" pin="1"/> +<pinref part="P+72" gate="VCC" pin="VCC"/> +</segment> +<segment> +<label x="48.26" y="20.32" size="1.778" layer="95"/> +<wire x1="76.2" y1="15.24" x2="45.72" y2="15.24" width="0.1524" layer="91"/> +<wire x1="45.72" y1="15.24" x2="45.72" y2="20.32" width="0.1524" layer="91"/> +<wire x1="45.72" y1="2.54" x2="45.72" y2="15.24" width="0.1524" layer="91"/> +<junction x="45.72" y="15.24"/> +<pinref part="SV3" gate="G$1" pin="3"/> +<wire x1="78.74" y1="7.62" x2="76.2" y2="7.62" width="0.1524" layer="91"/> +<wire x1="76.2" y1="7.62" x2="76.2" y2="10.16" width="0.1524" layer="91"/> +<junction x="76.2" y="15.24"/> +<pinref part="SV3" gate="G$1" pin="2"/> +<wire x1="76.2" y1="10.16" x2="76.2" y2="15.24" width="0.1524" layer="91"/> +<wire x1="93.98" y1="10.16" x2="96.52" y2="10.16" width="0.1524" layer="91"/> +<wire x1="96.52" y1="10.16" x2="96.52" y2="15.24" width="0.1524" layer="91"/> +<wire x1="96.52" y1="15.24" x2="76.2" y2="15.24" width="0.1524" layer="91"/> +<pinref part="SV3" gate="G$1" pin="4"/> +<wire x1="93.98" y1="7.62" x2="96.52" y2="7.62" width="0.1524" layer="91"/> +<wire x1="96.52" y1="7.62" x2="96.52" y2="10.16" width="0.1524" layer="91"/> +<junction x="96.52" y="10.16"/> +<pinref part="SV3" gate="G$1" pin="1"/> +<wire x1="78.74" y1="10.16" x2="76.2" y2="10.16" width="0.1524" layer="91"/> +<junction x="76.2" y="10.16"/> +<pinref part="C122" gate="G$1" pin="1"/> +<pinref part="P+73" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_0" class="0"> +<segment> +<wire x1="-88.9" y1="-27.94" x2="-58.42" y2="-27.94" width="0.1524" layer="91"/> +<label x="-58.42" y="-27.94" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_1" class="0"> +<segment> +<wire x1="-88.9" y1="-30.48" x2="-58.42" y2="-30.48" width="0.1524" layer="91"/> +<label x="-58.42" y="-30.48" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_0" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L1N_T0_16"/> +<wire x1="-88.9" y1="45.72" x2="-58.42" y2="45.72" width="0.1524" layer="91"/> +<label x="-58.42" y="45.72" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_1" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L2P_T0_16"/> +<wire x1="-88.9" y1="43.18" x2="-58.42" y2="43.18" width="0.1524" layer="91"/> +<label x="-58.42" y="43.18" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_2" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L2N_T0_16"/> +<wire x1="-88.9" y1="40.64" x2="-58.42" y2="40.64" width="0.1524" layer="91"/> +<label x="-58.42" y="40.64" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_IRQ_N_3" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L3P_T0_DQS_16"/> +<wire x1="-88.9" y1="38.1" x2="-58.42" y2="38.1" width="0.1524" layer="91"/> +<label x="-58.42" y="38.1" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_A_0" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L3N_T0_DQS_16"/> +<wire x1="-88.9" y1="35.56" x2="-58.42" y2="35.56" width="0.1524" layer="91"/> +<label x="-83.82" y="35.56" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="7"/> +<wire x1="78.74" y1="50.8" x2="55.88" y2="50.8" width="0.1524" layer="91"/> +<label x="55.88" y="50.8" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_1" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L4P_T0_16"/> +<wire x1="-88.9" y1="33.02" x2="-58.42" y2="33.02" width="0.1524" layer="91"/> +<label x="-83.82" y="33.02" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="8"/> +<wire x1="93.98" y1="50.8" x2="116.84" y2="50.8" width="0.1524" layer="91"/> +<label x="99.06" y="50.8" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_2" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L4N_T0_16"/> +<wire x1="-88.9" y1="30.48" x2="-58.42" y2="30.48" width="0.1524" layer="91"/> +<label x="-83.82" y="30.48" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="9"/> +<wire x1="78.74" y1="48.26" x2="55.88" y2="48.26" width="0.1524" layer="91"/> +<label x="55.88" y="48.26" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_3" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L5P_T0_16"/> +<wire x1="-88.9" y1="27.94" x2="-58.42" y2="27.94" width="0.1524" layer="91"/> +<label x="-83.82" y="27.94" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="10"/> +<wire x1="93.98" y1="48.26" x2="116.84" y2="48.26" width="0.1524" layer="91"/> +<label x="99.06" y="48.26" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_4" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L5N_T0_16"/> +<wire x1="-88.9" y1="25.4" x2="-58.42" y2="25.4" width="0.1524" layer="91"/> +<label x="-83.82" y="25.4" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="13"/> +<wire x1="78.74" y1="43.18" x2="55.88" y2="43.18" width="0.1524" layer="91"/> +<label x="55.88" y="43.18" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_5" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L6P_T0_16"/> +<wire x1="-88.9" y1="22.86" x2="-58.42" y2="22.86" width="0.1524" layer="91"/> +<label x="-83.82" y="22.86" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="14"/> +<wire x1="93.98" y1="43.18" x2="116.84" y2="43.18" width="0.1524" layer="91"/> +<label x="99.06" y="43.18" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_6" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L6N_T0_VREF_16"/> +<wire x1="-88.9" y1="20.32" x2="-58.42" y2="20.32" width="0.1524" layer="91"/> +<label x="-83.82" y="20.32" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="15"/> +<wire x1="78.74" y1="40.64" x2="55.88" y2="40.64" width="0.1524" layer="91"/> +<label x="55.88" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_A_7" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L7P_T1_16"/> +<wire x1="-88.9" y1="17.78" x2="-58.42" y2="17.78" width="0.1524" layer="91"/> +<label x="-83.82" y="17.78" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV2" gate="G$1" pin="16"/> +<wire x1="93.98" y1="40.64" x2="116.84" y2="40.64" width="0.1524" layer="91"/> +<label x="99.06" y="40.64" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_0" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L7N_T1_16"/> +<wire x1="-88.9" y1="15.24" x2="-58.42" y2="15.24" width="0.1524" layer="91"/> +<label x="-83.82" y="15.24" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="7"/> +<wire x1="78.74" y1="2.54" x2="55.88" y2="2.54" width="0.1524" layer="91"/> +<label x="55.88" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_1" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L8P_T1_16"/> +<wire x1="-88.9" y1="12.7" x2="-58.42" y2="12.7" width="0.1524" layer="91"/> +<label x="-83.82" y="12.7" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="8"/> +<wire x1="93.98" y1="2.54" x2="116.84" y2="2.54" width="0.1524" layer="91"/> +<label x="99.06" y="2.54" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_2" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L8N_T1_16"/> +<wire x1="-88.9" y1="10.16" x2="-58.42" y2="10.16" width="0.1524" layer="91"/> +<label x="-83.82" y="10.16" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="9"/> +<wire x1="78.74" y1="0" x2="55.88" y2="0" width="0.1524" layer="91"/> +<label x="55.88" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_3" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L9P_T1_DQS_16"/> +<wire x1="-88.9" y1="7.62" x2="-58.42" y2="7.62" width="0.1524" layer="91"/> +<label x="-83.82" y="7.62" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="10"/> +<wire x1="93.98" y1="0" x2="116.84" y2="0" width="0.1524" layer="91"/> +<label x="99.06" y="0" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_4" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L9N_T1_DQS_16"/> +<wire x1="-88.9" y1="5.08" x2="-58.42" y2="5.08" width="0.1524" layer="91"/> +<label x="-83.82" y="5.08" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="13"/> +<wire x1="78.74" y1="-5.08" x2="55.88" y2="-5.08" width="0.1524" layer="91"/> +<label x="55.88" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_5" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L10P_T1_16"/> +<wire x1="-88.9" y1="2.54" x2="-58.42" y2="2.54" width="0.1524" layer="91"/> +<label x="-83.82" y="2.54" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="14"/> +<wire x1="93.98" y1="-5.08" x2="116.84" y2="-5.08" width="0.1524" layer="91"/> +<label x="99.06" y="-5.08" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_6" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L10N_T1_16"/> +<wire x1="-88.9" y1="0" x2="-58.42" y2="0" width="0.1524" layer="91"/> +<label x="-83.82" y="0" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="15"/> +<wire x1="78.74" y1="-7.62" x2="55.88" y2="-7.62" width="0.1524" layer="91"/> +<label x="55.88" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GPIO_B_7" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L11P_T1_SRCC_16"/> +<wire x1="-88.9" y1="-2.54" x2="-58.42" y2="-2.54" width="0.1524" layer="91"/> +<label x="-83.82" y="-2.54" size="1.778" layer="95"/> +</segment> +<segment> +<pinref part="SV3" gate="G$1" pin="16"/> +<wire x1="93.98" y1="-7.62" x2="116.84" y2="-7.62" width="0.1524" layer="91"/> +<label x="99.06" y="-7.62" size="1.778" layer="95"/> +</segment> +</net> +<net name="FPGA_GCLK" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L12P_T1_MRCC_16"/> +<wire x1="-88.9" y1="-7.62" x2="-58.42" y2="-7.62" width="0.1524" layer="91"/> +<label x="-58.42" y="-7.62" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_2" class="0"> +<segment> +<wire x1="60.96" y1="-43.18" x2="58.42" y2="-43.18" width="0.1524" layer="91"/> +<label x="58.42" y="-43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R64" gate="A" pin="2"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_3" class="0"> +<segment> +<wire x1="60.96" y1="-40.64" x2="58.42" y2="-40.64" width="0.1524" layer="91"/> +<label x="58.42" y="-40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R64" gate="A" pin="1"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_0" class="0"> +<segment> +<wire x1="60.96" y1="-48.26" x2="58.42" y2="-48.26" width="0.1524" layer="91"/> +<label x="58.42" y="-48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R64" gate="A" pin="4"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_1" class="0"> +<segment> +<wire x1="60.96" y1="-45.72" x2="58.42" y2="-45.72" width="0.1524" layer="91"/> +<label x="58.42" y="-45.72" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R64" gate="A" pin="3"/> +</segment> +</net> +<net name="N$27" class="0"> +<segment> +<pinref part="LED17" gate="G$1" pin="A"/> +<pinref part="R64" gate="A" pin="5"/> +<wire x1="81.28" y1="-48.26" x2="88.9" y2="-48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$28" class="0"> +<segment> +<pinref part="LED15" gate="G$1" pin="A"/> +<pinref part="R64" gate="A" pin="6"/> +<wire x1="81.28" y1="-45.72" x2="83.82" y2="-45.72" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$29" class="0"> +<segment> +<pinref part="LED16" gate="G$1" pin="A"/> +<pinref part="R64" gate="A" pin="7"/> +<wire x1="81.28" y1="-43.18" x2="88.9" y2="-43.18" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$30" class="0"> +<segment> +<pinref part="LED14" gate="G$1" pin="A"/> +<pinref part="R64" gate="A" pin="8"/> +<wire x1="81.28" y1="-40.64" x2="83.82" y2="-40.64" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_ENTROPY_DISABLE" class="0"> +<segment> +<pinref part="U13" gate="B16" pin="IO_L11N_T1_SRCC_16"/> +<wire x1="-88.9" y1="-5.08" x2="-58.42" y2="-5.08" width="0.1524" layer="91"/> +<label x="-58.42" y="-5.08" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_2" class="0"> +<segment> +<wire x1="-88.9" y1="-33.02" x2="-58.42" y2="-33.02" width="0.1524" layer="91"/> +<label x="-58.42" y="-33.02" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="AVR_GPIO_FPGA_3" class="0"> +<segment> +<wire x1="-88.9" y1="-35.56" x2="-58.42" y2="-35.56" width="0.1524" layer="91"/> +<label x="-58.42" y="-35.56" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA MKM interface</description> +<plain> +<text x="-96.52" y="78.74" size="1.778" layer="91">*) Lower Right Bank</text> +<text x="-55.88" y="-17.78" size="1.778" layer="91">DIGITIZED_NOISE signal should go into +either W19 or Y18 (i.e. into one of the two +positive (master) sides of the two available +MRCC differential pairs)</text> +<text x="27.94" y="78.74" size="1.778" layer="91">*) Signals, that are allowed to be swapped, can be be swapped +with each other and/or moved to different pins within their bank.</text> +<text x="-15.24" y="17.78" size="1.778" layer="91"><-- FPGA_GPIO_* and FPGA_IRQ_N_* signals can be swapped</text> +<text x="-58.42" y="60.96" size="1.778" layer="91"><-- Disable pull-ups on all pins during configuration</text> +<text x="86.36" y="-68.58" size="2.54" layer="94">FPGA MKM interface</text> +</plain> +<instances> +<instance part="U13" gate="B14" x="-81.28" y="0"/> +<instance part="FRAME21" gate="G$1" x="-129.54" y="-88.9"/> +<instance part="R65" gate="G$1" x="-63.5" y="60.96" rot="R90"> +<attribute name="TOLERANCE" x="-63.5" y="60.96" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="P+74" gate="VCC" x="-63.5" y="76.2" smashed="yes"/> +<instance part="R83" gate="G$1" x="-53.34" y="50.8" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-53.34" y="50.8" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-55.88" y="53.34" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-63.5" y="53.34" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R84" gate="G$1" x="-53.34" y="48.26" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-53.34" y="48.26" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-55.88" y="50.8" size="1.778" layer="95" rot="R180"/> +<attribute name="VALUE" x="-63.5" y="50.8" size="1.778" layer="96" rot="R180"/> +</instance> +<instance part="R85" gate="G$1" x="-53.34" y="25.4" smashed="yes" rot="R180"> +<attribute name="TOLERANCE" x="-53.34" y="25.4" size="1.778" layer="96" rot="R180" display="off"/> +<attribute name="NAME" x="-60.96" y="25.4" size="1.778" layer="95"/> +<attribute name="VALUE" x="-60.96" y="22.86" size="1.778" layer="96"/> +</instance> +</instances> +<busses> +</busses> +<nets> +<net name="DIGITIZED_NOISE" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L12P_T1_MRCC_14"/> +<wire x1="-76.2" y1="-5.08" x2="-45.72" y2="-5.08" width="0.1524" layer="91"/> +<label x="-45.72" y="-5.08" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_2" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L7N_T1_D10_14"/> +<wire x1="-76.2" y1="17.78" x2="-45.72" y2="17.78" width="0.1524" layer="91"/> +<label x="-45.72" y="17.78" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_3" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L8P_T1_D11_14"/> +<wire x1="-76.2" y1="15.24" x2="-45.72" y2="15.24" width="0.1524" layer="91"/> +<label x="-45.72" y="15.24" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_0" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L6N_T0_D08_VREF_14"/> +<wire x1="-76.2" y1="22.86" x2="-45.72" y2="22.86" width="0.1524" layer="91"/> +<label x="-45.72" y="22.86" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_GPIO_LED_1" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L7P_T1_D09_14"/> +<wire x1="-76.2" y1="20.32" x2="-45.72" y2="20.32" width="0.1524" layer="91"/> +<label x="-45.72" y="20.32" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_CS_N" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L4P_T0_D04_14"/> +<wire x1="-76.2" y1="35.56" x2="-45.72" y2="35.56" width="0.1524" layer="91"/> +<label x="-45.72" y="35.56" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_SCK" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L4N_T0_D05_14"/> +<wire x1="-76.2" y1="33.02" x2="-45.72" y2="33.02" width="0.1524" layer="91"/> +<label x="-45.72" y="33.02" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_MOSI" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L5P_T0_D06_14"/> +<wire x1="-76.2" y1="30.48" x2="-45.72" y2="30.48" width="0.1524" layer="91"/> +<label x="-45.72" y="30.48" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="MKM_FPGA_MISO" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L5N_T0_D07_14"/> +<wire x1="-76.2" y1="27.94" x2="-45.72" y2="27.94" width="0.1524" layer="91"/> +<label x="-45.72" y="27.94" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="N$32" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L3P_T0_DQS_PUDC_B_14"/> +<pinref part="R65" gate="G$1" pin="1"/> +<wire x1="-76.2" y1="40.64" x2="-63.5" y2="40.64" width="0.1524" layer="91"/> +<wire x1="-63.5" y1="40.64" x2="-63.5" y2="55.88" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCCO_3V3" class="0"> +<segment> +<wire x1="-76.2" y1="68.58" x2="-71.12" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="68.58" x2="-71.12" y2="66.04" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="66.04" x2="-71.12" y2="63.5" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="63.5" x2="-71.12" y2="60.96" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="60.96" x2="-71.12" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="58.42" x2="-76.2" y2="58.42" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="60.96" x2="-71.12" y2="60.96" width="0.1524" layer="91"/> +<junction x="-71.12" y="60.96"/> +<wire x1="-76.2" y1="63.5" x2="-71.12" y2="63.5" width="0.1524" layer="91"/> +<junction x="-71.12" y="63.5"/> +<wire x1="-76.2" y1="66.04" x2="-71.12" y2="66.04" width="0.1524" layer="91"/> +<junction x="-71.12" y="66.04"/> +<junction x="-71.12" y="68.58"/> +<wire x1="-71.12" y1="68.58" x2="-63.5" y2="68.58" width="0.1524" layer="91"/> +<label x="-60.96" y="73.66" size="1.778" layer="95"/> +<wire x1="-63.5" y1="68.58" x2="-63.5" y2="73.66" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="55.88" x2="-71.12" y2="58.42" width="0.1524" layer="91"/> +<junction x="-71.12" y="58.42"/> +<pinref part="U13" gate="B14" pin="VCCO_14@5"/> +<wire x1="-76.2" y1="55.88" x2="-71.12" y2="55.88" width="0.1524" layer="91"/> +<pinref part="U13" gate="B14" pin="VCCO_14@4"/> +<pinref part="U13" gate="B14" pin="VCCO_14@3"/> +<pinref part="U13" gate="B14" pin="VCCO_14@2"/> +<pinref part="U13" gate="B14" pin="VCCO_14@1"/> +<pinref part="U13" gate="B14" pin="VCCO_14@0"/> +<pinref part="R65" gate="G$1" pin="2"/> +<wire x1="-63.5" y1="66.04" x2="-63.5" y2="68.58" width="0.1524" layer="91"/> +<junction x="-63.5" y="68.58"/> +<pinref part="P+74" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FPGA_CFG_MOSI" class="0"> +<segment> +<wire x1="-48.26" y1="50.8" x2="-45.72" y2="50.8" width="0.1524" layer="91"/> +<label x="-45.72" y="50.8" size="1.27" layer="95" xref="yes"/> +<pinref part="R83" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_CFG_MISO" class="0"> +<segment> +<wire x1="-48.26" y1="48.26" x2="-45.72" y2="48.26" width="0.1524" layer="91"/> +<label x="-45.72" y="48.26" size="1.27" layer="95" xref="yes"/> +<pinref part="R84" gate="G$1" pin="1"/> +</segment> +</net> +<net name="FPGA_CFG_CS_N" class="0"> +<segment> +<wire x1="-48.26" y1="25.4" x2="-45.72" y2="25.4" width="0.1524" layer="91"/> +<pinref part="R85" gate="G$1" pin="1"/> +<label x="-45.72" y="25.4" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="FPGA_CFG_MISO1" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L1N_T0_D01_DIN_14"/> +<wire x1="-76.2" y1="48.26" x2="-58.42" y2="48.26" width="0.1524" layer="91"/> +<pinref part="R84" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_CFG_MOSI1" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L1P_T0_D00_MOSI_14"/> +<wire x1="-76.2" y1="50.8" x2="-58.42" y2="50.8" width="0.1524" layer="91"/> +<pinref part="R83" gate="G$1" pin="2"/> +</segment> +</net> +<net name="FPGA_CFG_CS_N1" class="0"> +<segment> +<pinref part="U13" gate="B14" pin="IO_L6P_T0_FCS_B_14"/> +<wire x1="-76.2" y1="25.4" x2="-58.42" y2="25.4" width="0.1524" layer="91"/> +<pinref part="R85" gate="G$1" pin="2"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA power and ground</description> +<plain> +<text x="63.5" y="66.04" size="1.778" layer="91">*) Power - AUX</text> +<text x="-15.24" y="66.04" size="1.778" layer="91">*) Power - CORE & BRAM</text> +<text x="-91.44" y="68.58" size="1.778" layer="91">*) Ground Pins</text> +<text x="83.82" y="-68.58" size="1.9304" layer="94">FPGA power and ground</text> +</plain> +<instances> +<instance part="U13" gate="BGNDA" x="-101.6" y="-2.54"/> +<instance part="U13" gate="BGNDB" x="-55.88" y="-2.54"/> +<instance part="U13" gate="BVCCAUX" x="76.2" y="48.26"/> +<instance part="U13" gate="BVCCBRAM" x="0" y="50.8"/> +<instance part="U13" gate="BVCCINT" x="0" y="15.24" rot="MR180"/> +<instance part="SUPPLY125" gate="GND" x="-91.44" y="-66.04"/> +<instance part="SUPPLY126" gate="GND" x="-45.72" y="-63.5"/> +<instance part="FRAME22" gate="G$1" x="-132.08" y="-88.9"/> +<instance part="P+75" gate="VCC" x="10.16" y="60.96" smashed="yes"/> +<instance part="P+76" gate="VCC" x="86.36" y="60.96" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="U13" gate="BGNDA" pin="GND@43"/> +<wire x1="-96.52" y1="-58.42" x2="-91.44" y2="-58.42" width="0.1524" layer="91"/> +<pinref part="SUPPLY125" gate="GND" pin="GND"/> +<wire x1="-91.44" y1="-58.42" x2="-91.44" y2="-63.5" width="0.1524" layer="91"/> +<pinref part="U13" gate="BGNDA" pin="GND@42"/> +<wire x1="-96.52" y1="-55.88" x2="-91.44" y2="-55.88" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="-55.88" x2="-91.44" y2="-58.42" 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x2="10.16" y2="12.7" width="0.1524" layer="91"/> +<wire x1="10.16" y1="12.7" x2="10.16" y2="15.24" width="0.1524" layer="91"/> +<wire x1="10.16" y1="15.24" x2="10.16" y2="17.78" width="0.1524" layer="91"/> +<wire x1="5.08" y1="15.24" x2="10.16" y2="15.24" width="0.1524" layer="91"/> +<junction x="10.16" y="15.24"/> +<pinref part="U13" gate="BVCCINT" pin="VCCINT@5"/> +<wire x1="5.08" y1="12.7" x2="10.16" y2="12.7" width="0.1524" layer="91"/> +<junction x="10.16" y="12.7"/> +<pinref part="U13" gate="BVCCINT" pin="VCCINT@4"/> +<wire x1="5.08" y1="10.16" x2="10.16" y2="10.16" width="0.1524" layer="91"/> +<junction x="10.16" y="10.16"/> +<pinref part="U13" gate="BVCCINT" pin="VCCINT@3"/> +<wire x1="5.08" y1="7.62" x2="10.16" y2="7.62" width="0.1524" layer="91"/> +<junction x="10.16" y="7.62"/> +<pinref part="U13" gate="BVCCINT" pin="VCCINT@2"/> +<wire x1="5.08" y1="5.08" x2="10.16" y2="5.08" width="0.1524" layer="91"/> +<junction x="10.16" y="5.08"/> +<pinref part="U13" gate="BVCCINT" pin="VCCINT@1"/> +<wire x1="5.08" y1="2.54" x2="10.16" y2="2.54" width="0.1524" layer="91"/> +<junction x="10.16" y="2.54"/> +<pinref part="P+75" gate="VCC" pin="VCC"/> +</segment> +</net> +<net name="FPGA_VCCAUX_1V8" class="0"> +<segment> +<pinref part="U13" gate="BVCCAUX" pin="VCCAUX@0"/> +<wire x1="81.28" y1="53.34" x2="86.36" y2="53.34" width="0.1524" layer="91"/> +<wire x1="86.36" y1="53.34" x2="86.36" y2="50.8" width="0.1524" layer="91"/> +<pinref part="U13" gate="BVCCAUX" pin="VCCAUX@4"/> +<wire x1="86.36" y1="50.8" x2="86.36" y2="48.26" width="0.1524" layer="91"/> +<wire x1="86.36" y1="48.26" x2="86.36" y2="45.72" width="0.1524" layer="91"/> +<wire x1="86.36" y1="45.72" x2="86.36" y2="43.18" width="0.1524" layer="91"/> +<wire x1="86.36" y1="43.18" x2="81.28" y2="43.18" width="0.1524" layer="91"/> +<pinref part="U13" gate="BVCCAUX" pin="VCCAUX@3"/> +<wire x1="81.28" y1="45.72" x2="86.36" y2="45.72" width="0.1524" layer="91"/> +<junction x="86.36" y="45.72"/> +<pinref part="U13" gate="BVCCAUX" pin="VCCAUX@2"/> +<wire x1="81.28" y1="48.26" x2="86.36" y2="48.26" width="0.1524" layer="91"/> +<junction x="86.36" y="48.26"/> +<pinref part="U13" gate="BVCCAUX" pin="VCCAUX@1"/> +<wire x1="81.28" y1="50.8" x2="86.36" y2="50.8" width="0.1524" layer="91"/> +<junction x="86.36" y="50.8"/> +<junction x="86.36" y="53.34"/> +<wire x1="86.36" y1="53.34" x2="86.36" y2="58.42" width="0.1524" layer="91"/> +<label x="88.9" y="58.42" size="1.778" layer="95"/> +<pinref part="P+76" gate="VCC" pin="VCC"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA CORE and AUX capacitors</description> +<plain> +<text x="40.64" y="48.26" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA + package +<-- Place large 47 uF and 330 uF caps not far + from the BGA package + +<-- Distribute smaller caps evenly under the BGA package +<-- Distribute larger caps evenly around the BGA package</text> +<text x="-66.04" y="76.2" size="1.778" layer="91">*) Decoupling capacitors for VCCINT and VCCBRAM</text> +<text x="30.48" y="-33.02" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA package +<-- Place large 47 uF caps not far from the BGA package + +<-- Try to place smaller caps next to FPGA balls</text> +<text x="-66.04" y="-7.62" size="1.778" layer="91">*) Decoupling capacitors for VCCAUX</text> +<text x="88.9" y="-68.58" size="1.4224" layer="94">FPGA CORE and AUX capacitors</text> +</plain> +<instances> +<instance part="C123" gate="G$1" x="-104.14" y="63.5"> +<attribute name="DIELECTRIC" x="-104.14" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-104.14" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-104.14" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY127" gate="GND" x="-104.14" y="53.34"/> +<instance part="SUPPLY131" gate="GND" x="-91.44" y="53.34"/> +<instance part="SUPPLY145" gate="GND" x="-43.18" y="30.48"/> +<instance part="SUPPLY149" gate="GND" x="-30.48" y="30.48"/> +<instance part="SUPPLY153" gate="GND" x="-17.78" y="30.48"/> +<instance part="SUPPLY157" gate="GND" x="-5.08" y="30.48"/> +<instance part="SUPPLY161" gate="GND" x="7.62" y="30.48"/> +<instance part="SUPPLY165" gate="GND" x="20.32" y="30.48"/> +<instance part="C140" gate="G$1" x="-43.18" y="63.5"> +<attribute name="DIELECTRIC" x="-43.18" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-43.18" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-43.18" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY144" gate="GND" x="-43.18" y="53.34"/> +<instance part="SUPPLY148" gate="GND" x="-30.48" y="53.34"/> +<instance part="SUPPLY152" gate="GND" x="-17.78" y="53.34"/> +<instance part="SUPPLY156" gate="GND" x="-5.08" y="53.34"/> +<instance part="SUPPLY160" gate="GND" x="7.62" y="53.34"/> +<instance part="SUPPLY164" gate="GND" x="20.32" y="53.34"/> +<instance part="SUPPLY137" gate="GND" x="-73.66" y="53.34"/> +<instance part="SUPPLY141" gate="GND" x="-60.96" y="53.34"/> +<instance part="SUPPLY138" gate="GND" x="-66.04" y="30.48"/> +<instance part="SUPPLY134" gate="GND" x="-78.74" y="30.48"/> +<instance part="SUPPLY132" gate="GND" x="-91.44" y="30.48"/> +<instance part="SUPPLY128" gate="GND" x="-104.14" y="30.48"/> +<instance part="SUPPLY139" gate="GND" x="-66.04" y="7.62"/> +<instance part="SUPPLY135" gate="GND" x="-78.74" y="7.62"/> +<instance part="SUPPLY133" gate="GND" x="-91.44" y="7.62"/> +<instance part="C125" gate="G$1" x="-104.14" y="17.78"> +<attribute name="DIELECTRIC" x="-104.14" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-104.14" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-104.14" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY129" gate="GND" x="-104.14" y="7.62"/> +<instance part="SUPPLY154" gate="GND" x="-15.24" y="7.62"/> +<instance part="SUPPLY150" gate="GND" x="-27.94" y="7.62"/> +<instance part="SUPPLY146" gate="GND" x="-40.64" y="7.62"/> +<instance part="SUPPLY142" gate="GND" x="-53.34" y="7.62"/> +<instance part="SUPPLY167" gate="GND" x="35.56" y="7.62"/> +<instance part="SUPPLY166" gate="GND" x="22.86" y="7.62"/> +<instance part="SUPPLY162" gate="GND" x="10.16" y="7.62"/> +<instance part="SUPPLY158" gate="GND" x="-2.54" y="7.62"/> +<instance part="SUPPLY168" gate="GND" x="48.26" y="7.62"/> +<instance part="SUPPLY130" gate="GND" x="-96.52" y="-33.02"/> +<instance part="SUPPLY136" gate="GND" x="-78.74" y="-33.02"/> +<instance part="SUPPLY140" gate="GND" x="-66.04" y="-33.02"/> +<instance part="SUPPLY143" gate="GND" x="-53.34" y="-33.02"/> +<instance part="SUPPLY147" gate="GND" x="-35.56" y="-33.02"/> +<instance part="SUPPLY151" gate="GND" x="-22.86" y="-33.02"/> +<instance part="SUPPLY155" gate="GND" x="-10.16" y="-33.02"/> +<instance part="SUPPLY159" gate="GND" x="2.54" y="-33.02"/> +<instance part="SUPPLY163" gate="GND" x="15.24" y="-33.02"/> +<instance part="FRAME23" gate="G$1" x="-127" y="-88.9"/> +<instance part="C133" gate="G$1" x="-73.66" y="63.5"> +<attribute name="DIELECTRIC" x="-73.66" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-73.66" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-73.66" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C127" gate="G$1" x="-91.44" y="63.5"> +<attribute name="DIELECTRIC" x="-91.44" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-91.44" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-91.44" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C124" gate="G$1" x="-104.14" y="40.64"> +<attribute name="DIELECTRIC" x="-104.14" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-104.14" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-104.14" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C128" gate="G$1" x="-91.44" y="40.64"> +<attribute name="DIELECTRIC" x="-91.44" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-91.44" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-91.44" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C130" gate="G$1" x="-78.74" y="40.64"> +<attribute name="DIELECTRIC" x="-78.74" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C134" gate="G$1" x="-66.04" y="40.64"> +<attribute name="DIELECTRIC" x="-66.04" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C129" gate="G$1" x="-91.44" y="17.78"> +<attribute name="DIELECTRIC" x="-91.44" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-91.44" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-91.44" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C131" gate="G$1" x="-78.74" y="17.78"> +<attribute name="DIELECTRIC" x="-78.74" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C135" gate="G$1" x="-66.04" y="17.78"> +<attribute name="DIELECTRIC" x="-66.04" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C138" gate="G$1" x="-53.34" y="17.78"> +<attribute name="DIELECTRIC" x="-53.34" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-53.34" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-53.34" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C142" gate="G$1" x="-40.64" y="17.78"> +<attribute name="DIELECTRIC" x="-40.64" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-40.64" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-40.64" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C146" gate="G$1" x="-27.94" y="17.78"> +<attribute name="DIELECTRIC" x="-27.94" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-27.94" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-27.94" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C150" gate="G$1" x="-15.24" y="17.78"> +<attribute name="DIELECTRIC" x="-15.24" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-15.24" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-15.24" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C154" gate="G$1" x="-2.54" y="17.78"> +<attribute name="DIELECTRIC" x="-2.54" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-2.54" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-2.54" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C158" gate="G$1" x="10.16" y="17.78"> +<attribute name="DIELECTRIC" x="10.16" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="10.16" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="10.16" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C162" gate="G$1" x="22.86" y="17.78"> +<attribute name="DIELECTRIC" x="22.86" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="22.86" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="22.86" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C163" gate="G$1" x="35.56" y="17.78"> +<attribute name="DIELECTRIC" x="35.56" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="35.56" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="35.56" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C143" gate="G$1" x="-35.56" y="-22.86"> +<attribute name="DIELECTRIC" x="-35.56" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-35.56" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-35.56" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C147" gate="G$1" x="-22.86" y="-22.86"> +<attribute name="DIELECTRIC" x="-22.86" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-22.86" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-22.86" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C151" gate="G$1" x="-10.16" y="-22.86"> +<attribute name="DIELECTRIC" x="-10.16" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-10.16" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-10.16" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C155" gate="G$1" x="2.54" y="-22.86"> +<attribute name="DIELECTRIC" x="2.54" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="2.54" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="2.54" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C159" gate="G$1" x="15.24" y="-22.86"> +<attribute name="DIELECTRIC" x="15.24" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="15.24" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="15.24" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C164" gate="G$1" x="48.26" y="17.78"> +<attribute name="DIELECTRIC" x="48.26" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="48.26" y="17.78" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="48.26" y="17.78" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C144" gate="G$1" x="-30.48" y="63.5"> +<attribute name="DIELECTRIC" x="-30.48" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C148" gate="G$1" x="-17.78" y="63.5"> +<attribute name="DIELECTRIC" x="-17.78" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-17.78" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-17.78" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C152" gate="G$1" x="-5.08" y="63.5"> +<attribute name="DIELECTRIC" x="-5.08" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-5.08" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-5.08" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C156" gate="G$1" x="7.62" y="63.5"> +<attribute name="DIELECTRIC" x="7.62" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="7.62" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="7.62" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C160" gate="G$1" x="20.32" y="63.5"> +<attribute name="DIELECTRIC" x="20.32" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="20.32" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="20.32" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C141" gate="G$1" x="-43.18" y="40.64"> +<attribute name="DIELECTRIC" x="-43.18" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-43.18" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-43.18" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C145" gate="G$1" x="-30.48" y="40.64"> +<attribute name="DIELECTRIC" x="-30.48" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-30.48" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-30.48" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C149" gate="G$1" x="-17.78" y="40.64"> +<attribute name="DIELECTRIC" x="-17.78" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-17.78" y="40.64" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-17.78" y="40.64" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C153" gate="G$1" x="-5.08" y="40.64"> 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x="-78.74" y="-22.86"> +<attribute name="DIELECTRIC" x="-78.74" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-78.74" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-78.74" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C136" gate="G$1" x="-66.04" y="-22.86"> +<attribute name="DIELECTRIC" x="-66.04" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-66.04" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-66.04" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C139" gate="G$1" x="-53.34" y="-22.86"> +<attribute name="DIELECTRIC" x="-53.34" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-53.34" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-53.34" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C137" gate="G$1" x="-60.96" y="63.5"> +<attribute name="DIELECTRIC" x="-60.96" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-60.96" y="63.5" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-60.96" y="63.5" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C126" gate="G$1" x="-96.52" y="-22.86"> +<attribute name="DIELECTRIC" x="-96.52" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-96.52" y="-22.86" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-96.52" y="-22.86" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+77" gate="VCC" x="-116.84" y="76.2" smashed="yes"/> +<instance part="P+78" gate="VCC" x="-116.84" y="-10.16" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY127" gate="GND" pin="GND"/> +<pinref part="C123" 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width="0.1524" layer="91"/> +<wire x1="-78.74" y1="-17.78" x2="-96.52" y2="-17.78" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="-17.78" x2="-96.52" y2="-20.32" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="-20.32" x2="-78.74" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-78.74" y="-17.78"/> +<wire x1="-66.04" y1="-20.32" x2="-66.04" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-66.04" y="-17.78"/> +<wire x1="-53.34" y1="-20.32" x2="-53.34" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-53.34" y="-17.78"/> +<wire x1="-35.56" y1="-20.32" x2="-35.56" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-35.56" y="-17.78"/> +<wire x1="-22.86" y1="-20.32" x2="-22.86" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-22.86" y="-17.78"/> +<wire x1="-10.16" y1="-20.32" x2="-10.16" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-10.16" y="-17.78"/> +<wire x1="2.54" y1="-20.32" x2="2.54" y2="-17.78" width="0.1524" layer="91"/> +<junction x="2.54" y="-17.78"/> +<pinref part="C143" gate="G$1" pin="1"/> +<pinref part="C147" gate="G$1" pin="1"/> +<pinref part="C151" gate="G$1" pin="1"/> +<pinref part="C155" gate="G$1" pin="1"/> +<pinref part="C159" gate="G$1" pin="1"/> +<pinref part="C132" gate="G$1" pin="1"/> +<pinref part="C136" gate="G$1" pin="1"/> +<pinref part="C139" gate="G$1" pin="1"/> +<pinref part="C126" gate="G$1" pin="1"/> +<wire x1="-116.84" y1="-17.78" x2="-96.52" y2="-17.78" width="0.1524" layer="91"/> +<junction x="-96.52" y="-17.78"/> +</segment> +</net> +<net name="FPGA_VCCINT_1V0" class="0"> +<segment> +<label x="-111.76" y="73.66" size="1.778" layer="95"/> +<wire x1="-116.84" y1="68.58" x2="-116.84" y2="73.66" width="0.1524" layer="91"/> +<pinref part="P+77" gate="VCC" pin="VCC"/> +<wire x1="-91.44" y1="68.58" x2="-91.44" y2="66.04" width="0.1524" layer="91"/> +<pinref part="C123" gate="G$1" pin="+"/> +<wire x1="-104.14" y1="66.04" x2="-104.14" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="68.58" x2="-91.44" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="66.04" x2="-73.66" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-73.66" y1="68.58" x2="-91.44" y2="68.58" width="0.1524" layer="91"/> +<junction x="-91.44" y="68.58"/> +<wire x1="-60.96" y1="66.04" x2="-60.96" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="68.58" x2="-73.66" y2="68.58" width="0.1524" layer="91"/> +<junction x="-73.66" y="68.58"/> +<wire x1="20.32" y1="66.04" x2="20.32" y2="68.58" width="0.1524" layer="91"/> +<wire x1="20.32" y1="68.58" x2="7.62" y2="68.58" width="0.1524" layer="91"/> +<junction x="-60.96" y="68.58"/> +<pinref part="C140" gate="G$1" pin="1"/> +<wire x1="7.62" y1="68.58" x2="-5.08" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="68.58" x2="-17.78" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="68.58" x2="-30.48" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="68.58" x2="-43.18" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="68.58" x2="-60.96" y2="68.58" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="66.04" x2="-43.18" y2="68.58" width="0.1524" layer="91"/> +<junction x="-43.18" y="68.58"/> +<wire x1="-30.48" y1="66.04" x2="-30.48" y2="68.58" width="0.1524" layer="91"/> +<junction x="-30.48" y="68.58"/> +<wire x1="-17.78" y1="66.04" x2="-17.78" y2="68.58" width="0.1524" layer="91"/> +<junction x="-17.78" y="68.58"/> +<wire x1="-5.08" y1="66.04" x2="-5.08" y2="68.58" width="0.1524" layer="91"/> +<junction x="-5.08" y="68.58"/> +<wire x1="7.62" y1="66.04" x2="7.62" y2="68.58" width="0.1524" layer="91"/> +<junction x="7.62" y="68.58"/> +<wire x1="20.32" y1="68.58" x2="33.02" y2="68.58" width="0.1524" layer="91"/> +<junction x="20.32" y="68.58"/> +<wire x1="33.02" y1="68.58" x2="33.02" y2="45.72" width="0.1524" layer="91"/> +<wire x1="20.32" y1="43.18" x2="20.32" y2="45.72" width="0.1524" layer="91"/> +<wire x1="7.62" y1="43.18" x2="7.62" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-43.18" y1="43.18" x2="-43.18" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="43.18" x2="-5.08" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-5.08" y1="45.72" x2="-17.78" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-17.78" y1="45.72" x2="-30.48" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="45.72" x2="-43.18" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-30.48" y1="43.18" x2="-30.48" y2="45.72" width="0.1524" layer="91"/> +<junction x="-30.48" y="45.72"/> +<wire x1="-17.78" y1="43.18" x2="-17.78" y2="45.72" width="0.1524" layer="91"/> +<junction x="-17.78" y="45.72"/> +<wire x1="7.62" y1="45.72" x2="-5.08" y2="45.72" width="0.1524" layer="91"/> +<junction x="-5.08" y="45.72"/> +<wire x1="20.32" y1="45.72" x2="7.62" y2="45.72" width="0.1524" layer="91"/> +<junction x="7.62" y="45.72"/> +<wire x1="33.02" y1="45.72" x2="20.32" y2="45.72" width="0.1524" layer="91"/> +<junction x="20.32" y="45.72"/> +<wire x1="-104.14" y1="43.18" x2="-104.14" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-104.14" y1="45.72" x2="-91.44" y2="45.72" width="0.1524" layer="91"/> +<junction x="-43.18" y="45.72"/> +<wire x1="-91.44" y1="45.72" x2="-78.74" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="45.72" x2="-66.04" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="45.72" x2="-43.18" y2="45.72" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="43.18" x2="-91.44" y2="45.72" width="0.1524" layer="91"/> +<junction x="-91.44" y="45.72"/> +<wire x1="-78.74" y1="45.72" x2="-78.74" y2="43.18" width="0.1524" layer="91"/> +<junction x="-78.74" y="45.72"/> +<wire x1="-66.04" y1="43.18" x2="-66.04" y2="45.72" width="0.1524" layer="91"/> +<junction x="-66.04" y="45.72"/> +<wire x1="-104.14" y1="45.72" x2="-116.84" y2="45.72" width="0.1524" layer="91"/> +<junction x="-104.14" y="45.72"/> +<wire x1="-116.84" y1="45.72" x2="-116.84" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-116.84" y1="22.86" x2="-104.14" y2="22.86" width="0.1524" layer="91"/> +<pinref part="C125" gate="G$1" pin="1"/> +<wire x1="-104.14" y1="20.32" x2="-104.14" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="20.32" x2="-91.44" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-91.44" y1="22.86" x2="-104.14" y2="22.86" width="0.1524" layer="91"/> +<junction x="-104.14" y="22.86"/> +<wire x1="-78.74" y1="20.32" x2="-78.74" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-78.74" y1="22.86" x2="-91.44" y2="22.86" width="0.1524" layer="91"/> +<junction x="-91.44" y="22.86"/> +<wire x1="22.86" y1="20.32" x2="22.86" y2="22.86" width="0.1524" layer="91"/> +<wire x1="22.86" y1="22.86" x2="10.16" y2="22.86" width="0.1524" layer="91"/> +<junction x="-78.74" y="22.86"/> +<wire x1="10.16" y1="22.86" x2="-2.54" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="22.86" x2="-15.24" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-15.24" y1="22.86" x2="-27.94" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-27.94" y1="22.86" x2="-40.64" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-40.64" y1="22.86" x2="-53.34" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-53.34" y1="22.86" x2="-66.04" y2="22.86" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="22.86" x2="-78.74" y2="22.86" width="0.1524" layer="91"/> +<wire x1="48.26" y1="20.32" x2="48.26" y2="22.86" width="0.1524" layer="91"/> +<wire x1="48.26" y1="22.86" x2="35.56" y2="22.86" width="0.1524" layer="91"/> +<junction x="22.86" y="22.86"/> +<wire x1="35.56" y1="22.86" x2="22.86" y2="22.86" width="0.1524" layer="91"/> +<wire x1="35.56" y1="20.32" x2="35.56" y2="22.86" width="0.1524" layer="91"/> +<junction x="35.56" y="22.86"/> +<wire x1="-66.04" y1="20.32" x2="-66.04" y2="22.86" width="0.1524" layer="91"/> +<junction x="-66.04" y="22.86"/> +<wire x1="-53.34" y1="20.32" x2="-53.34" y2="22.86" width="0.1524" layer="91"/> +<junction x="-53.34" y="22.86"/> +<wire x1="-40.64" y1="20.32" x2="-40.64" y2="22.86" width="0.1524" layer="91"/> +<junction x="-40.64" y="22.86"/> +<wire x1="-27.94" y1="20.32" x2="-27.94" y2="22.86" width="0.1524" layer="91"/> +<junction x="-27.94" y="22.86"/> +<wire x1="-15.24" y1="20.32" x2="-15.24" y2="22.86" width="0.1524" layer="91"/> +<junction x="-15.24" y="22.86"/> +<wire x1="-2.54" y1="20.32" x2="-2.54" y2="22.86" width="0.1524" layer="91"/> +<junction x="-2.54" y="22.86"/> +<wire x1="10.16" y1="20.32" x2="10.16" y2="22.86" width="0.1524" layer="91"/> +<junction x="10.16" y="22.86"/> +<pinref part="C133" gate="G$1" pin="1"/> +<pinref part="C127" gate="G$1" pin="+"/> +<pinref part="C124" gate="G$1" pin="1"/> +<pinref part="C128" gate="G$1" pin="1"/> +<pinref part="C130" gate="G$1" pin="1"/> +<pinref part="C134" gate="G$1" pin="1"/> +<pinref part="C129" gate="G$1" pin="1"/> +<pinref part="C131" gate="G$1" pin="1"/> +<pinref part="C135" gate="G$1" pin="1"/> +<pinref part="C138" gate="G$1" pin="1"/> +<pinref part="C142" gate="G$1" pin="1"/> +<pinref part="C146" gate="G$1" pin="1"/> +<pinref part="C150" gate="G$1" pin="1"/> +<pinref part="C154" gate="G$1" pin="1"/> +<pinref part="C158" gate="G$1" pin="1"/> +<pinref part="C162" gate="G$1" pin="1"/> +<pinref part="C163" gate="G$1" pin="1"/> +<pinref part="C164" gate="G$1" pin="1"/> +<pinref part="C144" gate="G$1" pin="1"/> +<pinref part="C148" gate="G$1" pin="1"/> +<pinref part="C152" gate="G$1" pin="1"/> +<pinref part="C156" gate="G$1" pin="1"/> +<pinref part="C160" gate="G$1" pin="1"/> +<pinref part="C141" gate="G$1" pin="1"/> +<pinref part="C145" gate="G$1" pin="1"/> +<pinref part="C149" gate="G$1" pin="1"/> +<pinref part="C153" gate="G$1" pin="1"/> +<pinref part="C157" gate="G$1" pin="1"/> +<pinref part="C161" gate="G$1" pin="1"/> +<pinref part="C137" gate="G$1" pin="1"/> +<wire x1="-116.84" y1="68.58" x2="-104.14" y2="68.58" width="0.1524" layer="91"/> +<junction x="-104.14" y="68.58"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA VCCO bypass capacitors</description> +<plain> +<text x="30.48" y="50.8" size="1.778" layer="91"><-- Place small 0.47 uF caps right under the BGA package +<-- Place medium 4.7 uF caps very close to the BGA package +<-- Place large 47 uF caps not far from the BGA package + +<-- Place one of four 47 uF caps on every side of the BGA p. +<-- Distribute six sets of caps among six FPGA I/O banks</text> +<text x="-73.66" y="73.66" size="1.778" layer="91">*) Decoupling capacitors for VCCO</text> +<text x="68.58" y="-71.12" size="1.6764" layer="94">FPGA VCCO bypass capacitors</text> +</plain> +<instances> +<instance part="SUPPLY169" gate="GND" x="-111.76" y="50.8"/> +<instance part="SUPPLY170" gate="GND" x="-99.06" y="50.8"/> +<instance part="SUPPLY171" gate="GND" x="-86.36" y="50.8"/> +<instance part="SUPPLY172" gate="GND" x="-73.66" y="50.8"/> +<instance part="SUPPLY173" gate="GND" x="-50.8" y="50.8"/> +<instance part="SUPPLY179" gate="GND" x="-38.1" y="50.8"/> +<instance part="SUPPLY185" gate="GND" x="-20.32" y="50.8"/> +<instance part="SUPPLY191" gate="GND" x="-7.62" y="50.8"/> +<instance part="SUPPLY197" gate="GND" x="5.08" y="50.8"/> +<instance part="SUPPLY203" gate="GND" x="17.78" y="50.8"/> +<instance part="SUPPLY174" gate="GND" x="-50.8" y="27.94"/> +<instance part="SUPPLY180" gate="GND" x="-38.1" y="27.94"/> +<instance part="SUPPLY186" gate="GND" x="-20.32" y="27.94"/> +<instance part="SUPPLY192" gate="GND" x="-7.62" y="27.94"/> +<instance part="SUPPLY198" gate="GND" x="5.08" y="27.94"/> +<instance part="SUPPLY204" gate="GND" x="17.78" y="27.94"/> +<instance part="SUPPLY175" gate="GND" x="-50.8" y="5.08"/> +<instance part="SUPPLY181" gate="GND" x="-38.1" y="5.08"/> +<instance part="SUPPLY187" gate="GND" x="-20.32" y="5.08"/> +<instance part="SUPPLY193" gate="GND" x="-7.62" y="5.08"/> +<instance part="SUPPLY199" gate="GND" x="5.08" y="5.08"/> +<instance part="SUPPLY205" gate="GND" x="17.78" y="5.08"/> +<instance part="SUPPLY176" gate="GND" x="-50.8" y="-17.78"/> +<instance part="SUPPLY182" gate="GND" x="-38.1" y="-17.78"/> +<instance part="SUPPLY188" gate="GND" x="-20.32" y="-17.78"/> +<instance part="SUPPLY194" gate="GND" x="-7.62" y="-17.78"/> +<instance part="SUPPLY200" gate="GND" x="5.08" y="-17.78"/> +<instance part="SUPPLY206" gate="GND" x="17.78" y="-17.78"/> +<instance part="SUPPLY177" gate="GND" x="-50.8" y="-40.64"/> +<instance part="SUPPLY183" gate="GND" x="-38.1" y="-40.64"/> +<instance part="SUPPLY189" gate="GND" x="-20.32" y="-40.64"/> +<instance part="SUPPLY195" gate="GND" x="-7.62" y="-40.64"/> +<instance part="SUPPLY201" gate="GND" x="5.08" y="-40.64"/> +<instance part="SUPPLY207" gate="GND" x="17.78" y="-40.64"/> +<instance part="SUPPLY178" gate="GND" x="-50.8" y="-63.5"/> +<instance part="SUPPLY184" gate="GND" x="-38.1" y="-63.5"/> +<instance part="SUPPLY190" gate="GND" x="-20.32" y="-63.5"/> +<instance part="SUPPLY196" gate="GND" x="-7.62" y="-63.5"/> +<instance part="SUPPLY202" gate="GND" x="5.08" y="-63.5"/> +<instance part="SUPPLY208" gate="GND" x="17.78" y="-63.5"/> +<instance part="FRAME24" gate="G$1" x="-129.54" y="-91.44"/> +<instance part="C181" gate="G$1" x="-20.32" y="60.96"> +<attribute name="DIELECTRIC" x="-20.32" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-20.32" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-20.32" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C187" gate="G$1" x="-7.62" y="60.96"> +<attribute name="DIELECTRIC" x="-7.62" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-7.62" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-7.62" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C193" gate="G$1" x="5.08" y="60.96"> +<attribute name="DIELECTRIC" x="5.08" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="5.08" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="5.08" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C199" gate="G$1" x="17.78" y="60.96"> +<attribute name="DIELECTRIC" x="17.78" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="17.78" y="60.96" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="60.96" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C182" gate="G$1" x="-20.32" y="38.1"> +<attribute name="DIELECTRIC" x="-20.32" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-20.32" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-20.32" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C188" gate="G$1" x="-7.62" y="38.1"> +<attribute name="DIELECTRIC" x="-7.62" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-7.62" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-7.62" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C194" gate="G$1" x="5.08" y="38.1"> +<attribute name="DIELECTRIC" x="5.08" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="5.08" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="5.08" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C200" gate="G$1" x="17.78" y="38.1"> +<attribute name="DIELECTRIC" x="17.78" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="17.78" y="38.1" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="17.78" y="38.1" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C183" gate="G$1" x="-20.32" y="15.24"> +<attribute name="DIELECTRIC" x="-20.32" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-20.32" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-20.32" y="15.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C189" gate="G$1" x="-7.62" y="15.24"> +<attribute name="DIELECTRIC" x="-7.62" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-7.62" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-7.62" y="15.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C195" gate="G$1" x="5.08" y="15.24"> +<attribute name="DIELECTRIC" x="5.08" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="5.08" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="5.08" y="15.24" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C201" gate="G$1" x="17.78" y="15.24"> +<attribute name="DIELECTRIC" x="17.78" y="15.24" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="17.78" 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pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY205" gate="GND" pin="GND"/> +<wire x1="17.78" y1="10.16" x2="17.78" y2="7.62" width="0.1524" layer="91"/> +<pinref part="C201" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY176" gate="GND" pin="GND"/> +<wire x1="-50.8" y1="-15.24" x2="-50.8" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="C172" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY182" gate="GND" pin="GND"/> +<wire x1="-38.1" y1="-12.7" x2="-38.1" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="C178" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY188" gate="GND" pin="GND"/> +<wire x1="-20.32" y1="-15.24" x2="-20.32" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="C184" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY194" gate="GND" pin="GND"/> +<wire x1="-7.62" y1="-12.7" x2="-7.62" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="C190" gate="G$1" pin="2"/> +</segment> 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layer="91"/> +<wire x1="5.08" y1="-48.26" x2="-7.62" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="-7.62" y1="-48.26" x2="-20.32" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="-20.32" y1="-48.26" x2="-38.1" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="-48.26" x2="-50.8" y2="-48.26" width="0.1524" layer="91"/> +<wire x1="-38.1" y1="-50.8" x2="-38.1" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-38.1" y="-48.26"/> +<wire x1="-20.32" y1="-50.8" x2="-20.32" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-20.32" y="-48.26"/> +<wire x1="-7.62" y1="-50.8" x2="-7.62" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-7.62" y="-48.26"/> +<wire x1="5.08" y1="-50.8" x2="5.08" y2="-48.26" width="0.1524" layer="91"/> +<junction x="5.08" y="-48.26"/> +<wire x1="-50.8" y1="-48.26" x2="-60.96" y2="-48.26" width="0.1524" layer="91"/> +<junction x="-50.8" y="-48.26"/> +<wire x1="-60.96" y1="-48.26" x2="-60.96" y2="-25.4" width="0.1524" layer="91"/> +<junction x="-60.96" y="-25.4"/> +<pinref part="C181" gate="G$1" pin="1"/> +<pinref part="C187" gate="G$1" pin="1"/> +<pinref part="C193" gate="G$1" pin="1"/> +<pinref part="C199" gate="G$1" pin="1"/> +<pinref part="C182" gate="G$1" pin="1"/> +<pinref part="C188" gate="G$1" pin="1"/> +<pinref part="C194" gate="G$1" pin="1"/> +<pinref part="C200" gate="G$1" pin="1"/> +<pinref part="C183" gate="G$1" pin="1"/> +<pinref part="C189" gate="G$1" pin="1"/> +<pinref part="C195" gate="G$1" pin="1"/> +<pinref part="C201" gate="G$1" pin="1"/> +<pinref part="C184" gate="G$1" pin="1"/> +<pinref part="C190" gate="G$1" pin="1"/> +<pinref part="C196" gate="G$1" pin="1"/> +<pinref part="C202" gate="G$1" pin="1"/> +<pinref part="C185" gate="G$1" pin="1"/> +<pinref part="C191" gate="G$1" pin="1"/> +<pinref part="C197" gate="G$1" pin="1"/> +<pinref part="C203" gate="G$1" pin="1"/> +<pinref part="C186" gate="G$1" pin="1"/> +<pinref part="C192" gate="G$1" pin="1"/> +<pinref part="C198" gate="G$1" pin="1"/> +<pinref part="C204" gate="G$1" pin="1"/> +<pinref part="C169" gate="G$1" pin="1"/> +<pinref part="C175" gate="G$1" pin="1"/> +<pinref part="C176" gate="G$1" pin="1"/> +<pinref part="C170" gate="G$1" pin="1"/> +<pinref part="C171" gate="G$1" pin="1"/> +<pinref part="C177" gate="G$1" pin="1"/> +<pinref part="C178" gate="G$1" pin="1"/> +<pinref part="C172" gate="G$1" pin="1"/> +<pinref part="C173" gate="G$1" pin="1"/> +<pinref part="C179" gate="G$1" pin="1"/> +<pinref part="C180" gate="G$1" pin="1"/> +<pinref part="C174" gate="G$1" pin="1"/> +<pinref part="C165" gate="G$1" pin="1"/> +<pinref part="C166" gate="G$1" pin="1"/> +<pinref part="C167" gate="G$1" pin="1"/> +<pinref part="C168" gate="G$1" pin="1"/> +<wire x1="-121.92" y1="66.04" x2="-111.76" y2="66.04" width="0.1524" layer="91"/> +<junction x="-111.76" y="66.04"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA CORE voltage regulator</description> +<plain> +<text x="-33.02" y="73.66" size="1.778" layer="91">*) FPGA Power Subsystem -- CORE</text> +<text x="38.1" y="38.1" size="1.778" layer="91">*) VCCINT = 0.6V x (1 + 150 / 226) = 0.998V + +*) OCP_ADJ is not used (default over-current threshold) + +*) MARx are not used (output at nominal 100%) + +*) S_IN/S_OUT are not used (single regulator mode) + +*) S_DELAY is not used (single regulator mode) + +*) M/S is not used (parallel operation not needed) + +*) EA_OUT is not used (default control loop) + +*) Minimal load current is 0A, but we still place +load of 100 Ohms just in case (gives 10 mA)</text> +<text x="83.82" y="-71.12" size="1.6764" layer="94">FPGA CORE voltage regulators</text> +</plain> +<instances> +<instance part="FRAME25" gate="G$1" x="-132.08" y="-91.44"/> +<instance part="SUPPLY212" gate="GND" x="-35.56" y="-66.04"/> +<instance part="SUPPLY213" gate="GND" x="-22.86" y="-66.04"/> +<instance part="C207" gate="G$1" x="-55.88" y="-55.88" smashed="yes"> +<attribute name="RATED_VOLTAGE" x="-55.88" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-55.88" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="DIELECTRIC" x="-55.88" y="-55.88" size="1.778" layer="96" display="off"/> +<attribute name="NAME" x="-64.516" y="-55.499" size="1.778" layer="95"/> +<attribute name="VALUE" x="-69.596" y="-60.579" size="1.778" layer="96"/> +</instance> +<instance part="SUPPLY211" gate="GND" x="-55.88" y="-66.04"/> +<instance part="R66" gate="G$1" x="-71.12" y="7.62" rot="R90"> +<attribute name="TOLERANCE" x="-71.12" y="7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C205" gate="G$1" x="-96.52" y="10.16"> +<attribute name="DIELECTRIC" x="-96.52" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-96.52" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-96.52" y="10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C206" gate="G$1" x="-86.36" y="10.16"> +<attribute name="DIELECTRIC" x="-86.36" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-86.36" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-86.36" y="10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="SUPPLY209" gate="GND" x="-96.52" y="-2.54"/> +<instance part="SUPPLY210" gate="GND" x="-86.36" y="-2.54"/> +<instance part="R68" gate="G$1" x="7.62" y="7.62" rot="R90"> +<attribute name="TOLERANCE" x="7.62" y="7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R69" gate="G$1" x="7.62" y="-7.62" rot="R90"> +<attribute name="TOLERANCE" x="7.62" y="-7.62" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="C208" gate="G$1" x="15.24" y="10.16"> +<attribute name="DIELECTRIC" x="15.24" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="15.24" y="10.16" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="15.24" y="10.16" size="1.778" layer="96" display="off"/> +</instance> +<instance part="U16" gate="G$1" x="-30.48" y="-17.78"/> +<instance part="SUPPLY214" gate="GND" x="7.62" y="-17.78"/> +<instance part="SUPPLY215" gate="GND" x="25.4" y="-17.78"/> +<instance part="SUPPLY216" gate="GND" x="38.1" y="-17.78"/> +<instance part="FB7" gate="G$1" x="58.42" y="12.7" smashed="yes"> +<attribute name="NAME" x="54.61" y="17.78" size="1.778" layer="95"/> +</instance> +<instance part="R70" gate="G$1" x="50.8" y="-5.08" rot="R90"> +<attribute name="TOLERANCE" x="50.8" y="-5.08" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="SUPPLY217" gate="GND" x="50.8" y="-17.78"/> +<instance part="R67" gate="G$1" x="-2.54" y="-7.62" rot="R90"/> +<instance part="C209" gate="G$1" x="25.4" y="-2.54"> +<attribute name="DIELECTRIC" x="25.4" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="25.4" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="25.4" y="-2.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C210" gate="G$1" x="38.1" y="-2.54"> +<attribute name="DIELECTRIC" x="38.1" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="38.1" y="-2.54" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="38.1" y="-2.54" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+80" gate="VCC" x="-101.6" y="22.86" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY212" gate="GND" pin="GND"/> +<pinref part="U16" gate="G$1" pin="AGND"/> +</segment> +<segment> +<pinref part="SUPPLY213" gate="GND" pin="GND"/> +<pinref part="U16" gate="G$1" pin="PGND"/> +</segment> +<segment> +<pinref part="SUPPLY211" gate="GND" pin="GND"/> +<pinref part="C207" gate="G$1" pin="2"/> +<wire x1="-55.88" y1="-63.5" x2="-55.88" y2="-60.96" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C205" gate="G$1" pin="2"/> +<wire x1="-96.52" y1="5.08" x2="-96.52" y2="0" width="0.1524" layer="91"/> +<pinref part="SUPPLY209" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="C206" gate="G$1" pin="2"/> +<wire x1="-86.36" y1="5.08" x2="-86.36" y2="0" width="0.1524" layer="91"/> +<pinref part="SUPPLY210" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="R69" gate="G$1" pin="1"/> +<wire x1="7.62" y1="-12.7" x2="7.62" y2="-15.24" width="0.1524" layer="91"/> +<pinref part="SUPPLY214" gate="GND" pin="GND"/> +</segment> +<segment> +<pinref part="SUPPLY215" gate="GND" pin="GND"/> +<wire x1="25.4" y1="-15.24" x2="25.4" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="C209" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY216" gate="GND" pin="GND"/> +<wire x1="38.1" y1="-15.24" x2="38.1" y2="-7.62" width="0.1524" layer="91"/> +<pinref part="C210" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY217" gate="GND" pin="GND"/> +<pinref part="R70" gate="G$1" pin="1"/> +<wire x1="50.8" y1="-15.24" x2="50.8" y2="-10.16" width="0.1524" layer="91"/> +</segment> +</net> +<net name="FPGA_VCCINT_1V0" class="0"> +<segment> +<wire x1="63.5" y1="15.24" x2="68.58" y2="15.24" width="0.1524" layer="91"/> +<label x="68.58" y="15.24" size="1.778" layer="95" xref="yes"/> +<pinref part="FB7" gate="G$1" pin="2"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<label x="-99.06" y="20.32" size="1.778" layer="95"/> +<wire x1="-101.6" y1="15.24" x2="-101.6" y2="20.32" width="0.1524" layer="91"/> +<pinref part="P+80" gate="VCC" pin="VCC"/> +<wire x1="-55.88" y1="10.16" x2="-55.88" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-55.88" y1="15.24" x2="-50.8" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-50.8" y1="10.16" x2="-55.88" y2="10.16" width="0.1524" layer="91"/> +<wire x1="-55.88" y1="15.24" x2="-71.12" y2="15.24" width="0.1524" layer="91"/> +<junction x="-55.88" y="15.24"/> +<pinref part="C205" gate="G$1" pin="1"/> +<wire x1="-71.12" y1="15.24" x2="-86.36" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-86.36" y1="15.24" x2="-96.52" y2="15.24" width="0.1524" layer="91"/> +<wire x1="-96.52" y1="12.7" x2="-96.52" y2="15.24" width="0.1524" layer="91"/> +<pinref part="C206" gate="G$1" pin="1"/> +<wire x1="-86.36" y1="12.7" x2="-86.36" y2="15.24" width="0.1524" layer="91"/> +<junction x="-86.36" y="15.24"/> +<pinref part="R66" gate="G$1" pin="2"/> +<wire x1="-71.12" y1="12.7" x2="-71.12" y2="15.24" width="0.1524" layer="91"/> +<junction x="-71.12" y="15.24"/> +<pinref part="U16" gate="G$1" pin="PVIN"/> +<pinref part="U16" gate="G$1" pin="AVIN"/> +<wire x1="-101.6" y1="15.24" x2="-96.52" y2="15.24" width="0.1524" layer="91"/> +<junction x="-96.52" y="15.24"/> +</segment> +</net> +<net name="POK_VCCINT" class="0"> +<segment> +<wire x1="-7.62" y1="-53.34" x2="0" y2="-53.34" width="0.1524" layer="91"/> +<label x="0" y="-53.34" size="1.778" layer="95" xref="yes"/> +<pinref part="U16" gate="G$1" pin="POK"/> +</segment> +</net> +<net name="N$45" class="0"> +<segment> +<wire x1="-50.8" y1="-53.34" x2="-55.88" y2="-53.34" width="0.1524" layer="91"/> +<pinref part="C207" gate="G$1" pin="1"/> +<pinref part="U16" gate="G$1" pin="SS"/> +</segment> +</net> +<net name="N$46" class="0"> +<segment> +<pinref part="R66" gate="G$1" pin="1"/> +<wire x1="-50.8" y1="0" x2="-71.12" y2="0" width="0.1524" layer="91"/> +<wire x1="-71.12" y1="0" x2="-71.12" y2="2.54" width="0.1524" layer="91"/> +<pinref part="U16" gate="G$1" pin="EN_PB"/> +</segment> +</net> +<net name="PWR_ENA_VCCINT" class="0"> +<segment> +<wire x1="-50.8" y1="5.08" x2="-60.96" y2="5.08" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="5.08" x2="-60.96" y2="27.94" width="0.1524" layer="91"/> +<wire x1="-60.96" y1="27.94" x2="-73.66" y2="27.94" width="0.1524" layer="91"/> +<label x="-73.66" y="27.94" size="1.778" layer="95" rot="R180" xref="yes"/> +<pinref part="U16" gate="G$1" pin="ENABLE"/> +</segment> +</net> +<net name="N$47" class="0"> +<segment> +<pinref part="U16" gate="G$1" pin="VSENSE"/> +<wire x1="-7.62" y1="-15.24" x2="-2.54" y2="-15.24" width="0.1524" layer="91"/> +<wire x1="-2.54" y1="-15.24" x2="-2.54" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R67" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$48" class="0"> +<segment> +<wire x1="-2.54" y1="-2.54" x2="-2.54" y2="15.24" width="0.1524" layer="91"/> +<pinref part="U16" gate="G$1" pin="VOUT"/> +<wire x1="-2.54" y1="15.24" x2="-7.62" y2="15.24" width="0.1524" layer="91"/> +<junction x="-2.54" y="15.24"/> +<wire x1="-2.54" y1="15.24" x2="7.62" y2="15.24" width="0.1524" layer="91"/> +<pinref part="R68" gate="G$1" pin="2"/> +<wire x1="7.62" y1="12.7" x2="7.62" y2="15.24" width="0.1524" layer="91"/> +<wire x1="7.62" y1="15.24" x2="15.24" y2="15.24" width="0.1524" layer="91"/> +<junction x="7.62" y="15.24"/> +<pinref part="C208" gate="G$1" pin="1"/> +<wire x1="15.24" y1="15.24" x2="15.24" y2="12.7" width="0.1524" layer="91"/> +<wire x1="25.4" y1="0" x2="25.4" y2="15.24" width="0.1524" layer="91"/> +<wire x1="25.4" y1="15.24" x2="15.24" y2="15.24" width="0.1524" layer="91"/> +<junction x="15.24" y="15.24"/> +<wire x1="38.1" y1="0" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<wire x1="38.1" y1="15.24" x2="25.4" y2="15.24" width="0.1524" layer="91"/> +<junction x="25.4" y="15.24"/> +<pinref part="R70" gate="G$1" pin="2"/> +<wire x1="50.8" y1="0" x2="50.8" y2="15.24" width="0.1524" layer="91"/> +<wire x1="50.8" y1="15.24" x2="38.1" y2="15.24" width="0.1524" layer="91"/> +<junction x="38.1" y="15.24"/> +<pinref part="FB7" gate="G$1" pin="1"/> +<wire x1="53.34" y1="15.24" x2="50.8" y2="15.24" width="0.1524" layer="91"/> +<junction x="50.8" y="15.24"/> +<pinref part="R67" gate="G$1" pin="2"/> +<pinref part="C209" gate="G$1" pin="1"/> +<pinref part="C210" gate="G$1" pin="1"/> +</segment> +</net> +<net name="N$49" class="0"> +<segment> +<pinref part="U16" gate="G$1" pin="VFB"/> +<wire x1="-7.62" y1="0" x2="7.62" y2="0" width="0.1524" layer="91"/> +<pinref part="R68" gate="G$1" pin="1"/> +<wire x1="7.62" y1="0" x2="7.62" y2="2.54" width="0.1524" layer="91"/> +<pinref part="R69" gate="G$1" pin="2"/> +<wire x1="7.62" y1="0" x2="7.62" y2="-2.54" width="0.1524" layer="91"/> +<junction x="7.62" y="0"/> +<wire x1="7.62" y1="0" x2="15.24" y2="0" width="0.1524" layer="91"/> +<pinref part="C208" gate="G$1" pin="2"/> +<wire x1="15.24" y1="0" x2="15.24" y2="5.08" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +<sheet> +<description>FPGA power sequencing</description> +<plain> +<text x="73.66" y="50.8" size="1.778" layer="91">*) Recommended power-up sequence: + +1) VCCINT + +2) VCCAUX + +3) VCCO + +RC network values are preliminary, +should be tweaked after experiments +</text> +<text x="-27.94" y="43.18" size="1.778" layer="91">---></text> +<text x="91.44" y="43.18" size="1.778" layer="91">---></text> +<text x="-116.84" y="-43.18" size="1.778" layer="91">---></text> +<text x="-2.54" y="-43.18" size="1.778" layer="91">---></text> +<text x="33.02" y="-60.96" size="1.778" layer="91">*) "Power OK" LED, should be of green color</text> +<text x="91.44" y="-71.12" size="1.9304" layer="94">FPGA power sequencing</text> +</plain> +<instances> +<instance part="FRAME26" gate="G$1" x="-124.46" y="-91.44"/> +<instance part="R72" gate="G$1" x="-78.74" y="43.18"> +<attribute name="TOLERANCE" x="-78.74" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D2" gate="G$1" x="-78.74" y="53.34" rot="MR0"/> +<instance part="SUPPLY218" gate="GND" x="-68.58" y="22.86"/> +<instance part="R75" gate="G$1" x="15.24" y="53.34" rot="R90"> +<attribute name="TOLERANCE" x="15.24" y="53.34" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R76" gate="G$1" x="35.56" y="43.18"> +<attribute name="TOLERANCE" x="35.56" y="43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D4" gate="G$1" x="35.56" y="53.34" rot="MR0"/> +<instance part="SUPPLY220" gate="GND" x="45.72" y="22.86"/> +<instance part="R73" gate="G$1" x="-76.2" y="-33.02" rot="R90"> +<attribute name="TOLERANCE" x="-76.2" y="-33.02" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="R74" gate="G$1" x="-55.88" y="-43.18"> +<attribute name="TOLERANCE" x="-55.88" y="-43.18" size="1.778" layer="96" display="off"/> +</instance> +<instance part="D3" gate="G$1" x="-55.88" y="-33.02" rot="MR0"/> +<instance part="SUPPLY219" gate="GND" x="-45.72" y="-63.5"/> +<instance part="R77" gate="G$1" x="40.64" y="-22.86" rot="R90"> +<attribute name="TOLERANCE" x="40.64" y="-22.86" size="1.778" layer="96" rot="R90" display="off"/> +</instance> +<instance part="Q6" gate="G$1" x="60.96" y="-40.64"/> +<instance part="SUPPLY221" gate="GND" x="71.12" y="-50.8"/> +<instance part="LED18" gate="G$1" x="71.12" y="-30.48" rot="MR0"/> +<instance part="R78" gate="G$1" x="71.12" y="-20.32" rot="MR90"> +<attribute name="TOLERANCE" x="71.12" y="-20.32" size="1.778" layer="96" rot="MR90" display="off"/> +</instance> +<instance part="C211" gate="G$1" x="-68.58" y="35.56"> +<attribute name="DIELECTRIC" x="-68.58" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-68.58" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-68.58" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C212" gate="G$1" x="-45.72" y="-50.8"> +<attribute name="DIELECTRIC" x="-45.72" y="-50.8" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="-45.72" y="-50.8" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="-45.72" y="-50.8" size="1.778" layer="96" display="off"/> +</instance> +<instance part="C213" gate="G$1" x="45.72" y="35.56"> +<attribute name="DIELECTRIC" x="45.72" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="RATED_VOLTAGE" x="45.72" y="35.56" size="1.778" layer="96" display="off"/> +<attribute name="TOLERANCE" x="45.72" y="35.56" size="1.778" layer="96" display="off"/> +</instance> +<instance part="P+81" gate="VCC" x="-109.22" y="66.04" smashed="yes"/> +<instance part="P+82" gate="VCC" x="-76.2" y="-17.78" smashed="yes"/> +<instance part="P+84" gate="VCC" x="40.64" y="-2.54" smashed="yes"/> +<instance part="P+83" gate="VCC" x="15.24" y="66.04" smashed="yes"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="1"> +<segment> +<pinref part="SUPPLY218" gate="GND" pin="GND"/> +<wire x1="-68.58" y1="25.4" x2="-68.58" y2="30.48" width="0.1524" layer="91"/> +<pinref part="C211" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY220" gate="GND" pin="GND"/> +<wire x1="45.72" y1="25.4" x2="45.72" y2="30.48" width="0.1524" layer="91"/> +<pinref part="C213" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="SUPPLY219" gate="GND" pin="GND"/> +<wire x1="-45.72" y1="-60.96" x2="-45.72" y2="-55.88" width="0.1524" layer="91"/> +<pinref part="C212" gate="G$1" pin="2"/> +</segment> +<segment> +<pinref part="Q6" gate="G$1" pin="S"/> +<wire x1="66.04" y1="-43.18" x2="71.12" y2="-43.18" width="0.1524" layer="91"/> +<pinref part="SUPPLY221" gate="GND" pin="GND"/> +<wire x1="71.12" y1="-43.18" x2="71.12" y2="-48.26" width="0.1524" layer="91"/> +</segment> +</net> +<net name="VCC_5V0" class="0"> +<segment> +<label x="-106.68" y="63.5" size="1.778" layer="95"/> +<wire x1="-109.22" y1="43.18" x2="-109.22" y2="63.5" width="0.1524" layer="91"/> +<pinref part="P+81" gate="VCC" pin="VCC"/> +<pinref part="R72" gate="G$1" pin="1"/> +<wire x1="-83.82" y1="43.18" x2="-88.9" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-88.9" y1="43.18" x2="-88.9" y2="53.34" width="0.1524" layer="91"/> +<pinref part="D2" gate="G$1" pin="C"/> +<wire x1="-88.9" y1="53.34" x2="-81.28" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-109.22" y1="43.18" x2="-88.9" y2="43.18" width="0.1524" layer="91"/> +<junction x="-88.9" y="43.18"/> +</segment> +<segment> +<label x="-73.66" y="-20.32" size="1.778" layer="95"/> +<pinref part="P+82" gate="VCC" pin="VCC"/> +<pinref part="R73" gate="G$1" pin="2"/> +<wire x1="-76.2" y1="-27.94" x2="-76.2" y2="-20.32" width="0.1524" layer="91"/> +</segment> +<segment> +<label x="43.18" y="-5.08" size="1.778" layer="95"/> +<pinref part="P+84" gate="VCC" pin="VCC"/> +<pinref part="R77" gate="G$1" pin="2"/> +<wire x1="40.64" y1="-12.7" x2="40.64" y2="-5.08" width="0.1524" layer="91"/> +<wire x1="40.64" y1="-17.78" x2="40.64" y2="-12.7" width="0.1524" layer="91"/> +<pinref part="R78" gate="G$1" pin="2"/> +<wire x1="71.12" y1="-15.24" x2="71.12" y2="-12.7" width="0.1524" layer="91"/> +<wire x1="71.12" y1="-12.7" x2="40.64" y2="-12.7" width="0.1524" layer="91"/> +<junction x="40.64" y="-12.7"/> +</segment> +<segment> +<label x="17.78" y="63.5" size="1.778" layer="95"/> +<pinref part="P+83" gate="VCC" pin="VCC"/> +<pinref part="R75" gate="G$1" pin="2"/> +<wire x1="15.24" y1="58.42" x2="15.24" y2="63.5" width="0.1524" layer="91"/> +</segment> +</net> +<net name="PWR_ENA_VCCAUX" class="0"> +<segment> +<wire x1="40.64" y1="43.18" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<label x="68.58" y="43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="R76" gate="G$1" pin="2"/> +<wire x1="45.72" y1="43.18" x2="68.58" y2="43.18" width="0.1524" layer="91"/> +<wire x1="45.72" y1="38.1" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<junction x="45.72" y="43.18"/> +<pinref part="D4" gate="G$1" pin="A"/> +<wire x1="45.72" y1="53.34" x2="38.1" y2="53.34" width="0.1524" layer="91"/> +<wire x1="45.72" y1="53.34" x2="45.72" y2="43.18" width="0.1524" layer="91"/> +<pinref part="C213" gate="G$1" pin="1"/> +</segment> +</net> +<net name="POK_VCCINT" class="0"> +<segment> +<wire x1="-5.08" y1="43.18" x2="15.24" y2="43.18" width="0.1524" layer="91"/> +<pinref part="R75" gate="G$1" pin="1"/> +<wire x1="15.24" y1="43.18" x2="15.24" y2="48.26" width="0.1524" layer="91"/> +<label x="-5.08" y="43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="R76" gate="G$1" pin="1"/> +<wire x1="30.48" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<wire x1="25.4" y1="43.18" x2="25.4" y2="53.34" width="0.1524" layer="91"/> +<pinref part="D4" gate="G$1" pin="C"/> +<wire x1="25.4" y1="53.34" x2="33.02" y2="53.34" width="0.1524" layer="91"/> +<wire x1="15.24" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/> +<junction x="15.24" y="43.18"/> +<junction x="25.4" y="43.18"/> +</segment> +</net> +<net name="PWR_ENA_VCCO" class="0"> +<segment> +<wire x1="-45.72" y1="-43.18" x2="-21.59" y2="-43.18" width="0.1524" layer="91"/> +<label x="-21.59" y="-43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="D3" gate="G$1" pin="A"/> +<wire x1="-45.72" y1="-33.02" x2="-53.34" y2="-33.02" width="0.1524" layer="91"/> +<wire x1="-45.72" y1="-43.18" x2="-45.72" y2="-33.02" width="0.1524" layer="91"/> +<pinref part="R74" gate="G$1" pin="2"/> +<wire x1="-50.8" y1="-43.18" x2="-45.72" y2="-43.18" width="0.1524" layer="91"/> +<junction x="-45.72" y="-43.18"/> +<wire x1="-45.72" y1="-48.26" x2="-45.72" y2="-43.18" width="0.1524" layer="91"/> +<pinref part="C212" gate="G$1" pin="1"/> +</segment> +</net> +<net name="PWR_ENA_VCCINT" class="0"> +<segment> +<pinref part="D2" gate="G$1" pin="A"/> +<wire x1="-76.2" y1="53.34" x2="-68.58" y2="53.34" width="0.1524" layer="91"/> +<wire x1="-68.58" y1="53.34" x2="-68.58" y2="43.18" width="0.1524" layer="91"/> +<pinref part="R72" gate="G$1" pin="2"/> +<wire x1="-68.58" y1="43.18" x2="-73.66" y2="43.18" width="0.1524" layer="91"/> +<wire x1="-68.58" y1="38.1" x2="-68.58" y2="43.18" width="0.1524" layer="91"/> +<junction x="-68.58" y="43.18"/> +<wire x1="-68.58" y1="43.18" x2="-45.72" y2="43.18" width="0.1524" layer="91"/> +<label x="-45.72" y="43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="C211" gate="G$1" pin="1"/> +</segment> +</net> +<net name="POK_VCCAUX" class="0"> +<segment> +<wire x1="-95.25" y1="-43.18" x2="-76.2" y2="-43.18" width="0.1524" layer="91"/> +<pinref part="R73" gate="G$1" pin="1"/> +<wire x1="-76.2" y1="-43.18" x2="-76.2" y2="-38.1" width="0.1524" layer="91"/> +<label x="-95.25" y="-43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="R74" gate="G$1" pin="1"/> +<wire x1="-60.96" y1="-43.18" x2="-66.04" y2="-43.18" width="0.1524" layer="91"/> +<wire x1="-66.04" y1="-43.18" x2="-66.04" y2="-33.02" width="0.1524" layer="91"/> +<pinref part="D3" gate="G$1" pin="C"/> +<wire x1="-66.04" y1="-33.02" x2="-58.42" y2="-33.02" width="0.1524" layer="91"/> +<wire x1="-76.2" y1="-43.18" x2="-66.04" y2="-43.18" width="0.1524" layer="91"/> +<junction x="-76.2" y="-43.18"/> +<junction x="-66.04" y="-43.18"/> +</segment> +</net> +<net name="POK_VCCO" class="0"> +<segment> +<wire x1="21.59" y1="-43.18" x2="40.64" y2="-43.18" width="0.1524" layer="91"/> +<pinref part="R77" gate="G$1" pin="1"/> +<wire x1="40.64" y1="-43.18" x2="40.64" y2="-27.94" width="0.1524" layer="91"/> +<label x="21.59" y="-43.18" size="1.778" layer="95" rot="R270" xref="yes"/> +<pinref part="Q6" gate="G$1" pin="G"/> +<wire x1="40.64" y1="-43.18" x2="55.88" y2="-43.18" width="0.1524" layer="91"/> +<junction x="40.64" y="-43.18"/> +</segment> +</net> +<net name="N$50" class="0"> +<segment> +<pinref part="Q6" gate="G$1" pin="D"/> +<wire x1="66.04" y1="-38.1" x2="71.12" y2="-38.1" width="0.1524" layer="91"/> +<pinref part="LED18" gate="G$1" pin="C"/> +<wire x1="71.12" y1="-38.1" x2="71.12" y2="-35.56" width="0.1524" layer="91"/> +</segment> +</net> +<net name="N$51" class="0"> +<segment> +<pinref part="R78" gate="G$1" pin="1"/> +<pinref part="LED18" gate="G$1" pin="A"/> +<wire x1="71.12" y1="-25.4" x2="71.12" y2="-27.94" width="0.1524" layer="91"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +<compatibility> +<note version="6.3" minversion="6.2.2" severity="warning"> +Since Version 6.2.2 text objects can contain more than one line, +which will not be processed correctly with this version. +</note> +</compatibility> +</eagle> |