doc/design - Design documentation

Age	Commit message (Collapse)	Author
2015-05-05	Updated estimates with real values for RSA/modexp core. Fixed errors in ↵	Joachim Strömbergson
	calculations and updated numbers for available resources in Xilinx FPGAs.
2015-04-13	Updated Alpha board drawing with minor nits: Changed from Rx to Tx on serial ↵	Joachim Strömbergson
	port between Main CPU and Tamper CPU so that we have both Rx and Tx.
2015-03-25	Update of Alpha board drawing to change host and management interfaces to ↵	Joachim Strömbergson
	UART with updated interface chips. Updated EIM interface to 16 bit address bus. Updated PSU primary rail info. Added symbols for CPU clock and reset blocks. Added info about Tamper MCU clocking.
2015-03-19	Added info about FPGA config memory.	Joachim Strömbergson

2015-03-19	Update after feedback. Added battery and crystal to to the RTC.	Joachim Strömbergson

2015-03-19	Update after feedback. Fixed labels on wires and repositioned USB-SPI ↵	Joachim Strömbergson
	trasnscievers.
2015-03-19	Adding Alpha board drawing. This version fixes a few nits.	Joachim Strömbergson

2015-03-17	minor updates	Jakob Schlyter

2015-03-17	add CKM_ECDSA_SHA256	Jakob Schlyter

2015-03-14	export to PDF	Jakob Schlyter

2015-03-14	cleanup	Jakob Schlyter

2015-03-14	add alpha board overview based on design from Fredrik and Joachim	Jakob Schlyter

2015-03-14	some early sketches on application aware signing	Jakob Schlyter

2015-03-14	overview of HSM internal keys and how they relate	Jakob Schlyter

2015-03-13	Adding FPGA resource tracker and estimates document.	Joachim Strömbergson

2015-01-28	update based on discussion with Joachim	Jakob Schlyter

2015-01-11	fix typo	Jakob Schlyter

2015-01-11	clarify, show security boundry	Jakob Schlyter

2015-01-10	add annotation layer and mention the entropy sources	Jakob Schlyter

2015-01-09	add RTC and some other stuff	Jakob Schlyter

2015-01-09	sync	Jakob Schlyter

2015-01-09	initial draft from Stockholm meeting 2015-01-08	Jakob Schlyter