aboutsummaryrefslogtreecommitdiff
path: root/src/tb/tb_keywrap.v
diff options
context:
space:
mode:
Diffstat (limited to 'src/tb/tb_keywrap.v')
-rw-r--r--src/tb/tb_keywrap.v444
1 files changed, 407 insertions, 37 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index 1f1dabf..fb02792 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -39,9 +39,10 @@
module tb_keywrap();
- parameter DEBUG = 0;
- parameter DUMP_TOP = 0;
- parameter DUMP_CORE = 0;
+ parameter DEBUG = 0;
+ parameter DUMP_TOP = 1;
+ parameter DUMP_CORE = 1;
+ parameter DUMP_TIMEOUT = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
@@ -51,38 +52,42 @@ module tb_keywrap();
// API for the core.
- localparam ADDR_NAME0 = 8'h00;
- localparam ADDR_NAME1 = 8'h01;
- localparam ADDR_VERSION = 8'h02;
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
- localparam ADDR_CTRL = 8'h08;
- localparam CTRL_INIT_BIT = 0;
- localparam CTRL_NEXT_BIT = 1;
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+ localparam CTRL_ZEROISE_BIT = 2;
- localparam ADDR_STATUS = 8'h09;
- localparam STATUS_READY_BIT = 0;
- localparam STATUS_VALID_BIT = 1;
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+ localparam STATUS_LOADED_BIT = 2;
- localparam ADDR_CONFIG = 8'h0a;
- localparam CTRL_ENCDEC_BIT = 0;
- localparam CTRL_KEYLEN_BIT = 1;
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CTRL_ENCDEC_BIT = 0;
+ localparam CTRL_KEYLEN_BIT = 1;
- localparam ADDR_RLEN = 8'h0c;
- localparam ADDR_R_BANK = 8'h0d;
- localparam ADDR_A0 = 8'h0e;
- localparam ADDR_A1 = 8'h0f;
+ localparam ADDR_TIMEOUT = 8'h0b;
- localparam ADDR_KEY0 = 8'h10;
- localparam ADDR_KEY1 = 8'h11;
- localparam ADDR_KEY2 = 8'h12;
- localparam ADDR_KEY3 = 8'h13;
- localparam ADDR_KEY4 = 8'h14;
- localparam ADDR_KEY5 = 8'h15;
- localparam ADDR_KEY6 = 8'h16;
- localparam ADDR_KEY7 = 8'h17;
+ localparam ADDR_RLEN = 8'h0c;
+ localparam ADDR_R_BANK = 8'h0d;
+ localparam ADDR_A0 = 8'h0e;
+ localparam ADDR_A1 = 8'h0f;
- localparam ADDR_R_DATA0 = 8'h80;
- localparam ADDR_R_DATA127 = 8'hff;
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY1 = 8'h11;
+ localparam ADDR_KEY2 = 8'h12;
+ localparam ADDR_KEY3 = 8'h13;
+ localparam ADDR_KEY4 = 8'h14;
+ localparam ADDR_KEY5 = 8'h15;
+ localparam ADDR_KEY6 = 8'h16;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_R_DATA0 = 8'h80;
+ localparam ADDR_R_DATA127 = 8'hff;
//----------------------------------------------------------------
@@ -302,8 +307,21 @@ module tb_keywrap();
$display("keywrap_core_ctrl_reg = 0x%0x", dut.core.keywrap_core_ctrl_reg);
$display("keywrap_core_ctrl_new = 0x%0x", dut.core.keywrap_core_ctrl_new);
$display("keywrap_core_ctrl_we = 0x%0x", dut.core.keywrap_core_ctrl_we);
+ $display("");
end
+ if (DUMP_TIMEOUT)
+ begin
+ $display("timeout state:");
+ $display("api_timeout_reg = 0x%04x api_timeout_we = 0x%x", dut.timeout_reg, dut.timeout_we);
+ $display("timeout_delay = 0x%04x timeout = 0x%x ping = 0x%x zeroise = 0x%x loaded = 0x%x",
+ dut.core.timeout_delay, dut.core.timeout, dut.core.ping, dut.core.zeroise, dut.core.loaded);
+ $display("key_timeout_ctr_reg = 0x%04x key_timeout_ctr_new = 0x%04x key_timeout_ctr_we = 0x%x",
+ dut.core.key_timeout_ctr_reg, dut.core.key_timeout_ctr_new, dut.core.key_timeout_ctr_we);
+ $display("key_timeout = 0x%x key_timeout_ctr_we = 0x%x key_timeout_ctr_set = 0x%x key_timeout_ctr_dec = 0x%x",
+ dut.core.key_timeout, dut.core.key_timeout_ctr_we, dut.core.key_timeout_ctr_set, dut.core.key_timeout_ctr_dec);
+
+ end
$display("");
$display("");
end
@@ -448,16 +466,11 @@ module tb_keywrap();
write_word(ADDR_A1, 32'h0000001f);
- $display("* Dumping state and mem after data write and A words.");
+ $display("* Dumping state and mem after write of data A words, but before wrap processing.");
dump_dut_state();
dump_mem(6);
-
- $display("* Contents of memory and dut before wrap processing:");
- dump_mem(6);
-
-
// Start wrapping and wait for wrap to complete.
$display("* Trying to start processing.");
write_word(ADDR_CTRL, 32'h00000002);
@@ -1065,7 +1078,6 @@ module tb_keywrap();
endtask // test_kwp_ad_128_2
-
//----------------------------------------------------------------
// test_big_wrap_256
// Implements wrap test with a huge (16 kB+) data object
@@ -1154,6 +1166,360 @@ module tb_keywrap();
//----------------------------------------------------------------
+ // test_zeroise1
+ // Test the auto_zeroise functionality. We test that:
+ // 1. We can init a key and have it be auto zeroised.
+ //----------------------------------------------------------------
+ task test_zeroise1;
+ begin : test_zeroise1
+
+ $display("** TC test_zeroise1 START.");
+ $display("** Test of auto zeroise.");
+
+ tc_ctr = tc_ctr + 1;
+
+ // Write key and keylength, we also want to encrypt/wrap.
+ write_word(ADDR_KEY0, 32'h55aa55aa);
+ write_word(ADDR_KEY1, 32'h55aa55aa);
+ write_word(ADDR_KEY2, 32'h55aa55aa);
+ write_word(ADDR_KEY3, 32'h55aa55aa);
+ write_word(ADDR_KEY4, 32'h55aa55aa);
+ write_word(ADDR_KEY5, 32'h55aa55aa);
+ write_word(ADDR_KEY6, 32'h55aa55aa);
+ write_word(ADDR_KEY7, 32'h55aa55aa);
+ write_word(ADDR_CONFIG, 32'h00000003);
+
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ // Set the key timeout to 0xdeadbeef cycles.
+ write_word(ADDR_TIMEOUT, 32'hdeadbeef);
+ read_word(ADDR_TIMEOUT);
+ if (read_data != 32'hdeadbeef)
+ begin
+ error_ctr = error_ctr + 1;
+ $display("Error. Timeout value = 0x%04x, expected 0xdeadbeef", read_data);
+ end
+
+ // Display contents in key expansion register 2.
+ $display("Contents in key_mem[2] before init: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ // Initialize the AES engine (to expand the key).
+ // Wait for init to complete.
+ $display("* Initializing.");
+ write_word(ADDR_CTRL, 32'h00000001);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Init done.");
+
+ // Display contents in key expansion register 2 again.
+ $display("Contents in key_mem[2] after init: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ // Check if key is loaded, according to the loaded flag.
+ read_word(ADDR_STATUS);
+ $display("Status register: 0b%032b", read_data);
+
+ // Display the timeout counter a few times.
+ $display("Status of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Status of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Status timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Status of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ // Display contents in one of the key expansion registers
+ $display("Contents in key_mem[2]: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ // Set the key timeout to 16 cycles.
+ // Read status to perform ping.
+ $display("Setting the timeout to 0x10 cycles and checking status.");
+ write_word(ADDR_TIMEOUT, 32'h00000010);
+ read_word(ADDR_STATUS);
+ #(CLK_PERIOD);
+ read_word(ADDR_STATUS);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+
+ $display("Waiting 0x40 cycles.");
+ #(64 * CLK_PERIOD);
+
+
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+ $display("Status of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ // Display contents in key expansion register 2 again.
+ $display("Contents in key_mem[2] after timeout: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ if (dut.core.aes.keymem.key_mem[2] != 128'h62636363626363636263636362636363)
+ begin
+ error_ctr = error_ctr + 1;
+ $display("Error. Contents in key_mem[2]: 0x%016x, expected 0x62636363626363636263636362636363",
+ dut.core.aes.keymem.key_mem[2]);
+ end
+
+ $display("** TC test_zeroise1 END.\n");
+ end
+ endtask // test_zeroise1
+
+
+ //----------------------------------------------------------------
+ // test_zeroise2
+ // Test the auto_zeroise functionality. We test that:
+ // 2. We can init a key and keep it alive.
+ //----------------------------------------------------------------
+ task test_zeroise2;
+ begin : test_zeroise2
+ integer i;
+ integer err;
+
+ err = 0;
+
+ $display("** TC test_zeroise2 START.");
+ $display("** Test of key keep alive..");
+
+ tc_ctr = tc_ctr + 1;
+
+ // Write key and keylength, we also want to encrypt/wrap.
+ write_word(ADDR_KEY0, 32'haa55aa55);
+ write_word(ADDR_KEY1, 32'haa55aa55);
+ write_word(ADDR_KEY2, 32'haa55aa55);
+ write_word(ADDR_KEY3, 32'haa55aa55);
+ write_word(ADDR_KEY4, 32'haa55aa55);
+ write_word(ADDR_KEY5, 32'haa55aa55);
+ write_word(ADDR_KEY6, 32'haa55aa55);
+ write_word(ADDR_KEY7, 32'haa55aa55);
+ write_word(ADDR_CONFIG, 32'h00000003);
+
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ // Initialize the AES engine (to expand the key).
+ // Wait for init to complete.
+ // Note, not actually needed to wait. We can write R data during init.
+ $display("* Initializing.");
+ write_word(ADDR_CTRL, 32'h00000001);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Init done.");
+
+ // Display contents in key expansion register 2 again.
+ $display("Contents of the key_mem[2] after init: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ // Check if key is loaded, according to the loaded flag.
+ read_word(ADDR_STATUS);
+ $display("Status register: 0b%032b", read_data);
+
+ // Set the key timeout to 256 cycles.
+ $display("Setting timout to 16 cycles and then we keep it alive.");
+ write_word(ADDR_TIMEOUT, 32'h00000010);
+
+ // Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ // Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ $display("Contents of the key_mem[2]: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ // Display the timeout counter a few times.
+ // And then read status. Which should trigger reset of timout.
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(2 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+
+ $display("We now allow the timer to expire");
+ #(40 * CLK_PERIOD);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ $display("Contents of the key_mem[2]: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ if (dut.core.aes.keymem.key_mem[2] != 128'h62636363626363636263636362636363)
+ begin
+ error_ctr = error_ctr + 1;
+ $display("Error. Contents in key_mem[2]: 0x%016x, expected 0x62636363626363636263636362636363",
+ dut.core.aes.keymem.key_mem[2]);
+ end
+
+ $display("** TC test_zeroise2 END.\n");
+ end
+ endtask // test_zeroise2
+
+
+ //----------------------------------------------------------------
+ // test_zeroise3
+ // Test the auto_zeroise functionality. We test that:
+ // 3. We can init a key and the force zeroisation.
+ //----------------------------------------------------------------
+ task test_zeroise3;
+ begin : test_zeroise3
+ integer i;
+ integer err;
+
+ err = 0;
+
+ $display("** TC test_zeroise3 START.");
+ $display("** Test of forceed zeroisation.");
+
+ tc_ctr = tc_ctr + 1;
+
+ // Write key and keylength, we also want to encrypt/wrap.
+ write_word(ADDR_KEY0, 32'h13371337);
+ write_word(ADDR_KEY1, 32'h13371337);
+ write_word(ADDR_KEY2, 32'h13371337);
+ write_word(ADDR_KEY3, 32'h13371337);
+ write_word(ADDR_KEY4, 32'h13371337);
+ write_word(ADDR_KEY5, 32'h13371337);
+ write_word(ADDR_KEY6, 32'h13371337);
+ write_word(ADDR_KEY7, 32'h13371337);
+ write_word(ADDR_CONFIG, 32'h13371337);
+
+ // Initialize the AES engine (to expand the key).
+ // Wait for init to complete.
+ $display("* Initializing.");
+ write_word(ADDR_CTRL, 32'h00000001);
+ #(2 * CLK_PERIOD);
+ wait_ready();
+ $display("* Init done.");
+
+ // Check if key is loaded, according to the loaded flag.
+ read_word(ADDR_STATUS);
+ $display("Status register: 0b%032b", read_data);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ // Display contents in key expansion register 2.
+ $display("Contents of the key_mem[2] after init: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+ #(40 * CLK_PERIOD);
+ $display("Contents of timeout counter: 0x%04x",
+ dut.core.key_timeout_ctr_reg);
+
+ $display("* Trigger zeroisation.");
+ write_word(ADDR_CTRL, 32'h00000004);
+ #(40 * CLK_PERIOD);
+ read_word(ADDR_STATUS);
+ $display("Status register: 0x%032b", read_data);
+
+ $display("Contents of the API key registers:");
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("0x%04x 0x%04x 0x%04x 0x%04x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
+
+ // Display contents in key expansion register 2.
+ $display("Contents of the key_mem[2] after zeroisation: 0x%016x",
+ dut.core.aes.keymem.key_mem[2]);
+
+ if (dut.core.aes.keymem.key_mem[2] != 128'h62636363626363636263636362636363)
+ begin
+ error_ctr = error_ctr + 1;
+ $display("Error. Contents in key_mem[2]: 0x%016x, expected 0x62636363626363636263636362636363",
+ dut.core.aes.keymem.key_mem[2]);
+ end
+
+ $display("** TC test_zerois3 END.\n");
+ end
+ endtask // test_zeroise3
+
+
+ //----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
@@ -1178,9 +1544,13 @@ module tb_keywrap();
test_kwp_ad_128_1();
test_kwp_ae_128_2();
test_kwp_ad_128_2();
-
test_big_wrap_256();
+ reset_dut();
+ test_zeroise1();
+ test_zeroise2();
+ test_zeroise3();
+
display_test_results();
$display("");
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 02:40:48 +0000