src - core/rng/trng - True Random Number Generator core implemented in Verilog

index : core/rng/trng

True Random Number Generator core implemented in Verilog

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Mode	Name	Size
d---------	rtl	127	log plain
d---------	tb	116	log plain

generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 18:01:41 +0000