core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2019-02-08	(1) Silenced linter by adding default case states. (2) Fixed minor nits in ↵cleanup	Joachim Strömbergson
	help part of Makefile.
2019-01-25	Added flags for building and linting source.	Joachim Strömbergson

2018-07-24	Removing files for building and using the TRNG with TerASIC D0-Nano board.	Joachim Strömbergson

2015-05-22	Adding target for linting the trng.	Joachim Strömbergson

2015-04-02	Added new sim target. Added cleanup of sim target.	Joachim Strömbergson

2015-04-01	Adding target for csprng output simulation target.	Joachim Strömbergson

2015-03-26	Updated the Makefile to match the new CT repo structure.	Joachim Strömbergson

2014-10-02	Adding Quartus project files to build trng for TerasIC DE0 Nano board. This ↵	Joachim Strömbergson
	also includes a prebuilt config file.
2014-09-26	Update of fake entropy sources used in simulation.	Joachim Strömbergson

2014-09-12	Updated Makefile to build the complete trng simulation target.	Joachim Strömbergson

2014-09-11	Adding compile and sim target for the mixer.	Joachim Strömbergson

2014-09-11	Adding makefile.	Joachim Strömbergson