core/rng/trng - True Random Number Generator core implemented in Verilog

Branch	Commit message	Author	Age
cleanup	(1) Silenced linter by adding default case states. (2) Fixed minor nits in he...	Joachim Strömbergson	6 years
master	(1) Fixed width definitions and cleaned up constants as part of checking that...	Joachim Strömbergson	6 years
new_mixer	Changed separate block register to reg array.	Joachim Strömbergson	7 years


Age	Commit message	Author
2019-02-08	(1) Silenced linter by adding default case states. (2) Fixed minor nits in he...cleanup	Joachim Strömbergson
2019-01-25	Added flags for building and linting source.	Joachim Strömbergson
2018-10-16	(1) Fixed width definitions and cleaned up constants as part of checking that...HEAD master	Joachim Strömbergson
2018-07-24	Removing files for building and using the TRNG with TerASIC D0-Nano board.	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-11-17	Harmonize status valid bit with other cores.	Paul Selkirk
2015-11-16	harmonize ctrl and status addresses with other cores	Paul Selkirk
2015-11-14	Merge branch 'config_core_selector'	Paul Selkirk
2015-10-05	(1) Minor cleanup. Removed unneeded code blocks and comments. (2) Moved debug...	Joachim Strömbergson
2015-10-05	(1) Changed API addresses for ctrl and status registers - HEADSUP: this might...	Joachim Strömbergson
[...]

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