core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-09-07	(1) Verified that reseeding works. (2) Added missing define for the reseed ↵	Joachim Strömbergson
	counter API address.
2015-09-07	Adding a new task that reads out a given number of random data words from ↵	Joachim Strömbergson
	the DUT.
2015-08-27	Removed the temporary task for generating seeds that is obsoleted by the ↵	Joachim Strömbergson
	seed process.
2015-08-27	Added process to generate need seeds with differentg patterns and ↵	Joachim Strömbergson
	communicate with the DUT using the seed update protocol. Minor nits.
2015-08-26	(1) Removed obsolete dump of values from the monitor. (2) Changed to using ↵	Joachim Strömbergson
	proper API write_word.
2015-08-26	Adding test case for verifying reseed functionality in csprng.	Joachim Strömbergson

2015-07-18	Read out all data in the fifo by looking at the syn flag. The fifo simulates ok.	Joachim Strömbergson

2015-07-18	Writing a new word into the fifo.	Joachim Strömbergson

2015-07-18	Adding task for reading words from the fifo. Reading out more than 16 words. ↵	Joachim Strömbergson
	Refactored w512 task.
2015-07-17	Adding more functionality to observe the fifo during test.	Joachim Strömbergson

2015-07-17	Adding task to dump fifo contents.	Joachim Strömbergson

2015-07-17	Adding more test functionality in the fifo testbench. Now we generates ↵	Joachim Strömbergson
	several 512-bit words fed into the fifo.
2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code ↵	Joachim Strömbergson
	and connected discard for fast restart of trng. (3) Added addresses for allowing API to write a known seed to allow test mode. (3) Fixed a number of minor issues during linting. (4) Fixed the csprng testbench to actually generate data as well as displaying the block stat counter.
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ↵	Joachim Strömbergson
	csprng data words. (2) Updated the testbench with better test vector generation.
2015-04-02	Fixed syntax and added init functionality for testing the dut.	Joachim Strömbergson

2015-04-01	Adding initial version of testbench for the csprng fifo.	Joachim Strömbergson

2015-04-01	Adding fake entropy providers to allow us to simulate the complete trng.	Joachim Strömbergson

2014-11-20	Updates of variable names to matched changed instance name and new fifo.	Joachim Strömbergson

2014-10-02	Updating testbenches to match new interfaces and use the api to read and ↵	Joachim Strömbergson
	write data.
2014-09-26	Removing old fake entropy source.	Joachim Strömbergson

2014-09-26	Removing old fake module for ring oscillator.	Joachim Strömbergson

2014-09-12	Adding testbench for the complete trng.	Joachim Strömbergson

2014-09-12	Adding fake modules for the three types of entropy sources to allow us to ↵	Joachim Strömbergson
	simulate with known values.
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ↵	Joachim Strömbergson
	Now it works.
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson

2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson