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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-02 15:06:43 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-02 15:06:43 +0200
commitdd11b056b46be8f5ee17147265c4ba7dd6b660f2 (patch)
tree4e6bb218cff991f2216dc06ec62842885d6960a1 /src/tb
parentd39bba7d54fd0fb1967e1870374b4127345d4f17 (diff)
Fixed syntax and added init functionality for testing the dut.
Diffstat (limited to 'src/tb')
-rw-r--r--src/tb/tb_csprng_fifo.v105
1 files changed, 30 insertions, 75 deletions
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index c0b45ec..c5e283e 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -81,41 +81,24 @@ module tb_csprng_fifo();
wire [31 : 0] tb_rnd_data;
reg tb_rnd_ack;
- reg tb_discard;
- reg tb_test_mode;
-
- wire tb_ready;
- wire tb_more_seed;
- wire tb_security_error;
- reg tb_seed_syn;
- reg [511 : 0] tb_seed_data;
- wire tb_seed_ack;
- wire [31: 0] tb_rnd_data;
- wire tb_rnd_syn;
- reg tb_rnd_ack;
-
- wire [7 : 0] tb_debug;
- reg tb_debug_update;
-
- reg [31 : 0] read_data;
-
+ integer i;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
- trng_csprng dut(
- .clk(tb_clk),
- .reset_n(tb_reset_n),
+ trng_csprng_fifo dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
- .csprng_data(tb_csprng_data),
- .csprng_data_valid(tb_csprng_data_valid),
- .discard(tb_discard),
- .more_data(tb_more_data),
+ .csprng_data(tb_csprng_data),
+ .csprng_data_valid(tb_csprng_data_valid),
+ .discard(tb_discard),
+ .more_data(tb_more_data),
- .rnd_syn(tb_rnd_syn),
- .rnd_data(tb_rnd_data),
- .rnd_ack(tb_rnd_ack)
- );
+ .rnd_syn(tb_rnd_syn),
+ .rnd_data(tb_rnd_data),
+ .rnd_ack(tb_rnd_ack)
+ );
//----------------------------------------------------------------
@@ -159,59 +142,28 @@ module tb_csprng_fifo();
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
+ $display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x",
+ tb_rnd_syn, tb_rnd_ack, tb_rnd_data);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
- // write_word()
+ // gen_csprng_data
//
- // Write the given word to the DUT using the DUT interface.
+ // Generate test data with distinct patterns as requested
+ // by the dut.
//----------------------------------------------------------------
- task write_word(input [11 : 0] address,
- input [31 : 0] word);
+ always @ (posedge tb_more_data)
begin
- if (DEBUG)
- begin
- $display("*** Writing 0x%08x to 0x%02x.", word, address);
- $display("");
- end
+ for (i = 0 ; i < 16 ; i = i + 1)
+ tb_csprng_data[i * 32 +: 32] = ~tb_csprng_data[i * 32 +: 32] + 32'h01010101;
- tb_address = address;
- tb_write_data = word;
- tb_cs = 1;
- tb_we = 1;
+ tb_csprng_data_valid = 1'b1;
#(2 * CLK_PERIOD);
- tb_cs = 0;
- tb_we = 0;
- end
- endtask // write_word
-
-
- //----------------------------------------------------------------
- // read_word()
- //
- // Read a data word from the given address in the DUT.
- // the word read will be available in the global variable
- // read_data.
- //----------------------------------------------------------------
- task read_word(input [11 : 0] address);
- begin
- tb_address = address;
- tb_cs = 1;
- tb_we = 0;
- #(CLK_PERIOD);
- read_data = tb_read_data;
- tb_cs = 0;
-
- if (DEBUG)
- begin
- $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
- $display("");
- end
+ tb_csprng_data_valid = 1'b0;
end
- endtask // read_word
//----------------------------------------------------------------
@@ -258,6 +210,8 @@ module tb_csprng_fifo();
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
+ integer i;
+
begin
cycle_ctr = 0;
error_ctr = 0;
@@ -272,12 +226,11 @@ module tb_csprng_fifo();
tb_write_data = 32'h00000000;
tb_discard = 0;
- tb_test_mode = 0;
+ tb_rnd_ack = 1;
+
+ for (i = 0 ; i < 16 ; i = i + 1)
+ tb_csprng_data[i * 32 +: 32] = 32'h01010101 << (i + 1);
- tb_seed_syn = 0;
- tb_seed_data = {16{32'h00000000}};
- tb_rnd_ack = 0;
- tb_debug_update = 0;
end
endtask // init_sim
@@ -299,6 +252,8 @@ module tb_csprng_fifo();
reset_dut();
dump_dut_state();
+ #(100000 * CLK_PERIOD)
+
display_test_results();
$display("");